SU1517031A1 - Processor to online memory interface - Google Patents

Abstract

The invention relates to computing and can be used in the construction of computers with improved performance. The aim of the invention is to improve the speed of the device. The device contains a register of 1 microinstructions, the first 2 and second 3 decoders, the element I 4, the first 5 and the second 6 triggers, the first to the fourth elements are NOT 7-10, the third trigger is 11, from the fifth to the eighth elements are NOT 12-15, the element AND-OR-NOT 16. The device provides increased speed when the processor is working with RAM by eliminating idle read cycles when sampling the operands of unaddressed instructions. 1 il.

Description

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Write RAM Read RAM

The invention relates to computing and is likely to be used in the construction of computers with increased productivity.

The aim of the invention is to improve the speed of the device.

The drawing shows the block diagram of the device.

The device contains a register of 1 microinstructions, the first and second decoders 2 and 3, element 4, the first and second triggers 5 and 6, from the first to the fourth elements NOT 7-10, the third trigger 1, from the fifth and the eighth elements NOT 12- 15 and the element I-VDI-NOT 16.

The device operates in three modes: fetching the operand of the address command, disabling the reading of the operand when sampling an unaddressed instruction, and disabling the reading of the operand when a RAM regeneration cycle occurs at the time of fetching an addressless instruction.

In the sampling operand of the address command in the zero microcommand of the address command, a READ micro-order is output by the decoder 2 of the polarization and a READ OP signal is generated with a duration of microprogram beat that passes through the AND 4 element to the information input of the second trigger 6. At times P and Pr This firmware clock code appears on the main processor li TiHe address command code, since in this case, one of the bits of the SB12-SB14 bus necessarily contains a logical one, which, passing through one of the elements NOT J3

15 and the AND-OR-NOT 16 tribe, generate-dd periodically conduct special cycles of regeneration, in which reference to it is prohibited, since it is possible to get vague information. Since the RAM and the processor work in

level (which is generally asynchronous, then

signal A high logic level, which, entering the Hbu i input of the second flip-flop 6, does not prevent the entry of a low lofor-anion input into it by the difference from 1NCPCO to the high sync pulse. Consequently, in the next microprogram-; M OM clock, a READ signal is generated (its differential from low to high is generated by the RA reset signal), which starts the read operand cycle,

In the read prohibit mode, when an unaddressed instruction is scanned into a zero microcommand of an unaddressed microprogram using a READ micro-instruction, the READ OP signal is output at the output of the decoder 2 field operation.

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duration in one microprogram cycle, which, passing through the element 4, enters the information input of the second trigger 6. On the micro-order FTCH, the output of the decoder 3 generates a signal FTCK SP with a duration of one microprogramme time, which passes through the fourth element HE 10, enters to the input element I-IEP-NOT 16 high logic level. At times P and P of this firmware clock, an addressless command code appears on the main processor bus. Since, in this case, the SB12-SB14 bus has logical O on all bits, then the passage through the elements is NOT 13-15, they are at the inputs of the AND-OR-NOT element 16 logical 1. At the same time, at the output of this element a signal is generated A low logic level is suppressed, which is fed to the input of the second trigger 6 and causes a constant level of logic O to appear at its zero output. Since the trigger has a zero input that has a higher priority than the C input, then regardless of it comes a sync pulse and at its information input there is a logical cue O, the state of its zero output does not change, and the READ signal initializing the RAM reading cycle does not occur.

In the operand read inhibit mode, if a regeneration cycle of RAM occurs at the time of sampling an unaddressed instruction, it is necessary to ensure the integrity of information in such RAM.

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a cycle can occur when executing any microcommand, including at the moment when the central processor executes the zero microcommand of the subprogram to select an unaddressed instruction. In this mode, a READ OP signal is generated at the beginning of the microprogram cycle and passed through element 4 to the information input of the second trigger 6, and A prohibit signal is generated. This signal arrives at the single input of trigger 6 and prohibits the generation of the READ signal; in addition, it arrives at the informational

the input of the third flip-flop 11, and the logical O is entered into its single output at the arrival of the Pause signal (FRZFF), which is produced by the central processor in the event of a regeneration cycle. From the single output of the third trigger, the logical O inverts on the fifth element NOT, and logical 1, entering the input of the AND-OR-NOT 16 element, at its output (the Locking signal) is output a low logic level for the entire regeneration cycle, despite That the state of the entire information bus S, including bits SB12-SB14, is indefinite. Therefore, the clock pulse CP12, appearing in the firmware cycle with address 1, does not cause the read signal

RAM READ, the unit output of the trigger 11 is set to logical 1 after the FTCH SP signal goes high logic level in the microcommand with address 1 and, having passed through the fourth element NOT 10 low logic level, comes to its zero input and to the input of the element I- OR NOT 16 and remove the ban signal.

Claims (1)

Invention Formula A processor and RAM interface device containing the microinstructions register, the AND element, the first, second decoders, the first, second triggers, and the first, second NOT elements, and the microcommand register information input is the device input for connecting the processor output command, the register synchronization input microinstructions and synchronization inputs of the first, second triggers are the input of the device for connecting the processor synchronization output, the first, second outputs of the register of microcommands are connected respectively about o o d iQ o - 15 20 45 5170316 with the information inputs of the first, second decoders, the first, second outputs of the first decoder are connected respectively to the information input of the first trigger and to the first input of the element I, the second input and output of which are connected respectively to the first output of the second decoder and to the information input of the second trigger, zero outputs of the first The second flip-flops are connected respectively with the inputs of the first, second elements NOT, the outputs of the first, second elements are NOT outputs of the device for connecting respectively memory write and read inputs, characterized in that, in order to increase the speed of the device, NOT elements 3, the third trigger and the AND-OR-NOT element are entered into it from the third to the eighth, the third trigger is not connected to the third trigger input the input of the device for connecting the output of the processor to the processor, the second output of the second decoder through the fourth element is NOT connected to the single input of the third trigger and to the first input of the AND-OR-NOT element, the second input of which is through the fifth element is NOT connected to the single output of the third flip-flop, the inputs of the sixth, seventh-eighth elements are NOT device inputs for connecting a group of information outputs of the processor, the outputs of the sixth, seventh and eighth elements are NOT connected to the third, fourth, fifth inputs of the AND-OR-HE element, the sixth input of which is the input of the device for connecting the processor reset output, the output of the AND-OR-NOT element is connected to the single inputs of the first and second flip-flops and to the information input of the third flip-flop. 25 thirty 35 40