SU1462327A1 - Program debugging arrangement - Google Patents

Abstract

The device relates to computing, in particular, to devices that provide real-time hardware and software debugging, and can be widely used in debugging and operating microprocessor systems and devices (both single-processor and multi-processor). In order to improve performance, a device containing a register of 3 addresses and states, a register of 6 cycles, a counter of 10 cycles, a comparison circuit of 9 addresses, a register of 13 modes, a selector of 2 addresses, a decoder 4 entries, a decoder 3 readings, And 7, 12 elements are entered , 14, OR elements 8,11, interlock trigger 17, interrupt request trigger 15, interrupt request trigger 19, ready trigger 20, reset trigger 18, key block 16, The proposed device, in conjunction with a debugging microcomputer, allows developing a software cycle: and help programs, debugging them on microprocessor systems and microcomputers. 3 ill., 1 tab. with /)

Description

The computer goes into the standby state g SHA2, the memory is unlocked as a result of which its memory is locked.

Then the port B of the register 13 loads the data byte of the MVTA command, DATA, which through the key block 16 enters the data bus SD2, Signal 31 resets the ready trigger 20, as a result of which the microcomputer goes out of the STANDBY state, accepts the value of the data byte and processes it to according to the command code. Thus, in the accumulator of the microcomputer being debugged, the required information will be recorded, the value of which is determined by the second byte50.

At the same time, the signal is set by the trigger 17 of the signal 49 Memory lock due to the supply to the D input of the trigger 17 via port C of the register 13 of the signal 36 Memory lock with the O level. Thus, the step of loading the programs being debugged into the memory is realized.

The next stage of the program run is carried out either in continuous mode or in steps. The required mode of operation is determined by the state of port C of the data register 13 and the setting of modes, the recording of information in which is effected by the data signal 32 of the data record DAS2, the memory is unlocked in

At the same time, the signal is set by the trigger 17 of the signal 49 Memory lock due to the supply to the D input of the trigger 17 via port C of the register 13 of the signal 36 Memory lock with the O level. Thus, the step of loading the programs being debugged into the memory is realized.

The next stage of the program run is carried out either continuously or in steps. The required mode of operation is determined by the state of port C of the data register 13 and the setting of modes, information is written to by the write signal 32 of the data Hbix to the register 13. In all the listed modes, the internal control signal 36 is received at the D input of the memory lock trigger 17 and a signal 39 arriving at the D-input of the flip-flop 18 provides the signals Blocking of the memory 49 and Reset 50 of the level O. In the case of a continuous operation in the port C of the register 13 is set to the state O Signals 38,40,42 and 43 in the result of h (its output from the element IL And 11 to the li-input trigger 20 readiness post10

the inputs of the element OR the output is connected to the ready mode 20. Controller B starts tact. Such a difference in the scheduling or de SCH 2 1, on the transfer 44 trigger 30 52 Readiness, Repetition of the address externally on data 2 INTRODUCTION SHU2 carried out B and C of the register 3 on

port A of the register 11 register of the register 13,

20

25

35

r | s O is informed of a single signal-is signal 33, PS2 Nal 52 ShU2 Ready,

When operating in the execution mode of a bold program, the steps are set to one state. Signal 40, which through the OR 11 element arrives at the D input of the trigger 20, The C signal enters the 44 Start of the command, As a result, the front output signal 52 Ready j . After that, the signal 32 Read register 1 reads the byte of the state of the microcomputer recorded in register 1, then the command code located on PS2 through the port A of register 13 and read the address of the WMD through ports B and C of the register 3, sampling the specified registers carried out is; control signals 35 and 33,

The operation of the device in the run mode of the working programs with a stop is determined by setting the next sig in one state; inquiries: -38 - setting the Stop mode at the address, 42 - setting the Stop mode according to the presets, and 43 - setting the stop mode using the ENTER and DISPLAY commands,

When debugging work programs with a stop at the INPUT and OUTPUT commands, the control signal 43 is fed to the first input of an AND 12 element. The second input of an AND 12 element is connected to the output of an OR 8 element, to the two inputs of which are respectively the sixth and fourth bits of SD2, Attach to these bits is necessary for determining the INPUT and OUTPUT machine cycles, the sixth bit single state of the CG2, in the presence of a 44 gating signal — The start of the command determines the IN block, similarly the 4th bit of the CID 2 determines the OUTPUT cycle element And 12 enters one of the teams

When debugging the workings of the preregaganista 13, the unit state is set to 42i, which after the input of the element I7, H comes in the zero-zero state, which has a strobe signal and the definition of the interruption, you are connected to one of the hr 30 or 11, Connected to the D-input of the product. At cycles 20, a signal is received. Thus, the 52Go signal in the case of the occurrence of a CONFIRMATION PREP will be assigned by the EST command interrupt processing program, the interrupt will be detected.

When debugging the Stop operation, the transition goes to the debugging state of the program, the specified address, the number of cycles 29, is written to the register and register 6 of the register, to the port, because of the cycles, this mode is fixed in the port. 38, which is the input element and 13

40

45

50

55

the inputs of the element OR 11, which its output is connected to the input of the trigger 20 is ready. A control signal 44 is received at the C input - a sign of the start of the clock. Thus, if there is a scatter or a fourth bit of 2 2 1, on the leading edge of the signal 44 the trigger 30 sets the signal 52 Ready, On W2, the address of the external device will be found, on the gad2 the data of the INPUT or OUTPUT, the SCH2 is read through the ports B and C of the register 3 submission of the control port A of register 11 to the register 13,

 signal 33, ПЩ2

read via signal 35

five

five

When debugging the working programs, the Stop by the preregang in port C of the register 13 is set to the active single state, the control signal 42i, which is fed to the first input of the I7 element. The second input receives the zero bit of the ShchTs2, the single state of which, in the presence of the gate signal 44 The beginning of the command and define the cycle CONFIRMATION OF INTERRUPT, the output of element I., is connected to one of the four inputs of the element OR 11, which is connected to the D input of the ready trigger 20 by its output. At the clock input of the trigger 20 receives a signal 44 Start command. Thus, the trigger 20 will set the 52 readiness signal only in the event of a computer cycle occurrence CONFIRMATION OF INTERRUPTION, 1CU2 will find the return address in the program being debugged to complete the processing of interrupts, and the EST command defining the interrupt microcomputer vector is generated same as in the INPUT and OUTPUT loop,

When debugging work programs in the Stop mode at the address, the microcomputer goes into the standby state when the program being debugged passes the specified number of cycles through the specified stop address. On signal 29, a record in register 6, a stop address is written to ports A and B of register 6, and the number of cycles of repetitions is written to port C of register 6. The setting of this mode is accomplished by installing in port C a register 5 3 into one state of the control signal 38, which is fed to the first input of the element AND 13, Record number cyc0

five

0

55

Repeating in counter 10, operating in the subtraction mode, is performed by setting the state 37 of the signal 37 generated by the port C of the register 13. When operating in this mode, the comparison circuit 9 compares the stop address recorded in the ports A and B of the register 6 with the value of CA2. If these addresses match, circuit 9 generates an equality signal. The output of the circuit 9 is connected to the counting input of the subtraction of the counter 10. When the value of the counter 10 becomes zero, t, e, the program will go through a specified number of cycles, a transfer signal is generated, which is fed to the second input of the element 14, the output of the element 14 is connected to one of four the inputs of the element OR 11, and the output of the element OR 11 is connected to the D input of the ready trigger 20. Thus, on the input of the trigger 20 in Wits 1 under the condition of zero value of the counter 10 repetitions. Readiness trigger 20 generates a Readiness signal on the rising edge of the signal 44, which goes to the C input. The processor of the device being debugged will transition to the idle state. On D1A2 there will be a stop address on 1CD2, the data corresponding to this address. Mycomputer tire readout is performed in the same way as in the previous shutdown modes. In addition, the operation of the device in steps or with a stop is organized with the formation of an interrupt request in the debugging microcomputer. For this purpose, a trigger 15 interrupts are introduced. Setting the trigger to the active state is performed by the 52 Ready signal arriving at. C-input, Preamble request is removed by a signal 34 arriving at the E-input of the trigger 15, the work on the interference is necessary for organizing the optimal use of the debugging microcomputer software. In addition to generating an interrupt request to execute a microcomputer control program, the device can generate an interrupt signal 51 Interrupt request arriving at the microcomputer being debugged. A trigger 19 serves for this purpose. The control signal 41 arrives at the input 1, which is set to 1 d port C of the register 13. At the C-input trigger

19, a clock frequency of 47 is received. An interrupt request is removed by applying a zero signal to the P input 19 of a zero signal 41 on the leading edge of the clock frequency 47, Applying a trigger 19 in the formation circuit of the 51 Interrogation Signal 51 is necessary for the asynchronous signal 41 generated in Port C register 13, was given to the timing diagram of the debugged microcomputer. For the same purpose, a trigger 18 is used, which allows synchronization of the signal 50 50 - Reset,

Claims (1)

Invention Formula A device for debugging programs containing an address register and a state of 20 research institutes, a cycle register, a comparison circuit, a cycle counter, the second information input of the address and status register being the state input of the device for connecting to the control unit of the computer being debugged, the second and the third information inputs of the address register and the states of the state, the address input of the device for connection to the address bus of the debugged computer, the first input of the comparison circuit is connected to the address input of the device for connection to the address bus of the debugger my computer, the second input of the comparison circuit is connected to the first output of the cycle register, the second output of which is connected to the information input & m of the cycle counter, characterized in that, in order to increase the performance when programs are programmed, the device contains a status byte register, a mode register, address selector, write decoder, read decoder, four AND elements, two OR elements, two interrupt request triggers, ready trigger, reset trigger, lock trigger, key block, and the byte register synchronization and, the lock trigger and the readiness trigger are connected to the synchronization input of the device for connecting to the control bus of the computer being debugged, the information input of the status byte register is the device input for connecting to the data of the computer being debugged, the first information inputs of the write and read decoder are connected to address input device to connect to the address 35 50 55 The debugging computer bus, the write and read decoder enable inputs are the write and read inputs of the device for connecting to the debugging computer control bus, the first to fourth read decoder outputs are connected respectively (to the read input of the status byte register, the address register read input and state, the input of the first request of the setting of the first request to the first I in I, the reading of the mode register I, the outputs of the first to fourth record decoder are connected respectively to: the inputs of the register of the address register and; neither the register of cycles, the register: the mode and the input of the installation into the ready trigger, the output of the ad- ira selector is connected with the second information I inputs of write decoders and j readings, the information input of the address selector is the address I input of the device for connection to the I address bus of the debugging computer, the address to the I input, the address selector is the i input of the device mode, the first information permission input, and the second information inputs of the mode register are respectively the address input of the device for Switches to the address bus of the debugging computer and the information input of the device for connecting the debugging computer to the data bus, the first group of outputs of the mode register is connected to the group of information inputs of the block ... keys, the bit outputs of the second group of outputs of the mode register are connected to the information inputs of the request reset blocking triggers interrupt, the installation input of the loop counter, the first inputs of the first and second elements AND, and the first element OR, and the first input of the third element AND, the second input of which is connected to the output the second element OR, the first and second inputs of which and the second input of the second element And form a group of information inputs five 0 devices for connecting the debugging computer to the data bus, synchronizing triggers for resetting and interrupting are connected to the clock input of the device for connecting to the control bus of the computer being debugged, the output of the comparison circuit is connected to the seventh-input loop counter, the output of which is connected to the second input of the first computer the AND element, the output of which is connected to the second input of the first OR element, the third and fourth inputs of which are connected respectively to the outputs of the second and third AND elements, the output of the first OR element is connected to info The trigger input, readiness, direct trigger outputs, reset locks, readiness and inverse output of the second interrupt request trigger are outputs of the device for connection to the control bus of the computer being debugged, direct output of the ready trigger trigger is connected to the first interrupt of the first interrupt request trigger The inputs for receiving and blocking the key block are the inputs of the device for connecting to the control bus of the computer being debugged, the output of the key block is the output of the device for connecting to the data bus, debugging my computer, the direct output of the first interrupt request trigger is the output of the device for connecting to the control bus of the debugging computer, the enable inputs of the address registers and the cycles and mode states are the address input of the device for connecting to the address computer of the debugging computer, the fourth information input-output of the address and status register is the input-output of the device for connection to the data bus of the debugging computer, the information input-output of the register of cycles is the input-output of the device for connection to the bus s debugging computer, the byte output register state is output apparatus podklyuche- audio to debug a computer data bus, vjU 0 five 45 Fie.2 jsnucisejy shaki1aeeaa fii / xfffXH ". h evfwt. iOftOH WITH (SHLNI & Tf, I the condition of the lantern ch /