SU1262516A1

SU1262516A1 - Microprogram control device

Info

Publication number: SU1262516A1
Application number: SU843729126A
Authority: SU
Inventors: Анатолий Иванович Подгорнов; Ромуальд Станиславович Мойса; Аркадий Яковлевич Костинский; Александр Михайлович Шугаев
Original assignee: Предприятие П/Я М-5339
Priority date: 1984-04-20
Filing date: 1984-04-20
Publication date: 1986-10-07

Abstract

Изобретение относитс к области вычислительной техники и может быть использовано в процессорах ЭВМ. Цель изобретени - повьтение быстродействи . Микропрограммное устройство управлени содержит блок 1 местного управлени , блок 2 обработ- с S т елThe invention relates to the field of computer technology and can be used in computer processors. The purpose of the invention is to increase the speed. The microprogram control unit contains a local control unit 1, a processing unit 2 with S

Description

ки условий формировани адреса, пам ть 3, регистр А адреса, триггер 5 выбора двойного слова, триггер 6 выбора слова, блок 7 регистров, элемент И 8, триггер 9 блокировки, элемент 2И-НЛИ 10, два дешифратора 11,14 СОСТОЯНИ11, два счетчика 12,13 повторений и коммутатор 16 микрокоманд . Сущность изобретени эаключаетс в том, что из пам ти выбираютс сразу четЕлре. микрокоманды, а параллельно с этим осуществл етс формирование условий перехода (в микрокоманде условного перехода).Выборка нужного двойного слова, содержащего микрокоманду, заноситс в регистр микрокоманд. При этом разницы во временах выполнени микрокоманды условного и безусловного переходов нет 1 3. п. ф--лы, 3 ил.ki conditions of formation of the address, memory 3, register A address, trigger 5 double word selection, trigger 6 word selection, block 7 registers, element 8, blocking trigger 9, element 2I-NLI 10, two decoder 11.14 STANDING 11, two counter 12,13 repetitions and switch 16 microinstructions. The essence of the invention is that immediately foursome are selected from the memory. microinstructions, and in parallel with this, the formation of transition conditions (in the microcommand of the conditional transition) is carried out. The selection of the desired double word containing the microinstruction is entered into the register of microinstructions. At the same time, there are no differences in the times of execution of the microcommand of the conditional and unconditional transitions 1 3. Sec. F - ly, 3 il.

1one

Изобретение относитс к вычислительной технике и может быть использовано в процессорах ЭВМ.The invention relates to computing and can be used in computer processors.

Цель изобретени - повышение быстродействи .The purpose of the invention is to increase speed.

На фиг.1 представлена функциональна схема предлагаемого устройства; на фиг.2 - блок обработки условий формировани адреса; на фиг.З блок местного управлени .Figure 1 shows the functional diagram of the device; Fig. 2 illustrates a processing unit for the formation of an address; in FIG. 3, a local control unit.

Устройство (фиг.1) содержит блок 1 местного управлени , блок 2 обработки условий формирований адреса , пам ть 3, регистр 4 адреса, триггер 5 выбора двойного слова, триггер 6 выбора слова, блок 7 регистров , элемент И 8 , триггер 9 блокировки, элемент 2И-ИЛИ 10, первый дешифратор 11 состо ний, первый счетчик 12 повторений, второй счет чик 13 повторений, второй дешифратор 14 состо ний, вход 15 синхрони зации, коммутатор 16 микрокоманд, выход 17 признака цикла.The device (Fig. 1) contains a local control unit 1, an address condition generation unit 2, a memory 3, an address 4 register 4, a double word trigger 5, a word selection trigger 6, a registers block 7, an AND 8 element, a locking trigger 9, element 2I-OR 10, first decoder 11 states, first counter 12 repetitions, second counter 13 repetitions, second decoder 14 states, synchronization input 15, switch 16 micro-instructions, cycle sign output 17.

Блок обработки условий формировани адреса (фиг.2) содержит первый регистр 18, второй регистр 19, арифметико-логический узел 20, третий 21 и четвертый 22 регистры.The processing unit of the address generation conditions (FIG. 2) contains the first register 18, the second register 19, the arithmetic logic unit 20, the third 21 and the fourth 22 registers.

Блок местного управлени (фиг.З) содержит вводной регистр 23, регистр 24 маски, выходной регистр 25, регистр 26 микрокоманд, узел 27 элементов 4И-ИЛИ, первьм 28 и второй 29 коммутаторы, первый 30 и второй 31 элементы ЗИ-ИЛИ, первый 32 второй 33, четвертый 34 и третий 35 элементы И, первый 36 и второй 37 дешифраторы, первый 38 и второй 39 мультиплексоры и узел 40 элементовThe local control unit (Fig. 3) contains the input register 23, the mask register 24, the output register 25, the micro-command register 26, the node 27 of the 4I-OR elements, the first 28 and the second 29 switches, the first 30 and the second 31 ZI-OR elements, the first 32 second 33, fourth 34 and third 35 elements And, the first 36 and second 37 decoders, the first 38 and second 39 multiplexers and the node 40 elements

И. Устройство имеет управл к ций выход 41.I. The device has control outputs 41.

Пам ти выбираютс сразу четьфе микрокоманды у а параллельно с этимMemories are immediately selected by the microcommand's chip in parallel with this.

осуществл етс формирование условий перехода (в микрокоманде условного перехода). Выборка нужного двойного слова, содержащего микрокоманду, заноситс в регистр микрокоманд. Приthe formation of the transition conditions is carried out (in the microcommand of the conditional transition). The selection of the desired double word containing a microinstruction is entered into the microinstruction register. With

этом разницы во временах выполнени микрокоманды условного и безусловного переходов нет.There is no difference in the execution times of the microcommand of conditional and unconditional transitions.

В один из счетчиков повторений или в оба сразу заноситс константа , определ юща число вьтолнений одной и той же микрокоманды. При первом выполнении этой микрокоманды устанавливаетс триггер блокировки , который блокирует прием из пам ти новой микрокоманды. Модифициру сь , счетчики измен ют адреса блоков регистров, участвующих в выполнении микрокоманды. Так как врем на формирование адреса следующей микрокоманды при этом учитывать не надо.In one of the repetition counters or in both, a constant is immediately entered, which determines the number of executions of the same microinstruction. The first time this microcommand is executed, a lock trigger is set that blocks the reception of a new microcommand from the memory. Modified, the counters change the addresses of the blocks of registers involved in the execution of a microcommand. Since the time to form the address of the next micro-command is not taken into account.

то цикл устройства определ етс только временем чтение регистра + выполнение операции арифметико-логическим узлом. После обнулени одного из счетчиков повторенийthen the device cycle is determined only by the time the register is read + the operation of the arithmetic logic node. After zeroing one of the repetition counters

триггер блокировки сбрасываетс и из пам ти выбираетс нова микрокоманда .the lock trigger is reset and a new micro-command is selected from the memory.

В микрокомандах условного перехода в. качестве услови перехода может использоватьс как результат выполнени операции в блоке 2, так и cotдержимое отдельных разр дов какоголибо регистра из блока регистров, аIn microcommands of conditional transition in. As a transition condition, it can be used as the result of the operation in block 2, as well as the cotrapping of individual bits of any register from the register block, and

также смешанное условие перехода.also mixed transition condition.

Устройство ориен гировано на выполнение микрокоманд условного перехода при возможности выполнени перехода с коэффициентом ветвлени , равным 4 В этом случае услови перехода могут принимать следующие значени : 00, 01,10,11. Таким образом, адрес группы из четырех микрокоманд задан в самой микрокоманде, а конкретный переход определ етс путем опроса заданных в микрокоманде условий, The device is focused on the performance of conditional transition micro-commands when the transition is possible with a branching ratio of 4. In this case, the transition conditions can take the following values: 00, 01,10,11. Thus, the address of a group of four micro-commands is specified in the micro-command itself, and a specific transition is determined by polling the conditions specified in the micro-command.

Работа устройства при выполнении микрокоманды условного перехода можно разбить на следующие этапы: считьгаание из пам ти 3 группы из четырех микрокоманд; считывание одного из регистров, вход щих в состав блока 7 регистров и содержащего биты, вл ющиес условием перехода; формирование условий перехода; установка триггера 5 выбора двойного слова; установка триггера 6 выбора слова; занесение очередной микрокоманды в регистр 26 микрокоманд; дешифраци выбранной микрокоманды.The operation of the device when performing a microcommand of a conditional transition can be divided into the following stages: retrieving from memory 3 groups of four microcommands; reading one of the registers included in block 7 of registers and containing bits that are a condition for the transition; formation of transition conditions; setting the trigger 5 double word selection; installation of the trigger 6 word selection; entering the next microinstruction in the register of 26 microinstructions; decryption of the selected microcommand.

По содержимому регистра 4 адреса из пам ти 3 считываетс четыре слова, которые поступают на коммутатор 16 микрокоманд, на котором выбираетс нужное двойное слово по состо нию триггера 5 выбора двойного слова. Далее выбранное двойное слово заноситс в выходной регистр 25. В свою очередь это двойное слово подаетс на коммутатор 29, на котором выбираетс нужное слово по соето нию триггера 6 выбора слова. Выбранное слово заноситс в регистр 26 микрокоманд, содержимое которого по .даетс на второй дешифратор 37.According to the contents of register 4 of the address from memory 3, four words are read out, which are fed to the switch 16 microinstructions, where the desired double word is selected according to the state of the double word selection trigger 5. Next, the selected double word is entered into the output register 25. In turn, this double word is fed to the switch 29, where the desired word is selected by the word selector trigger 6. The selected word is entered in the register 26 microinstructions, the contents of which is given to the second decoder 37.

Под управлением соответствующего второго дешифратора 37 на коммутаторе 28 выбираетс слово из пам ти 3 с коммутатора 29 или значение регистра 21 блока 2 и передаетс через тракт данных в регистры блока 7. В формировании адресов регистров 7 блока, поступающих из первого дешифратора 36, участвуют определенные разр ды регистра микрокоманд 26, зна чение соответствующего выхода второго дешифратора 37 и значени первого 12 и второго 3 счетчиков. Под управлением соответствующих выходов второго дешифратора 37 на элементах ЗИ-ИЛИ 30 и 31 выбираютс признаки результата с регистра 22 блока 2, под управлением второго дешифратора 37, кроме того, выбираютс Under the control of the corresponding second decoder 37, the switch 28 selects the word from memory 3 from switch 29 or the value of register 21 of block 2 and is transmitted through the data path to registers of block 7. Specific bits participate in generating addresses of block registers 7 coming from first decoder 36 d-register microinstructions 26, the value of the corresponding output of the second decoder 37 and the values of the first 12 and second 3 counters. Under the control of the corresponding outputs of the second decoder 37 on the elements ZI-OR 30 and 31, the result signs are selected from the register 22 of the block 2, under the control of the second decoder 37, in addition,

признаки безуслонных переходов с регистра 26 микрокоманд.signs of seamless transitions from the register of 26 microinstructions.

В случае выполнени микрокоман ды условного перехода соответствующие выходы второго дешифратора 37 .1от выбором на первом 38 и втором 39 мультиплексорах условий перхода , подаваемых с регистра 21 блока 2 на фоне чтени группы из четырех слоев пам ти 3. Эти выбранные услови переходов под управлением соответствуюп5их выходов второго дешифратора 37 передаютс на установку новых значений триггера 5 выбора двойного слова и триггера 6 выбора слова.In the case of a conditional transition micro-coder, the corresponding outputs of the second decoder 37 .1 are selected by selecting the first 38 and second 39 multiplexers of the transition conditions supplied from the register 21 of unit 2 against the background of reading a group of four layers of memory 3. These selected conditions of the transitions under the control of the corresponding outputs the second decoder 37 is transmitted to the installation of the new values of the double word trigger 5 and the word 6 trigger 6.

В микропрограммах часто встречаютс циклы, в которых однотипные действи выполн ютс над различными операндами. Микрокоманды, составл ющие цикл, отличаютс только пол ми , aдpecyющи ш операнды. При это в основу работы устройства положено требование размещени операндов, :участвующих в цикле, в регистрах блока 7, имеющих последовательные адреса. Работу устройства в этом случае можно разбить на следующие этапы: выбора микрокоманды из пам ти 3 в регистр 26 микрокоманд; занесение в счетчики 12 и 13 константы, определ ющей количество микрокоманд в цикле; состо ние счетчиков 12 и 13; считывание операндов в блок 2 формирование результата в блоке 2;. состо ние триггера 9 блокировки; модификаци счетчиков.In microprograms, cycles are often encountered in which actions of the same type are performed on different operands. The microcommands constituting the cycle are distinguished only by the fields that specify the operands. In this case, the operation of the device is based on the requirement for the placement of operands,: participating in the cycle, in the registers of block 7 having consecutive addresses. The operation of the device in this case can be divided into the following steps: the choice of a microcommand from memory 3 to the register of 26 microcommands; entering in counters 12 and 13 a constant defining the number of micro-instructions in a cycle; the state of the counters 12 and 13; reading operands in block 2; the result is formed in block 2 ;. lock trigger status 9; counter modifications.

Claims

After such a micro-command is entered into the register of 26 micro-commands, a signal is written to the first 12 and second 13 counters from the memory via the data path through the corresponding output of the second decoder. In the case of non-zero values of the first 12 or second 13 counters, a signal is set from element 2ILI 10 under control of the corresponding outputs of the second decoder 37, which sets in one state the lock trigger 9, which in turn blocks the reception of new information from memory 3 to output register 25 and blocks changes in the word trigger selection 6. The state of this trigger provides for the re-sampling of this microcommand from the output register 25, excluding the access to the memory 3. Opt {ov. 5 variable signal from the output of the element 2I-I.PI 10 is fed to the output I 7 to reduce the cycle time of the process time taken to access memory. The number of repetitions of this microcommand is determined by the state of the counters 12 and 13. When the counter is reset, output 17 generates a processor cycle increase signal and locks trigger 9 is reset, which paapeinaeT receives the next microcommand from the memory. Claim 1. A microprogram control device containing an address generation condition processing block, a register block, double word trigger, word select trigger, address register, memory and local control block containing input register, output register, mask register, micro-command register, two multiplexers , node of elements, two decoders, two elements of ZI-OR, two switches, node of elements AND, and from the first to third elements AND, and the information input of the memory is connected to the output of the node of elements 4И-OR, the first inputs of the first and second a number of groups of which are connected to the output of the input register, the information input is connected to the information output of the processing unit for the formation of the address, the second information output of which is connected to the first information input of the first switch, the second information input of which is connected to the information input of the micro-command register and the output of the second the switch, the first information input of which is connected to the first input of the third group of the node of elements 4И-OR and the first output of the output register, the second output which is connected to the second information-tM input of the second switch by the first input of the fourth group of the 4I-OR node node, the second inputs of the first and fourth groups of which are connected to the direct output of the AND node, the inverse output of which is connected to the first inputs of the second and third groups The 4ILI element node, the first input of the AND node is connected to the output of the mask register, the information input of which is connected to the output of the mask register field of 166 microcommands, the output of the analyzing Mojo field is connected to the first input of the first des If the second input and output are connected respectively to the first output of the second decoder and the register number of the register block, the synchronization input of which is connected to the synchronization inputs of the double word trigger, address register, microinstructions register and address condition processing unit, the first inputs of the first, second and the third And elements and the synchronization input of the device; the second input of the Node of the elements And is connected to the control input of the second switch and the output of the word selection trigger; which is connected to the output of the first ZI-OR element, the first and second inputs of the first group of which are connected respectively to the second output of the second decoder and the output of the second multiplexer, the control input of which is connected to the third output of the second decoder, the fourth output of which is connected to the control input of the first multiplexer, the output of which is connected to the first input of the first group of the second element ZI-OR, the second input of the first group of which is connected to the fifth output of the second decoder, the sixth and seventh you the moves of which are connected, respectively, with the first inputs of the second and third groups of the second element ZI-I.PI; OR, the second input of the second group of which is connected to the eighth output of the second decoder, the ninth and tenth outputs of which are connected respectively to the first input of the third group of the first element ZI-OR and to the control input p The first switch, the output of which is connected to the information input of the register block, the output of which is connected to the information input of the processing block of addressing conditions, the input of the operation code of which is connected to the eleventh output of the second decoder, the twelfth, thirteenth and fourteenth outputs of which are connected to the second inputs of the first, the second and third elements And, the outputs of which are connected respectively to the inputs of the input register record, mask register and memory, the address: input of which is connected with the output of the address register, the information input of which is connected to the output of the address field of the microinstruction register, the output of the local control field of which is connected to the input of the second decoder, the second inputs of the third GRUPP of the first and second ZI-OR elements are connected to the output of the result sign; the conditions of formation of the address, the output of the second element PLN-OR is connected to the information input of the double word selection trigger, the output field of the micro-operation of the microcommand register is connected to the control output of the device, about and so that, in order to increase speed, a micro-command switch, an AND element, a lock trigger, an element of the first and second decoders of the co-ordinates, a first and second counters of ignitions, and a fourth element of the The device sync input is connected to the synchronization input of the blocking trigger, to the counting inputs of the first and second repeat counters, to the first input of the device AND element and the first input of the fourth And element, the second input of which is connected to the direct output blocking trigger, the inverse output of which is connected to the second input of the element I of the device, the output of which is connected to the synchronization input of the word selection trigger, the information input of the blocking trigger is connected to the fifteenth output of the second decoder, the sixteenth and seventeenth outputs of which are connected respectively to the first inputs of the first and second groups of element 2IPI,. the second inputs of the first and second groups of which are connected respectively to the outputs of the first and second state decoders, the output of the element 2Y-OR is connected to the input of setting the lock trigger to zero and to the output of the device cycle indication. 168 the input of the first state decoder is connected to the third input of the first decoder and with the output of the first repeat counter, the recording / account input of which is connected to the record input of the second counter and the eighteenth output of the second decoder, the output of the first switch is connected to the information inputs of the first and second repetition counters, the output of the second repetition counter is connected to the fourth input of the first decoder and to the input of the second state decoder, the output of the fourth element I is connected to the recording input yhodnogo registers of ra, an information input coupled to an output switch microinstructions, first and second control inputs of which are connected soot. Correspondingly, with the direct and inverse outputs of the double word selection trigger, the first and second information inputs of the micro-command switch are connected respectively to the first and second memory outputs.

2. The device according to claim 1, that the unit for processing the conditions for the formation of the address contains four registers and an arithmetic logic node, and the information input of the block is connected to the information inputs of the first and second registers, the synchronization inputs of which are connected to the synchronization inputs of the third and the fourth registers and are connected to the syncronization input of the block, the output of the first register is connected to the first information input of the arithmetic logic node and connected to the first informational output of the block, the output of the second p The register is connected to the second information input of the arithmetic-logical node, the input of the operation code of which is connected to the input of the operation code of the block, the outputs of the operation result and the indication of the result of the operation of the arithmetic logic node, respectively, with the information inputs of the third and fourth registers, whose outputs are respectively, the second informational OUTPUT and the output of the indication of the result of the block.