JPH09223010A - Microprocessor and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change the frequency of a clock signal and to improve the total processing speed of a microprocessor by using a clock control circuit which changes the frequency of a clock to be supplied to each pipeline stage based on the time information held by each pipeline holding means. SOLUTION: A clock control circuit 353 changes the frequency of a clock signal 354 based on the time information held in the time information fields 321a, 331a and 341a of stages E, M and W respectively. Only the instruction that is held by an input register of the stage M requires 6 cycles of a source clock 352 for its execution, and the instructions of stages E and W can operate by 4 cycles of the source clock 352 respectively. Under such conditions, the type of instruction that is held by the input register of a stage D cannot be discriminated and the time required for its execution is fixed at 4 cycles of the source clock 352. The circuit 353 does not raise the clock signal 354 before the execution is over for the instruction of the stage M that requires the longest time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor for executing instructions in a pipeline system in synchronization with a clock and a processing method thereof.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a conventional pipeline type microprocessor. This microprocessor has a five-stage pipeline configuration of F, D, E, M, and W.

In the F stage, the instruction fetched from the instruction cache 101 is fetched in the D stage input register 111. In the D stage, register file 11
2 is read and an instruction is decoded by the decoder 113, and its output is captured in the E stage input register 121.

At the E stage, depending on the type of instruction, the address calculation by the operand address adder 122, A
An arithmetic operation or a logical operation by the LU 123 or a shift operation by the shifter 124 is performed, and the result is stored in the M stage input register 131.

At the M stage, depending on the type of instruction, reading from the data cache 132, writing to the data cache 132, or W of the operation result at the E stage held in the M stage input register 131 is performed.
Transfer to the stage input register 141 is performed.

At the W stage, writing to the register file 112 is performed depending on the type of instruction. Instructions progress one stage at a time in one clock in the above five pipeline stages. This is shown in FIG.

Although the register file 112 described in the D stage and the register file 112 described in the W stage are described separately for the purpose of explaining the pipeline operation, they are actually the same. And
It has the function of simultaneously executing the read operation and the write operation in one clock.

A clock signal 154 from a clock control circuit 153 is supplied to each of the D, E, M, and W input registers, and these input registers are synchronized with the rising edge of the clock signal 154 to instruct the preceding stage instruction. Take in. That is, the pipeline advances one stage at each rising edge of the clock signal 154.

The clock control circuit 153 divides the original clock signal 152 output from the clock generator 151 by 6, and outputs it as a clock signal 154. FIG. 11 is a circuit diagram of a conventional clock control circuit 153. The clock control circuit 153 is a frequency divider mainly composed of three-stage D-FF circuits. FIG. 12 shows the operation timing. Only the waveform obtained by dividing the original clock by 6 is output.

[0010]

The same clock signal 154 is supplied to the input registers 111, 121, 131 and 141 of D, E, M and W, respectively. The higher the frequency of the clock signal 154, the faster the instructions flow through the pipeline, and the processing speed of the processor is improved. The maximum frequency of clock signal 154 is determined by the most recently completed stage of the five pipeline stages. This is because if the clock signal 154 is raised before the operation of all pipeline stages is completed, an incorrect value will be input to the next pipeline stage. Here, it is assumed that the operation of the data cache 132 of the M stage is the slowest as compared with the other register file 112 and ALU 123.

A problem with the conventional example is that the maximum frequency cannot be increased due to the operating speed of the data cache, although the data cache is not used depending on the type of instruction. Even if the data cache is used, the clock signal 15 is used so that the processor operates normally.
Since the frequency of 4 is set low and the frequency cannot be changed according to the situation, even instructions that could otherwise be processed at higher speed are processed slower, resulting in a decrease in the processing speed of the entire processor. .

The present invention is intended to solve the above problems, and an object thereof is to improve the processing speed of the entire processor by changing the frequency of a clock signal according to an instruction.

[0013]

In a microprocessor for executing an instruction in a pipeline system in synchronization with a clock, an instruction register holding an instruction to be executed and an instruction held in the instruction register are decoded, The instruction decoder outputs the time information required for execution in each subsequent pipeline stage, and the time information output by the instruction decoder, and holds the time information flowing through the pipeline as the instruction is executed. A plurality of pipeline stages having a time information holding field, a clock control circuit for changing the frequency of a clock supplied to the pipeline according to the time information held in the plurality of pipeline stages, and a clock control circuit Micro having a clock generator for generating a clock Using processor prevents reduction of unnecessary operating frequency, improve the processing speed of the processor.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. FIG.
The microprocessor has a five-stage pipeline structure of F, D, E, M, and W.

First, in the F stage, the instruction cache 3
The instruction fetched from 01 is the D stage input register 3
Taken in 11. In the D stage, the register file 312 is read and the decoder 313 decodes the instruction, and the output is the E stage input register 3
21. Along with the decoding of the instruction, the decoder 313 outputs information on the time required to execute the instruction in each subsequent pipeline stage.
FIG. 2 shows the configuration of the decoder 313 that outputs this time information. The decoder 313 includes an instruction decoder 313a having the same function as that of a conventional instruction decoder, and E, M, W as the instruction decoder 313a decodes an instruction.
And a time information setting circuit 313b that outputs the time information required to execute the instruction in each pipeline stage. The time information output by the time information setting circuit 313b is held in the time information field (time) 321a provided in the input register of the E stage.

In the E stage, depending on the type of instruction, the address calculation by the operand address adder 322, A
An arithmetic operation or a logical operation by the LU 323 or a shift operation by the shifter 324 is performed, and the result is stored in the M stage input register 331. At the same time, the time information held in the time information field 321a provided in the input stage of the E stage is changed to the time information field 3 provided in the input register of the M stage.
31a.

At the M stage, depending on the type of instruction, reading from the data cache 332, writing to the data cache 332, or W of the operation result at the E stage held in the M stage input register 331 is performed.
Transfer to the stage input register 341 is performed. At the same time, the time information held in the time information field 331a provided in the input stage of the M stage is
It is transferred to the time information field 341a provided in the input register of the W stage.

At the W stage, writing to the register file 312 is performed depending on the type of instruction. Instructions progress one stage at a time in one clock in the above five pipeline stages.

Further, the clock control circuit 353 has E,
Time information field 321 for each stage of M and W
The frequency of the clock signal 354 is changed based on the time information held in a, 331a, and 341a. An operation example of the clock control circuit 353 will be described below. For example, in FIG. 1, only the instruction held in the input register of the M stage requires 6 cycles of the original clock 352 to execute, and the instruction of the E stage and the W stage requires 4 cycles.
It is assumed that it can operate in cycles. Since the instruction held in the input register of the D stage is before being decoded by the decoder 313, the type of the instruction cannot be discriminated and the time required to execute the instruction is fixed to 4 cycles.
The clock control circuit 353 does not raise the clock signal 354 until the execution of the instruction in the M stage, which takes the longest time, is completed.

Next, the operation of the microprocessor to which the present invention is applied will be described with reference to FIG. It is assumed that the instruction of number N requires 6 cycles of the original clock 352 only in the M stage and can operate in 4 cycles in the other stages. The instructions with numbers N-1, N + 1, and N + 2 are assumed to be able to execute all stages in a time corresponding to four cycles. The clock control circuit 353 outputs a clock signal 354 whose one cycle is four cycles of the original clock 352 except when the instruction of the number N is in the M stage, and the pipeline flows at high speed. When the instruction with the number N enters the M stage, the clock control circuit 353 outputs a clock signal 354 having 6 cycles of the original clock 352 as one cycle, and the pipeline operation is temporarily delayed. When the instruction of the number N passes through the M stage, a clock signal having 4 cycles of the original clock as 1 cycle is output again, and the 4 pipelines operate at high speed. Comparing with the operation timing of the conventional example shown in FIG. 10, it can be seen that the same number of instructions is processed in a short time.

The field holding the time information is specifically shown in FIG. 6 (a). The time information field 321a in the input register 321 of the E stage has E, M, and
W has a total of 3 bits of 1 bit each representing time information in each stage. "0" indicates that the execution of that stage requires a time corresponding to four cycles of the original clock 352. "1" indicates that it takes 6 cycles.
In the example of FIG. 6A, the E stage and the W stage can be executed in 4 cycles, and the M stage shows that an instruction which takes 6 cycles advances in the pipeline. When going through the pipeline, the time information that is no longer needed is not transmitted to the next stage.

6B and 6C show another example of the time information field. FIG. 6B shows by 1 bit only whether or not the frequency is lowered in the M stage which lowers the frequency of the clock signal. Instead of the M stage, the E stage or the W stage may be used depending on the stage configuration. In FIG. 6C, the operating frequency of any one of the stages E, M and W can be lowered. For example, when a certain instruction is decoded and information "10" is sent to the time information field in synchronization with the clock signal, the frequency drops when this instruction is in the M stage. The frequency of the E stage decreases when the information is “01”, and the frequency of the W stage decreases when the information is “11”. "0" when the frequency is not dropped at any stage
Flow 0 ".

FIG. 4 shows the clock control circuit 353 of the present invention.
FIG. FIG. 5 shows the operation timing of the circuit of FIG. First, the configuration of the circuit shown in FIG. 4 will be described. Similar to the conventional clock control circuit shown in FIG. 11, the frequency divider mainly comprises three stages of D flip-flop circuits 360, 361, 362. In addition to the circuit of FIG. 11, the selector 36
5 is newly provided, and the OR signal of the time information inputs 325, 333, 342 is used as the selection signal output from the OR circuit 369. The selector 365 receives the D flip-flop 36 output from the AND circuit 370 as one input.
An AND signal of the inversion of the Q output of 1 and the Q output of the D flip-flop 362 is supplied, and the Q output of the D flip-flop 361 and the Q output of the D flip-flop 362 output from the AND circuit 371 as the other input are inverted. An AND signal with is supplied. When the selection signal output from the OR circuit 369 is 1, the one input is output, and when the selection signal is 0, the other input is output. The output of the selector 365 is input to one input end of the selector 363 via the inverter 372 and used as a counter reset signal.

This circuit is used when the time information shown in FIG. 6 (a) is used. When using other types of time information, the time information input 32 is used instead of the OR circuit.
5. Use appropriate logic circuitry to generate the select signal from 5,333,342.

Flip-flops 360, 361, 362
Takes in the D input in synchronization with the rising edge of the clock input signal, and outputs its normal signal to Q and its inverted signal to QN. When the reset signal 355 goes low, the selectors 363 and 364 select the original clock 352. At the same time, the D inputs of the flip-flops 361 and 362 become 0, and the D inputs of the flip-flop 360 become 1. When the original clock 352 rises in this state, the flip-flop 3
61 and 362 are 0, and flip-flop 360 is 1
Is initialized to

When the reset signal 355 goes high, the flip-flops 361 and 362 operate as counters. When the selection signal 365 is 0, the flip-flop 3
When 62 becomes 0 and the flip-flop 361 becomes 1, the counter reset signal 366 becomes 1, and the flip-flops 361 and 362 become 0 at the next rising edge of the original clock 352.
And the Q output of the flip-flop 360 is inverted at the same time. By repeating this, the clock signal 35
The waveform of 4 is a waveform obtained by dividing the original clock 352 by 4.

When even one of the time information signals 325, 333, 342 becomes 1, the selection signal 365 becomes 1, the flip-flop 362 becomes 1, and the flip-flop 361 becomes 0.
The counter reset signal 366 goes to 1 only after. At the next rising edge of the next original clock 352, the flip-flops 361 and 362 are reset to 0, and at the same time, the Q output of the flip-flop 360 is inverted. By repeating this, the waveform of the clock signal 354 becomes the original clock 35.
It becomes a waveform obtained by dividing 2 by 6.

As described above, when there is a slow instruction in any one of the E, M, and W stages, the frequency of the clock signal 354 becomes low. FIG. 7 shows another embodiment of the present invention.
The difference from the embodiment of FIG. 1 is that the execution time in each of the E, M, and W stages can be externally controlled using an external input signal 315. When the information indicating the execution time is in the format of FIG. 6A, if the external input signal 315 is set to 1, the time information output from the decoder 313 is directly taken into the time information field of the E stage, and if it is set to 0, the time information is output. Is 0
The execution time at the corresponding stage does not become long.
That is, although the execution time information for each instruction for each stage is defined in advance by the instruction decoder 313,
It is possible to control it from the outside.

FIG. 8 shows still another embodiment of the present invention. The difference from the embodiment of FIG. 1 is that an instruction for lengthening the execution time can be set by software. The low speed instruction register 317 and the mask register 319 are registers writable by a machine language instruction. D
The comparator 31 compares the instruction bit pattern of the stage input register and the instruction bit pattern stored in the low speed instruction register.
8, and the time information according to the result is written in the E stage input register 321. When comparing instruction bit patterns, data in which 1 is set in the bit positions of the bits to be compared and 0 is set in the bit positions of the bits that are not compared is written in the mask register 319, and the logical product of this and the instruction bit pattern is written. The AND circuit 316 limits the bits to be compared. By doing so, it becomes possible to execute a plurality of instructions as low speed instructions as in the following example. Instruction mask Comparator input Comparison low speed instruction register 11101000 and 1111000-> 11100000 <-> 11100000 11101111 and 1111000-> 11100000 <-> 11100000 Both of the above instructions are low speed instructions.
If the instruction is slow in the M stage and the time information in the format shown in FIG. 6A is used, "010" is output.

Further, as another means for generating the execution time information for each stage for each instruction, the EE for performing the read operation using the instruction code of the D stage input register as an address.
There is also a method of using a PROM.

[0031]

As described above, the present invention is provided with a decoder which decodes an instruction and outputs information on the time required for execution in each pipeline stage, and registers the time information in the register of each pipeline stage. A field to hold is provided so that time information flows along with the instruction in the pipeline stage, and the frequency of the clock supplied to the pipeline by the clock control circuit is changed according to the time information of each instruction held in each pipeline stage. By doing so, the processing speed of the processor is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a diagram showing a decoder of the present invention.

FIG. 3 is a diagram showing an operation timing of the present invention.

FIG. 4 is a circuit diagram of a clock control circuit of the present invention.

FIG. 5 is a diagram showing the operation timing of the clock control circuit of the present invention.

FIG. 6 is a diagram showing a configuration example of a time information field.

FIG. 7 is a diagram showing another embodiment of the present invention.

FIG. 8 is a diagram showing still another embodiment of the present invention.

FIG. 9 is a block diagram of a conventional example.

FIG. 10 is a diagram showing operation timing of a conventional example.

FIG. 11 is a circuit diagram of a conventional clock control circuit.

FIG. 12 is a diagram showing an operation timing of a clock control circuit of a conventional example.

[Explanation of symbols]

313 ... Decoder, 321 ... E stage input register, 321a ... E stage input register time information field, 331 ... M stage input register, 331a ... M stage input register time information field, 341 ... W stage input register, 341a ... W Time information field of stage input register, 351 ... Clock generator, 353 ... Clock control circuit.

Claims (9)

[Claims] 1. In a microprocessor having a plurality of pipeline stages and executing instructions in a pipeline system in synchronization with a clock, an instruction register holding an instruction to be executed, and an instruction register held in the instruction register. An instruction decoder that decodes an instruction and outputs information on the time required for the instruction to execute in a subsequent pipeline stage to the next pipeline stage; and an instruction decoder provided in each pipeline stage, And a frequency of a clock to be supplied to each pipeline stage according to the time information held in the holding means of each pipeline and the holding means that outputs the time information flowing through the pipeline with the execution of the instruction. And a clock control circuit for changing the clock. Russia processor. 2. The instruction is provided between the instruction decoder and the holding means, and receives time information output from the instruction decoder and control information input from the outside, and the instruction is executed in each subsequent pipeline stage. The microprocessor according to claim 1, further comprising a control circuit that outputs time information necessary for the microprocessor. 3. A microprocessor having a plurality of pipeline stages and executing instructions in a pipeline system in synchronization with a clock, a first register holding an instruction to be executed, and the plurality of pipeline stages. A second register that holds information that specifies an instruction that requires a longer execution time than usual, and a second register that holds information that specifies a field to be masked for the instruction held in the instruction register. A third register, an AND circuit that inputs the contents of the first register and the contents of the third register, and outputs information in which some fields are masked, the output of the AND circuit, and the second It compares the information held in the registers and determines the time required to execute the instruction to be executed in each subsequent pipeline stage. A comparator for outputting information, a holding unit provided in each of the pipeline stages for holding the time information output from the instruction decoder and flowing through the pipeline with execution of an instruction, and a holding unit for each of the pipelines. A clock control circuit that changes the frequency of the clock supplied to each of the pipeline stages according to the held time information. 4. The time information comprises 1-bit information, and indicates whether or not the instruction requires a longer than usual execution time in a specific pipeline stage. Microprocessor. 5. The time information comprises a plurality of bits for identifying a certain pipeline stage, and when an instruction including the time information enters a pipeline stage indicated by the time information, each pipeline 2. The microprocessor according to claim 1, wherein the frequency of the clock supplied to the microprocessor is reduced. 6. The time information comprises the same number of bits as the number of pipeline stages, each bit indicating whether the instruction requires a longer than normal execution time in the corresponding pipeline stage. The microprocessor according to claim 1, characterized in that: 7. In a microprocessor having a plurality of pipeline stages and executing instructions in a pipeline system in synchronization with a clock, a decoder decodes an instruction to be executed, and the instruction decodes each subsequent instruction. Outputs time information required for execution in the pipeline stage, the time information is held in the pipeline stage, flows through the pipeline with the instruction, and is supplied to the pipeline according to the time information held in each pipeline stage. A method of processing a microprocessor, characterized in that the frequency of a clock to be used is changed. 8. The time information required for execution of the instruction in each subsequent pipeline stage is output from the time information and control information input from the outside. Microprocessor processing method. 9. A processing method of a microprocessor having a plurality of pipeline stages and implementing instructions in a pipeline system in synchronization with a clock, comprising a bit pattern of an instruction to be executed and a bit pattern which is a mask. AND operation is performed between the two, and the result of the AND operation is compared with information specifying an instruction that requires a longer than usual execution time in any of a plurality of pipeline stages, and the instruction to be executed is A microprocessor characterized by outputting time information required for execution of each subsequent pipeline stage, and changing a frequency of a clock supplied to the pipeline according to the time information held in a plurality of pipeline stages. Processing method.