JPS60250473A - Vector processor - Google Patents

Abstract

PURPOSE:To count the number of extracted vector elements that conform to a specified pattern continuously by generating the number of continuous specific patterns in a part masked by a mask register to resultant vector. CONSTITUTION:When a vector element of input vector is inputted to a register R3, logical operation is made with a mask pattern stored in a register R2 by a logical operator G2. The result is compared with a specific pattern stored in a register R5 by a comparator C3, and the result is sent to a count discrimination circuit C4 through an AND gate G1. When specific patterns are applied continuously from a line l9, the count discrimination circuit C4 applies count pulse to a counter C5 through a line l15 under control of a flip-flop FF1. The result of counting is stored in a vector register by a distributor D1 from a gate C6 through a line l17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a program-controlled digital computer, and particularly to a digital computer suitable for executing vector operations at high speed (hereinafter referred to as a vector processor).

[Background of the invention]

Vector processors have been devised for high-speed processing such as large matrix calculations that frequently appear in scientific and technical arithmetic.

A vector processor can perform vector processing at high speed as shown in the following FOR"RAN statement.

DO10I=1. N 10 A(1) = B(I) 10(I) That is, (B(I), I=1.N) is vector B.

Let (C(I), I=1.N) be a vector C, add both elements for each vector element (B(I), C(I), etc.), and store the result as a vector A. In this way, the vector processor can process operations between vector elements at high speed using vector processing techniques. However, as shown in Figure 1, the conventional process of extracting some (or all) of each vector element and counting the number of consecutive extracted elements that match a specific pattern is difficult. Vector processors could not perform vector processing.

When performing such processing, high-speed processing cannot be expected because each instruction is executed sequentially one by one as in a general-purpose computer. The processing shown in Figure 1 is essential when, for example, in image processing, it is necessary to perform run-length encoding at high speed, which requires counting the number of consecutive O's or 1's in an image. be.

In previously published examples, there was an instruction to count the number of consecutive '0's from the beginning of a line, and an instruction to count the number of '1'a's in a vector register.
There were no examples of two vector elements.

[Purpose of the invention]

One object of the present invention is to provide a vector processor capable of executing the processing shown in FIG. 1 as vector processing.

) [Summary of the Invention] Specifically, as shown in FIG. In this case, the number of consecutive specific patterns (in this case, ``'1'') in the part masked by the mask register of the data vector corresponding to the element containing the pattern (in this case, ``'1'') is generated in the result vector. The goal is to realize vector processing.The result vector shown in Figure 2 changes in length (vector length) with respect to the control vector and input vector, so if vector elements corresponding to the required length are extracted, the required data can be obtained.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to examples. Third
The figure shows an embodiment of the invention.

In FIG. 3, register R1 is an instruction register;
It is divided into two fields. The OP field indicates an instruction code, which is sent by l/111 to the arithmetic control (22) CI, which controls instruction execution. Refield specifies the vector register number in which the result vector is stored, is input to the distributor D1 by glt2, and in D1, the result vector input from the line L17 is assigned to one of the vector registers Vo-Va-t. Used to control whether to store data in a register. The j field specifies the vector register number in which the control vector is stored, is input to the selector S1 through the line t3, and is used to select which register among the vector registers Vo to V m -s. The selected content is placed on line t6.

The K field specifies the vector register number in which the data vector is stored, and the line t4 indicates the selector S.
2 and vector register Vo~■. -Used to select which register in the village. The selected content is placed on line t5. Register R2 is an input button mask register for masking the input vector, register R34d is a register for holding a 1-element vector of the input vector, register R4 is a register for holding 1 vector element of the control vector, and flip-flop F1 is a register for holding a 1-element vector of the input vector. , a flip-flop that holds the state of whether to count continuous specific patterns or continuous patterns that are not specific patterns, and logic operator C2 to perform logical operations on input vector register R3 and mask register R1 to extract necessary parts. The calculation result is sent to the comparator C by the line t7.
Sent to 3. The comparator C3 is a comparator that compares the input extraction vector element and the comparison button register R5 to see if they match. The count discrimination circuit C4 supplies the count pulse inputted from mt9 to the counter C5 via the line t16. The gate C6 outputs the cumulative count information of the counter C5 to wt1 when the series of specific patterns ends or starts.
't to the distributor D1.

Next, the operation will be explained in detail. When an instruction specifying the execution of this operation is input to the instruction register R1, OP, i, j,
The contents of each field are sent to the arithmetic and control unit C1, distributor D1, and selectors 81 and 82, respectively. Arithmetic control unit) CI first connects the count discrimination circuit C to line t13.
Issue a clear instruction after passing through 4, flip flop FF1
, counter C5, and gate C6 are respectively connected to lines t11. By t16°t14, it becomes shiny. Distributor D1, selector 8
1.82 sets the distribution route and the selection route as indicated by l+J+k, respectively. Next, the arithmetic and control unit sends read and write instructions to the necessary vector registers via line 118, and at the appropriate timing, reads j, one vector element at a time from the registers specified by j. Instructs sequential reading and writing of results to the vector register specified by i. This operation is
Since it is similar to a normal vector processor, a detailed explanation of its operation will be omitted.

Now, when the vector element of the input vector is input to the register R3, a logical operation (for example, an AND operation) is performed on the mask button stored in the register R2 and the logical operator C2, and the result is placed on the line t7. The result is compared with the specific button stored in the register R5 by the comparator C3, and the result is sent to the count discrimination circuit C4 via the ANDG1. AND game) Gl is a circuit for calculating the logical product of the control vector element register R4 and the output of the comparator C3, and calculating the number of consecutive control vectors only in the portion t'1''.

ANDG) The output of Gl is passed through line t9 to counting discrimination circuit C.
Added to 4. The C4 is a specific button or a continuous line t.
9, it applies a count pulse to counter C5 via line t15 under the control of flip-flop FFI. Here, the operation of 04 will be explained. Counting discrimination circuit C
4 outputs one count pulse to line t15 when 1'' is added from line t9 when flip-flop FF1 is reset. When FFI is in the reset state, line t
If '0' is added from 9, FF1 is connected to line t11.
is set via line t14, gate C6 is opened, and the contents of counter C5 are sent to distributor D1. After the data of counter C5 is sent out, the contents of counter C5 are reset to 0 via line t16. flip flop FF
, 1 is set, contrary to the above operation, 10 is set.
'' is applied from line t9, the count pulse is applied from line t9.
15, and when @1'' is added, it resets the flip-flop FFI, opens the gate C6, and resets the counter C5 to 0.
From there, it is stored in the vector register by the distributor D1 via 1f#t17.

The above operation is repeated for the vector length that can be stored in the vector register, and the processing of this instruction is completed.

In this instruction specification, since the input vector length specified in field j and the output vector length specified in 1 field are generally different, it is necessary to provide a register to record the number of openings and closings of gate C6, or to change the output vector element tag. at the end of
Add an end mark such as to -1n to clearly indicate the vector length.

Various modifications can be made in addition to the description of this embodiment.

For example, the specific button of the control vector may be fixed or may be changed by a command. Register R4 is necessary when it can be changed by an instruction, but when it is fixed, the signal line can be set to a 1 #) or '0'', so register R4 is not necessarily necessary. The specific button of R5 may also be fixed or may be changed by a command. If a fixed button is sufficient, ``'1'' or 10'' may be added directly from the signal line. Similarly, mask register R2 can have both variable and fixed functions.

Furthermore, instead of using the data in the vector register shown in this embodiment as the control vector, a vector mask register (this register is used for masked vector operations and is a common register in vector processors) is used. You may also use the vector mask inside. At this time, the elements to be counted are controlled according to the contents of the vector mask register.

Furthermore, in this embodiment, the control vector and the mask register can be specified separately as independent specifications, but it is also possible to use the contents of the vector element of the control vector as a mask to make the portion to be extracted variable. .

〔Effect of the invention〕

As shown in this embodiment, according to the present invention, the process of extracting a portion of each vector element of vector data and counting consecutive specific patterns among them can be processed at high speed as vector processing.

In particular, this processing is suitable for run-length encoding in image processing and image compression file creation processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the processing performed by the present invention, and FIG.
The figure shows an example of vector processing performed in the present invention.
FIG. 3 is a diagram showing an embodiment of the present invention. R1...Instruction register, R2...Input button mask register, R3...Register that holds the vector elements of the data vector,'fL4...Register that holds the vector elements of the control MI vector, R5...・Comparison button register, ■o to ■fi-1...vector register. 1st b 2nd 1 ``

Claims (1)

[Claims] 1. A circuit that extracts a portion of a plurality of vector elements in a data vector in order to extract a portion of a plurality of vector elements in the data vector and generate the number of specific patterns included in the data. A vector processor characterized by having: a counting circuit that holds the number of specific patterns existing in the data extracted so far; and a circuit that converts the counting result into vector data. 2. In the vector processor of item 1, in order to enable control using a control vector, a comparator that checks whether the contents of the vector element of the control vector have a specific content or a detector that detects that the content is a specific content. , a vector processor characterized in that the content of the aforementioned holding register that holds the data extracted and counted up to that point is changed according to the comparison or detection result. 3. In the vector processor of the first term, in order to enable control of the extraction part of the data vector by the control vector, the extraction point of the vector element of the control vector and the extraction point of the contents of the first term holding register are variable. A vector processor characterized by: