SU1062712A1 - Microprogram processor - Google Patents

Description

And, the element is NOT and the element is OR, while the address input, information input, sampling control input, low word record strobe input, high word record strobe input, high word output and accumulator low word output are connected respectively to the address switch output address, informational the input of the block, the output of the element OR, the output of the first element AND, the output of the second element AND, the first and second outputs of the block, the first inputs of all the elements AND connected to the first control input of the block, the control output of the switch address connected to the second input of the first element AND and the input of the element NOT whose output is connected to the second input of the second element AND, the second inputs and outputs of the third and fourth elements AND are connected respectively to the second and third control inputs of the block and the first and second inputs of the OR element, the first and the second address inputs and the first and second control inputs of the address switch are connected respectively to the first and second address inputs of the block and the second and third control inputs of the block.

3. Processor according to claim 1, characterized in that the micro-command address generation unit contains the micro-instruction address register, an address decoder, a group of OR elements and three groups of AND elements, the first inputs of which are connected respectively to nepBfcjM, the second and third address inputs of the block, the second inputs of elements AND of all groups are connected to the control input of the block, the first, second and third inputs and outputs of the elements OR of the group are connected respectively

With the outputs of the elements of the first, second and third groups and the register of the address of the microinstructions, the outputs of the junior and senior parts of which are connected respectively to the address output of the block and the input of the address decoder, and the output of the address decoder is connected to the control output of the block.

4. The processor according to claim 1, wherein the processing unit comprises the first and second register nodes, a switch, an adder, a shifter, a data register and a comparison node, the first and second inputs and output of which are connected respectively to the control input of the block , the output of the adder and the second address output of the block, the information and control inputs of the first and second nodes of the registers are connected respectively to the output of the shifter and the control input of the block, the outputs of the first and second nodes of the registers are connected to the first information inputs of responsibly the adder and switch, the second information input, the control input and the output of which are connected respectively to the information input of the block, the control input of the block and the second information input of the adder, the control input and output of the adder are connected respectively to the control input of the block and the information input of the shifter, the control input and output of which are connected respectively to the control input and the first address output of the block, and the information input, control input and output of the data register are connected respectively to the output of the shifter, the control input and the information output

one

The invention is related to computer technology and is intended for use in small digital microprogrammed Jinax digital computers (mini- and micro-computers).

As is well known, the basis for building microprocessor processors is the use of permanent storage devices for storing microprograms. At the same time, the development of technology, the advent of new hardware and software for implementation, the increasing amount of firmware and the need for its most effective use led to the introduction of a microprogram memory with overwriting into the computer.

including random access memory, and building on its basis of processors with dynamic firmware programming. Dynamic firmware improves the functionality of traditional ways of applying firmware, provides the ability to simulate using firmware

management level, development of new language tools, availability of microprogramming to the user, etc. Microprocessors with dynamic microprogramming open new

opportunities when using them to build high-performance large computers and multisystems. At present, two approaches are mainly used in the construction of processors with dynamic firmware programming. The first step, a move, is to use the own memory of the control unit, the recording in which is carried out according to the chosen algorithm from the main memory, microprogram fixed memory or external devices l. The second approach is to use the main computer memory for storing and executing microprograms from it. In this case, there is no need for additional rewriting equipment, development of algorithms for preliminary calling the microprogram during their operational change, and time spent on rewriting the necessary microprograms, since they can be stored in a common field of the user program. In addition, there is no need for special commands for stalking and procedures for locating microprograms. The closest in technical essence to the present invention is a microprogram processor capable of executing microprograms stored in the microprogram constant of the memory or in the main memory. This firmware contains the main memory block, the microprogram memory block, the command register, the data register, the AND elements, the microinstruction switch, the microinstructor register with the address and operating parts, the microinstruction address generation unit, the control decoder, the processing unit, and the control block addressing the main memory. The output of the main memory block is connected to the input of the register coman and the data register. The first output of the microprogram memory block is connected to the information input of the And elements. The second output of the microprogram memory block is connected to the first input of the switch, the second input of which is connected to the output of the data register and the H formation input of the processing block I and the switch elements. connected to the inputs of the address and one of the parts of the register of micro-instructions, respectively. The output of the address part is connected to the first input of the microcommand address generation unit whose second input is connected to the first command register house, the third input is connected to the control output of the processing unit, and the output is connected to the input of the microprogram memory block. The controls of the output of the spindle block are connected to the control inputs of the AND elements and the switch, and the address output is connected to the address input of the main memory block. The addressing control unit is also connected to the processing unit, the information outputs of which are connected to the corresponding input of the main memory unit. The output of the operating section of the micro-command register is connected to the input of the control signal decoder, the outputs of which are connected respectively to the control inputs of the processing unit, the micro-address address generation unit, the main memory address control control unit and the control inputs of the command register, the data register, respectively. The disadvantage of the known processor is low speed. This is due to the fact that the cycle of accessing the main memory in modern computers is more (usually several times) the cycle of accessing the permanent microprogram memory. Therefore, in the main memory access mode, the execution time of the firmware is increased. Moreover, the described organization of the processor limits the microinstruction width of the main memory, which, for example, in modern mini-computers is mainly 16 bits. This leads either to a limitation of the power of the microcommand or to the use of strong encoding methods. In both cases, the speed is reduced, since the power of the microcommand is determined by the number of concurrently running micro ops, and strong encoding methods complicate the decryption scheme, which introduces additional delays. The purpose of the invention is to increase the speed of the firmware processor. The goal is achieved by the fact that in a firmware processor containing a main memory block, a main memory address control block consisting of an address decoder and address register, a processing block, a microprogram memory block, an micro-command address generation unit, a micro-command switch, a micro-command register , the control signal decoder and command register, the control input of which is connected to the output of the control signal decoder, the information output, the first, second address outputs and the control input of the processing unit The bots are connected respectively to the information input of the main memory, the address input of the address register, the first address input of the microinstructor address generation block and the output of the control decoder, the control input, the output of the upper part and the lower part of the address register are connected respectively to the output of the control decoder signals, the address decoder input and the address of the main memory block, the control input, the second and third address inputs, the address output, and the control output of the ad-shaping unit microcommand rests are connected respectively to the output of the decoder of control signals, the output of the command register, the output of the address part of the register of microcommands, the address input of the microprogram memory block and the control input of the microinstruction switch, the first and second information inputs and output of which are connected respectively to the first and second outputs of the block the microprogram memory and the register of microinstructions, the output of the operating part of the register of microinstructions is connected to the input of the decoder of control signals, the output of which is connected Inen with control inputs of the main memory block and microprogram memory block, a RAM block and a data switch are entered, the first and second control inputs and the first, second and third information inputs of which are connected respectively to the outputs of the address decoder and low register bit the address, the output of the main memory block to the first and second outputs of the block memory, the data switch output is connected to. information inputs of the command register and processing unit, and: the first, second and third control inputs, the first and second address inputs, the first and the second outputs of the operative memory unit are connected to the information output of the processing unit, the output of the decoder signals, the output of the address decoder, the control output of the microcommand address generation unit, the output of the lower part of the address register, the address output of the microcommand address generation unit, the third and fourth information inputs m switch microinstructions. In addition to the toga, the RAM block contains a drive, an address switch, four AND-elements, an NOT element and an OR element, while the address input, information input, sample control input, input of the low word record, the high word record input, the high word output the words and the low word of the accumulator are connected respectively to the address output of the address switch, the information input of the block, the output of the element OR, the output of the first element AND, the output of the second element AND, the first and second outputs of the block, the first inputs of all elements And connected to the first control input block, the control output of the address switch is connected to the second input of the first AND element and the input of the NOT element, the output of which is connected to the second input of the second And element, the second inputs and outputs of the third and fourth AND elements are connected respectively, with the second and third control inputs of the block and the first and second inputs of the OR element, the first and second address inputs and the first and second control inputs of the address switch are connected respectively to the first and second address inputs of the block and a second and third inputs udravl yuschim b.loka. Moreover, the microinstruction address generation unit contains the microinstruction address register, an address decoder, an OR group of elements and three groups of AND elements, the first inputs of which are connected respectively to the first, second and third address inputs of the block, the second inputs of the AND elements of all groups are connected to the control input of the block The first, second and third inputs and outputs of the elements OR of the group are connected respectively to the outputs of the elements AND of the first, second and third groups and the register of the address of microinstructions, the outputs of the youngest and oldest parts of which are under The switches are connected respectively to the address output of the block and the input of the address decoder, and the output of the address decoder is connected to the control output of the block. The processing unit contains the first and second register nodes, the switch, the adder, the shifter, the data register and the comparison node, the first and second inputs and the output of which are connected respectively to the control input of the block, the output of the adder and the second address output of the block, information and the control inputs of the first and second register nodes are connected respectively to the output of the shifter and the control input of the block; the outputs of the first and second register nodes are connected to the first information inputs of the adder and the comm, respectively the second information input, the control input and the output of which are connected respectively to the information input of the block, the control input of the block and the second information input of the adder, the control input and output of the adder are connected respectively to the control input of the block and the information input of the shifter, the control input and the output of which is connected respectively to the control input and the first, address output of the block, and the information input, the control input and output of the data register are connected respectively to the output of the cd igatel, control input and a data output unit.

FIG. 1 shows a block diagram of the firmware process in FIG. 2 is a functional block diagram of the RAM / FIG. 3 is a block diagram of the control unit for addressing the main memory in FIG. 4circuit of the microinstructions address generation unit; in fig. 5 is a schematic of the processing unit.

The microprocessor processor contains the main memory unit 1, the address and information inputs of which are connected respectively with the address output of the address control unit 2, the main memory and the information output of the processing unit 3, and the unit. 4 of the microprogram memory, the input of which is connected to the address output of the microcommand address generation unit 5, and the first and second outputs to the first and second information inputs of the microcommand switch 6 (Fig. 1). The processor also contains a decoder 7 control signals, the input of which is connected to the output of the operating part 8 of the register 9 microcommands, and the outputs with the first control inputs of blocks 1 and 4, block 10 RAM, block 3, register 11 commands, block 5 and block 2. Block 2's address input is connected. I am the first address output of block 3} the second address output is ko-. The second one is connected to the first address input of the block 5, the second and third address inputs of which are connected respectively to the outputs of the register 11 and the address part 12 of the register 9, the last of which is connected to the output of the switch 6 micro-commands. The information, the first and second adrenal inputs of the RAM 10 are connected respectively to the information and address inputs of block 1 and the input of block 4. In addition, the processor contains a data switch 13, the output of which is connected to the information inputs of block 3 and register 11, the first a control input connected to the second control input of the unit 10 and the first control output of the unit 2, the second control output of which is connected to the second control input of the switch 13. The first information input of the switch 1 3 is connected to the output of block 1, and the second and third information inputs are connected respectively to the first and second outputs of block 10 and to the third and fourth information inputs of switch b ,. moreover, the control input of the latter is connected to the control output of block 5 and to the third control input of the block 10.

The operational memory unit 10 contains a storage unit 14, the bit width of which is equal to twice the size of unit 1 and consisting of the high word drive 15 and the low word drive 16 (Fig. 2}. The block 10 also contains the address switch 17, the first 18, the second 19 , third 20, fourth 21 elements AND, element 22 NOT, element 23 OR, the output of which is connected to the first control input, which is the input of the sample, accumulator 14, whose address input is connected to the address output of the switch 17. The control output of the switch 17, low bit output It is connected to the first input of the element 18 and the input of the element 22, the output of which is connected to the first input of the element 19, whose second input, which is the input of the recording signal, is connected to the first control input 24 of block 10 and to the second input of the element 18, the output of which connected to the input of the strobe of the storage drive 16, which is the second control input of the storage device 14. The third control input of the storage device 14, which is the input of the recording strobe i of the storage device 15, is connected to the output of the And 19 element, the information input 25 of the block 10 is connected to the information input accumulator .14, the first address input of the switch 17 is connected to the first address input 26 of block 10, the second address input 27 of which is connected to the second address input of the switch 17. The first control input of the switch 17 is connected to the first input of the AND element 20 and the second control input 28 unit 10, the third control input 29 of which is connected to the second control input of the switch 17 and the first input of the element 21, the output of which is connected to the first input of the element 23. The second input of the element 23 is connected to the output of the element 20, the second input of which isA sign of accessing the memory for operational information is connected to the input 24 of the block 10. At the same time, the second input of the element 21, which is a sign of the request for the microprogram information, is connected to the input 24 of the block 10, the first 30 and. the second 31 outputs of which are connected respectively to the outputs of the accumulator 15 and the accumulator 16. The accumulator 14 can be made on integrated semiconductor chips K565RU2A.

The unit 2 for managing the addressing of the main PS1m (Fig. 3) contains the address register 32, consisting of the eldest 33, the younger 34. the address parts and the low order 35, the address decoder 36, the input of which is connected to the output of the elder 33 part of the register 32, and the output of the decoder 36 is connected to the first control output 37 of block 2, the address output 38 of which is connected to the output of register 32, the input of which is connected to the address input 39 of block 2, the second control output 40 of which is connected to the output of the lower bit 35 of the address control input 41 of block 2 is connected to control 32 register input.

The micro-command address generation unit 5 (FIG. 4) contains the micro-command address register 42 consisting of the upper 43 and the lower 44 parts, the address decoder 45, the group of 46 elements OR, the first 47, the second 48, the third 49 of the group of elements AND whose outputs are connected with the inputs of the corresponding elements 46 OR, and the first inputs of which are connected respectively to nepBtoM 50, the second 51-, third-52 address inputs of block 5. The control 53 output of block 5 is connected to the output of the decoder 45, the input of which is connected to the output of the older 43 part of the register 42. Register register .42 is connected to the output. m OR element group 46, and an output - with a yield of 54 address unit 5, a control input 55 which is connected to the second

entrances of groups 47, 48 and 49 el.

Comrade and.

The processing unit 3 (Fig. 5) contains p €; the left register node 56, the second register node 57, the switch 58, the adder 59, the comparison node 60, the shifter 61 and the data register 62, the output of which is connected to the information output 63 of block 3, The first address output 64 of which is connected to the inputs of the register 62, nodes 56 and 57 to the output of the shifter 61. The input of the shifter 61 is connected to the input of the node 60 and the output of the adder 59, the first and second information inputs of which are connected respectively to the output of the node 56 and the output of the switch 58 The first. And the second information inputs are comm. torus 58 is connected respectively to the output of node 57 and information input 65 of block 3, control input 66 of which is connected to control inputs of nodes 56 and 57, a summator 59, switch 58, a shifter 61, register 62 and node 60, the output of which is connected to the second address output 67 of unit 3. K155 series microcircuits can be used for the technical implementation of processing unit 3. In this case, nodes 56 and 57 can be executed on K155 RU2 memory chips, switch 58 - on K155 LR1 chips, adder 59 - on K155.PM chips, data register 62 - on K155 triggers. The shifter 61 can be performed on the chip K155 KP2,

herewith, four operations are implemented, for example: direct information transfer, left and right shift by one bit, as well as cyclic shift by one byte. Node 60 is a combination of combinational circuits that provide for the generation of corresponding features. So, for example, in order to generate the signs of zero result and overflow, this block will include respectively the OR element for all bits of the result and the EXCLUSIVE OR element for transfers from the higher and previous bits of the result.

The processing unit 3 can also be performed on the basis of the microprocessor element K589 IC02. In this case, the output of the register of the battery is the information output of block 3, the output of the address register is the first address output, the outputs of the transfer signals Co and the overflow SSP are the second address output. The control input of block 3 is the input of the operation code decoder, and the information input is input information highway B.

. Consider the operation of the firmware processor. At the current moment of time the register 9 enters the next micro-command. Its operational part

8 is fed to the input of the decoder 7, which produces a set of signals that control the operation of the blocks

I, 4 and 10, blocks 2 and 3 and register

II. The address part 12 of the micro-command is fed to the input of block 5, which forms the address of the next micro-command, taking into account the signs of branching, coming through the condition bus from block 3. When generating the initial microprogram addresses, block 5 also sends the operation code of the control word from register 11. Depending on from the generated address code of the next micro-command, which is analyzed by block 5, the access occurs either

to block 4, or by the second address input to block 10.

In the first case, the read information enters the register 9 from block 4 through the first and second information inputs of the switch 6 by the direct value of the signal at the control output of block 5. In the second case, from block 10, in accordance with the structure described above, a double word is read enters the register

9 through the third and fourth information inputs of the switch 6 by the inverse of the signal at the control output of block 5. If the current microcommand specifies that it is necessary to access data or another command word, which determines the decoder 7, the address from the first output lo 3 enters the block 2, which analyzes the address and, depending on its value., Accesses block 1, or at the first address input to block 10. In this connection, information will be read either from the output of block -1, from the first or from wto th output block 10. The latter is determined by the particular address block 10. The alternation switch 13 is supplied to the read information register 11, when the next read word komandnoe- or unit 3, if data is read. The switch 13 is controlled by signals at its first and second control inputs from the outputs of block 2. When there is a signal at the first control input, switch 13 transfers information from the output of block 1. If there is no signal at the first control input, switch 13 transmits information from the first or second output. The iO block, depending on the parity of the address of block 10, which is determined by the signal at the second control input of the switch 13.

Thus, when accessing the first address input, block 10 is a continuation of the address space of block 1, and when accessing the second address input, a continuation of the address space of block 4. Therefore, in block 10, both commands and data can be stored as well Moreover, the firmware download, as well as any other information, to the RAM block is performed when accessing the first address input. Since the volume of block 10 is relatively small compared to the total amount of main memory, it can be made as a semiconductor memory device with a high speed equal to the speed of block 4. On the other hand, when accessing the second address input from block 10, a double word is read which allows you to select the micro-command and block 4 bits to be equal to the double bits of block 1.

In accordance with the described principle of the processor and shown in FIG. 2-5 functional blocks of blocks 10, 2, 5 and 3, these blocks operate as follows. The operational memory unit 10 (Fig. 2) Will be able to operate in three modes: the mode of recording data, commands or micro-instructions, the mode of reading data or commands, the mode of reading microx1and.

The operation of block 10 in the recording mode is possible only at the input of block 26

If in decoder 36 of block 2 it is determined that the address to memory access belongs to block 10, the single level of the signal from output 37 of block 2 is fed to input 28 of block 10, allowing the address to pass from input 26 of block 10. cut the switch 17 to the input of the accumulator 14 and also permit the passage of the memory access signal (read or write) coming from the output of the decoder 7 to the input 24 of block 10 and then through elements 20 and 23 to the input of the drive 14. The recording signal is passes from the output of the decoder 7 through the input 24 of block 1 and the element 18 on the input d, strobe, record 16 or through element 19 to the strobe input of record 15, depending on the parity of the address received from the control output of switch 17. At its single value, element 18 opens, and at zero value - element 19. Thus, if there is a recording signal, if the specified address belongs to block 10 by the address code at the output. 26, information from information input 25 is recorded, and it is carried out either to drive 15 or to drive (Drive 16, depending on the resolution of the parity of the address.

The operation of block 10 in the mode of reading data or commands occurs as follows 1. If in the decoder 36 of block 2 it is determined that the memory address belongs to block 10, the unit signal level at input 28 of block 10 allows the address to pass from input 26 unit 10 through the switch 17 to the input of the accumulator 14, and also allows the circulation signal from the input 24 of the unit 10 to pass through the elements 20 and 23 to the input of the sample of the accumulator 14. At the outputs 30 and 31 of the accumulator 14, the read information appears. The reading of micro-commands from block 10 is performed when the decoder 45 of block 5 determines that the address of the micro-command formed on register .42 belongs to block 10. In this case, the unit level of the output from the output 53 of the decoder 45 is fed to the input 29 of the patch 10 allowing the passage addresses of microcommands from input 27 of block 10 through switch 17 to input of accumulator 14 and allowing the passage of the signal of sampling of microcommands coming from output of decoder 7 to input 24 of block 10 and further through elements 21 and 23 to input of sample of accumulator .14. At AmoA 30 and 31 of the accumulator 14, a read-in micro-command appears.

In the main memory addressing control block 2 ((FIG. 3), the address is received from address input 39 to register 32 under the control of a signal at input 41. Decoder 36 analyzes the contents of the upper part 33 of register 32 and if it matches the address with proper block 10, generates a single signal at output 37. The lowest bit 35 is output from the block output 40, indicating a parity of the word address. From the block address output 38, the contents of register 32 are output.

In block 5 of the formation of the address of the microinstructions (Fig. 4), under the control of the signals at the input 55, the address of the microcommand is received to register 42 via element 46 from the inputs 51 and 52 kt by disjunctive injection from inputs 50 and 52. The decoder 45 analyzes the contents of the older 43 parts of register 42 ij; if it matches the address belonging to block 10, it generates a single signal at output 53. From output 54, the contents of register 42 of microcommand addresses are output. ,

The processing unit 3 (Fig. 5), depending on the microcommand being executed under the influence of control signals at input 66, can perform an arithmetic logic operation in the adder 59 on one or two operands coming from nodes 56 and 57 or from input 65 to generate characteristics of the result in node 60, shift the result of arithmetic logic operation on the shifter 61, enter the result of the operations in nodes 56 and 57 or in the register 62. The result of the operation is also output through output 64 of block 3 to register 32 into block 2. From output 63 content is displayed register 62, and from exit 67 - signs of the result of the operation.

These features make it possible to increase the speed of the microprocessor processor in comparison with the known processors by increasing the width of microcommands and the absence of time losses for reading microcommands from the RAM.

The use of double-bit memory / 32 bits) in this processor allows you to simultaneously perform up to six operations ({transfer, arithmetic-logical operation, shift, inversion, setting of signs and checking conditions). The use of fast RAM for storing the firmware in this processor several times increases the speed of their execution.

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Claims (4)

1. The MICROPROGRAM PROCESSOR, containing the main memory block, the address control unit of the main memory. a memory consisting of a decoder of an address and an address register, a processing unit, a microprogram memory block, a micro command address generation unit, a micro command switch, a micro command register, a control signal decoder and a command register whose control input is connected to the output of a control signal decoder, information output, the first , the second address outputs and the control input of the processing unit are connected respectively to the information input of the main memory block, the address input of the address register, the first address entry As for the formation of the micro-command address and the output of the decoder of the control signals, the control input, the output of the senior part and the output of the lower part of the address register are connected respectively to the output of the decoder of the control signals, the input of the address decoder and the address input of the main memory unit, the control input, second and third address inputs, address the output and control output of the micro-command address generation unit are connected respectively to the output of the decoder of the control signals, the output of the command register, the output of the address part of the register microcommands, the address input of the microprogram memory block and the control input of the microcommand switch, the first and second information inputs and the output of which are connected respectively to the first second outputs of the microprogram memory block and the input of the microcommand register, the output of the operational part of the microcommand register is connected to the input of the control signal decoder, the output of which is connected with control inputs of the main memory block and the firmware block, characterized in that, in order to increase speed, it contains there is a random-access memory block and a data switch, the first and second control inputs and the first, second and third information inputs of which are connected respectively to the outputs of the address decoder and the lower order of the address register, the output of the main memory block, the first and second outputs of the block RAM, the output of the data switch is connected to the information inputs of the command register and the processing unit, and the information input, the first, second and third control inputs, the first and second address inputs, the first to second outputs of the opera block main memory are respectively connected to the data output of the processing unit, the output of decoder control signals, the output of the address decoder, control output of the block forming microinstruction addresses, output low part · register addresses, the address output unit forming microinstruction addresses, the third and fourth data inputs microinstruction switch. 2. The processor according to p. 1, characterized in that the RAM contains a drive, address switch, four elements SU ... 1062712 And, the element is NOT and the element is OR, while the address input, information input, sample control input, low word write strobe input, high word write strobe input, · high word output and low word output of the drive are connected respectively with the address output of the address switch, the information input of the block, the output of the OR element, the output of the first AND element, the output of the second AND element, the first and second outputs of the block, the first inputs of all AND elements are connected to the first control input of the block, the control output of the address switch connected to the second. the input of the first AND element and the input of the NOT element, the output of which is connected to the second input of the second AND element, the second inputs and outputs of the third and fourth AND elements are connected respectively to the second and third control inputs of the block and the first and second inputs of the OR element, the first and second address inputs and - the first and second control inputs of the address switch are connected respectively to the first and second address inputs of the block and the second and third control inputs of the block. 3. The processor according to claim 1, characterized in that the micro-command address generating unit comprises a micro-command address register, an address decoder, a group of OR elements and three groups of AND elements, the first inputs of which are connected respectively to the first, second and third address inputs of the block, the second inputs of the AND elements of all groups are connected to the control input of the block, the first, second and third inputs and outputs of the elements OR groups are connected * respectively to the outputs of the And elements of the first, second and third groups and the input of the micro address command register, the output is small the upper and lower parts of which are connected respectively to the address output of the block and the input of the address decoder, and the output of the address decoder is connected to the control output of the block. 4. The processor according to π. 1, wherein the processing unit contains the first and second register nodes, a switch, an adder, an shifter, a data register and a comparison node, the first and second inputs and output of which are connected respectively to the control input of the block, the output of the adder and the second address output block, the information and control inputs of the first and second register nodes are connected respectively to the output of the shifter and the control input of the block, the outputs of the first and second register nodes are connected to the first information inputs', respectively, of the sums torus and switch, the second information input, the control input and output of which are connected respectively to the information input of the block, the control input of the block and the second information input of the adder, the control input and output of the adder are connected respectively to the control input of the block and the information input of the shifter, the control input and output of which connected respectively to the control input and the first address output of the block, and the information input, control input and output of the data register are connected respectively to you ode shifter, the control input and data output b £ eye.