SU1293729A1 - Microprogram control device - Google Patents

Abstract

The invention relates to microprogram control and can be most effectively used in computer technology, for example, in computers, in the construction of control systems, as well as in stand-alone microprogram automata. The purpose of the invention is to increase speed. The device contains a block of memory of micro-commands 1, a register of 2 micro-commands, a multiplexer 3 of logical conditions, a block of 4 analysis of logical conditions containing two elements NOT 14, 15, three elements AND 16, 17, 18 and element OR 19, adder 9 addresses, register 10 addresses and switch 11 addresses. Introduction of the type of transition to the microcommand format, logical conditions analysis block, address adder and address switch made it possible not to insert special control microcommands into the microprogram, which made it possible to achieve the purpose of the invention, 2 Il. with (L

Description

The invention relates to microprogram control and can be used in computing, for example, in a computer, in building control systems, as well as in stand alone microprogram automata with microinstructions, the address and operating parts of which are comparable in size.

The purpose of the invention is to increase speed.

Figure 1 shows the functional diagram of the firmware control device; 2 shows timing diagrams of its operation.

The device contains a block of micro-command memory 1, a register of 2 micro-commands, a multiplexer 3 logical conditions, a logic conditions analysis unit 4, a reset input 5, the first 6, the second 7, and the third 8 synchronous inputs, the adder 9 addresses, the address register 10, the address switch t1, output 12 and a group of 13 inputs of logical conditions,

The block of the analysis of logical conditions contains two elements NOT 14 and 15, - three elements and 16-18 and element OR 19.

In addition, the register 2 micro-commands has an output of 20 signs of the type of transition and the output 21 of the signs of the type of micro-commands.

The device works as follows.

Pgi by the arrival of the start-up signal at device 5, the address register 10 is set to the initial zero state, arriving at the input group A of the adder 9, therefore, at the output of the adder 9, the output state is equal to one because at the lower bit of the input group B - I, and at the input P O), since at the output of the element I 1 there is a signal O (at both inputs of this moment there are signals O at a given moment). The control input of the switch II also contains the signal O, and, therefore, the output of the switch 11 through its first information input is connected to the output of the adder 9, the output state of which is equal to one. This output state of the adder 9 is fed to the input of the memory 1, As a result, the output of the first memory line is set to the output of the memory 1, the output from the memory I of the memory I to the input D of micro-commands 2 and

to the information input of the switch 115 but does not pass to the output of the latter.

At the time of launch, a synchronization device (not shown) generates only a series of first clock signals SI1, arriving at input 6 of the device, connected to input C of the register 2 micro-instructions. The leading edge of the clock signal, SI1, the contents of memory block 1 is rewritten into register 2 of micro-instructions and is fed to output 12 of the device for execution. The PPE 5 signal generated by the synchronization device is currently equal to o.

Let the microinstruction selected from the first line of memory block 1 and rewritten along the leading edge of SI1 in

microinstructions register, i.e. executable microinstruction, unconditional. Then the state of output 20 of register 2 micro-instructions is equal to 0. Regardless of the state of output of multiplexer 3 conditions and output 21 of register 2 of micro-commands, signals are present at the transfer input P of the adder 9 and at the control input of the switch 11; on the first and second outputs of the block

signals oh

four

When the initial start signal is removed from input 5, the synchronization device begins to generate (after passing the signal CI) the PPE signal, with the receipt of which at this moment the output state of unit 4 does not change.

With the arrival of the signal CI2, the output state of the adder 9 (one). Is rewritten (by the leading edge of CI2) through the switch 11 into the TO register of the address, i.e. the output of the register 10 address is set to a single output state, which is fed to a group of inputs A of the adder 9. At the output of the latter, a state equal to two is established (one from the group of inputs A plus one from the lowest bit of the group of inputs B),

As a result, according to the output state of the adder 9 in block 1 of memory, a second line is selected, the contents of which are fed from the output of block 1 of memory. To input D of register 2 of microcommands and to the corresponding information input of switch 11, However, the output of switch 11 is The output of memory block 1 cannot pass, because at the control input

switch 11 has a signal O,

and the first input is the value

output adder 9.

With the arrival of the next clock signal SI1, the output state of memory block 1 is rewritten (on the leading edge of SI1) into register 2 of micro-instructions and enters output 12 of the device for execution. Consequently, in this case (when executing a nonconditional microcommand), the natural (by +1) way of addressing is performed, and the duration of the machine cycle (microcommand) is equal to two cycles: SI1 and SI2.

Consider the operation of the device for the case when the microcommand is executed, i.e. the microinstruction selected in memory block 1 (for example, from the 1st line) and rewritten on the leading edge of SI1 into the register 2 microcommands is conditional.

Then the exit status of 20 registers of 2 micro-instructions is l. This output state of output 20 of register 2 is fed to the corresponding input of block 4.

At the input A of the multiplexer 3 conditions, the condition code is included in the conditional microcommand that is executed. At the output 21 of the register 2 microinstructions, there can be a signal O or 1 (depending on what was included in this microcommand during microprogramming).

Depending on the fulfillment (non-fulfillment) of the condition, as well as the state 1 and the output 20 of the register of 2 microcommands in the device, two situations are possible: the output state of the multiplexer 3 conditions and the output 20 of the register of 2 microcommands, and therefore the state of the inputs of block 4 are equivalent or unequal . In each of the indicated situations, the formation of the address of the next microcommand on the execution of the amp & conditional microcommand is carried out in its own way.

Consider the operation of the device in each of these situations.

Let the state of the inputs of block 4 be equivalent, i.e. Both inputs have a 1 or O signal.

The output state of the adder 9 is equal to one (since it is agreed that the executable conditional micro-instruction is selected from the first line of the first 1 unit). With the arrival of the PPE signal at one of the inputs of the element 16, the signal is set at the output of the latter

five

0

five

0

five

0

g

nal, as at the second entrance ele. At the time of And 16 there is also a signal 1 from the output 20 of the register of 2 micro-instructions. The signal 1 from the output of the element And 16 goes to the first inputs of the elements And 17, 18 and to the input P of the transfer of the adder 9, increasing the contents of the last (it was equal to 1) by one, i.e. the output state of adder 9 becomes 2. For this output state of adder 9 in memory block 1, a second line is selected, the contents of which go to input D of register 2 micro-instructions and to the corresponding information input of switch 11. At the control input of switch 11, if present the signal of the PPE signal is present 1., since the output of the element OR 19 is the signal l at the equivalent states of the inputs of block 4. Indeed, if the output state of the multiplexer 3 and the output 21 of the microcomputer register 2 is equal and equal to 0, then The signal of the PPE at the output of the element 17 sets the signal l, and in the case of a single output state of the inputs of block 4, the single state is set (in the presence of the PPE signal) to the output of the element 18. Consequently, in any of the states of equivalence of the inputs of block 4 at the output of the element OR 19 and, therefore, at the control input of switch 11 is signal 1. The output state of memory block 1 (the contents of its 2nd line) goes through switch 1t The input D of the address register 10 and with the arrival of the second clock signal CI2 is recorded in the register 10 of the address (on the leading edge of the clock signal CI2).

This output state of the address register 10 is fed to a group of inputs A of the adder 9. At the output of the adder 9, a state is set equal to the contents of the output of the register 10 (the content of the 2nd line of the memory block 1) increased by 2. ; stored at the output of the adder 9 until the end of the PPE signal.

With the removal of the PPE, the output state of the adder 9 is reduced by one (because the O signal is set at the P input), i.e. becomes equal to the content of the second line of memory 1 plus one. This output condition of the adder 9 is the address of the following microcommand.

for this case (the case of equivalent input states of the inputs of block 4). Therefore, in the second line

memory unit 1 must be encoded. the address is one less than the actual address of the next microprogram microcommand. And at the address thus formed in memory block 1, a corresponding ruler is selected, the contents of which are written to register 2 of micro-instructions on the leading edge of the SI and arrive at information output 12 of the device for execution.

Consider the operation of the device for the case of unequal state of the inputs of block 4.

Let the executable conditional microinstruction be selected from the 1st line of memory block 1 and, on the leading front, SI1 is rewritten in the register of 2 microcommands. Then the initial output state of the adder is one.

With the arrival of the PPE signal, signal 1 is set at the output of element 16 (since signals 1 are present at both inputs of element 16) signal 1 at the output of element 16 is fed to the first inputs of elements 17 and 18 and to the transfer input P of the adder 9.

At the output of the latter, a state equal to two is established (it was equal to one + one from input P). This output state (two) of the adder 9 is fed to the input of memory block 1 and to the corresponding information input of switch 11, at the control input of which signal O is present. Indeed, if any 1 is unequal to the output state of the inputs of block 4,

19 signal O is present, since the outputs of the elements 17 and 18 in this case also contain signals O.

Consequently, the output state of the adder 9 is fed through the switch 11 to the input P of the register 10 of the address AND on the leading edge of the clock signal CI2 is rewritten into it. The group of inputs A of the adder 9 receives a state equal to two, and at the output of the adder until the end of the PPE signal a state is established

equal to four. I

After removing the PPE signal, the output of the adder 9 is set to three (it was equal to 0

five

0

fiem minus one from input P). This output state of the adder 9 (three) is the address of the following microcommand,. those. the address of the following microcommand is equal to the address executed

(one) plus two. I

In this way, the address of the next microcommand is formed in the case of unequal states of the inputs of block 4. The corresponding (in this case, one third) line is selected by the address thus formed in memory block 1 and its contents on the leading edge of the clock signal CI1 are written to the address register 2 to be executed. Further operation of the device is determined by whether the selected microcommand is conditional or nonconditional.

Claims (1)

Invention Formula five 0 A microprogram control device containing a microinstructions memory block, a microinstructions register, a logic conditions multiplexer and an address register, the outputs of the microoperations field and the logic conditions register register of microcommands are connected respectively to the output of the device and the logic conditions multiplexer control input, the group of information inputs of which are connected to the group of inputs of the logical conditions of the device, the information The 5 register input of micro-commands is connected to the output of all fields of the micro-command memory block, the synchronous input of the micro-commands register and the synchronous input of the address register are connected respectively to the first and second synchronous inputs of the device, the reset input of the address register is connected to the reset input of the device, characterized in that .speed of speed, it contains an address switch, address adder and a logical conditions analysis block containing three AND elements, two NOT elements and an OR element, the third synchronous input of the device connected to the first at the input of the first element And, the second input of which is connected to the output of the type of register of microinstructions, the output of the sign of the type of microcommand of which is connected to the first input of the second element and through the first element is NOT connected to the first input of the third element And, the second input of which is connected to the second the input of the second element And, the output of the first element And and the transfer input of the address adder, the first and second information inputs of which are connected respectively to the input of the unit constant of the device and the output of the address register, and formational input coupled to an output of the switch address, the first information input coupled to an output of the adder and an address input of the address memory unit microinstructions output address field kotoGen  ff i JlrlllllllJmлJ JLГшлJL W UlJl JLJLJlJL fL n n Or L.Pcholinsk 387/53 Compiled by Y.Laytsov Tehred I.Pspovnch Co Pod Circulation 673 VNIIPI USSR State Committee for inventions and discoveries 113033, Moscow, Raushsk nab. / d. A / 5 Production and printing company, Uzhgorod, st. Project, 4 3729 connected to the second information input of the address switch, the control input of which is connected to the output of the OR element, the first and second inputs 5 of which are connected to the outputs of the second and third elements, respectively, and the output of the logical conditions multiplexer and the second fO element is NOT - with the third input of the third element I. Compiled by Y.Laytsov Tehred I.Pspovnch Circulation 673 of the USSR Military Committee