SU1200294A1 - Processor - Google Patents

Abstract

1, a CPU containing an operation unit, an address generation unit, a pusch memory module and microinstruction register, a sync input, an information input, a read control output, a write control output, an output of the microinstruction code, and an output of the operating field of which are connected respectively to the processor sync input and information output of the microprogram memory block, first and second. the third, fourth, fifth, sixth and seventh inputs of the address shaping unit are connected to the initial setup input of the processor, the address output of the microprogram memory block, the transfer output of the operational block, synchronous input of the processor and the first information input of the processor, the first and second outputs of the address generation unit are connected respectively to the address input of the microprogram memory block and the second input - / IS .. / operating unit, the address and informational outputs of which are connected to the corresponding processor outputs, the third, fourth, fifth and sixth inputs of the operating unit are connected to the first, second and third information inputs and the synchronous input processor, respectively, in that In order to improve performance, it contains a decoder, two reversible counters and a switch, with the control input and the first, second and third information inputs and output of the switch connected i respectively output of the first guide yn .. ravl floor microinstruction register (L outputs of the first and second reversible counters informatsionnpch microinstruction register output and the seventh input operation unit, the clock. S processor and the output of the second control floor of the microinstructions register are connected respectively to the control and information inputs of the decoder, the first output of which is connected to the recording inputs of the first and CO 4 second reversible counters, and the second, third, fourth and fifth outputs - respectively to the inputs of the first and second reversible counters, the information inputs of which are connected to the second and third information inputs of the processor 2, respectively. The processor according to claim 1, in which the operational unit contains a microinstructor decoder, a decoder choice of register, eleven gztp elements And, f t

Description

groups of elements OR, group of registers, group of elements NOT, adder, five elements AND, element OR, address register and shift register, input and outputs of the microinstaller decoder are connected respectively to the first input of the block and the first inputs of the first, second, second, third, fourth And the fifth elements And, the inputs of the elements And the first, second, third, fourth, fifth, sixth, seventh and eighth groups, information input, parallel recording INPUT, shift input, serial information 1st input, output and sequential output shift The register is connected respectively to the outputs of the elements OR of the first group by the output of the first element AND, the output of the second element AND, the second input of the block, the information output of the block and the second input of the third element AND the second inputs of the first and second elements AND are connected to the sixth input of the block, the second input of the fourth element AND connected to the transfer output of the adder, the first and second inputs and output of the OR element are connected respectively to the outputs of the third and fourth elements AND and the transfer output of the block, information input output and synchronous The address register is connected respectively to the output of the elements OR of the first group, the output address of the block, the output of the fifth element AND, the second input of which is connected to the sixth input of the block, the second input and output of the elements AND the first group are connected respectively to the output of the elements NOT the group and the first input of the elements OR of the first group, BTOpoii input and output of elements AND of the second group are connected respectively to the outputs of the elements OR of the second group and the second inputs of the elements OR of the first group, the second input of the output elements AND the third 1 4 group are connected We are correspondingly with the outputs of elements AND of the ninth group and the third input of the elements OR of the first group, the second input and output of the elements AND of the fourth group are connected respectively to the output of the adder and the fourth input-elements OR of the first group, the first and second inputs and the output of the ETgi elements of the third group are connected respectively, with the outputs of the elements of the And the fifth and sixth groups and the first inputs of the OR elements of the second group, the elements of the Nine group and the adder, the first and second inputs and output of the OR elements of the fourth group are connected to But with the outputs of the elements of the seventh and eighth groups, the inputs of the elements NOT the group and the second inputs of the elements OR of the second group, the elements AND the ninth group and the adder, the input transfer of which is connected to the second input of the block, the 1 st inputs of the elements And the fifth group are connected to the combined third, fourth, and fifth inputs of the block, the second inputs of elements of the sixth and eighth groups are connected to the information output of the block, the input and outputs of the register select decoder are connected respectively to the seventh input of the block, the first inputs of the AND elements the tenth and eleventh groups, the second input of the elements of the tenth group are connected to the sixth input of the block, the synchronous inputs, the information inputs and outputs of the group registers are connected respectively to the outputs of the corresponding: elements of the tenth group, the outputs of the elements OR of the first group, the second inputs of the elements And the eleventh group, the second inputs and outputs of the elements OR of the fourth group are connected respectively to the outputs of the elements AND the eleventh group and the second inputs of the elements And the seventh group,.

The invention relates to computing and can be used in information, control, and computing systems. The purpose of the invention is to increase the processor prodigence. Fig, 1 shows a functional diagram of the processor; Fig.2 is a functional diagram of the operating unit; FIG. 3 is a functional block diagram of the formation of an address; FIG. 4 shows the microprogram execution algorithm. The processor contains the operation unit 1, information inputs 2-4 of the processor, address 5 and information 6 outputs of the processor, block 7 of forming the address, input 8 of the initial installation of the processor, block 9 of microprogramming memory, register 10 microcommands, controlling output 11 processors, decoder 12, reversible counters 13 and 14, switch 15 and synchronous input 16 of the processor, output 17 of transfer of block 1, input 18 of signs of block 7, output 19 of signs of block 7, input 20 of block 1, exit 21 of block 7, inputs 22- 24 blocks 7, input 25 of block 1, inputs 26 and 27 of the switch 15, input 28 of the decoder 12, the input 29 of the counter 13, the input 30 of the counter 14, the inputs 31 and 32 of the counter 13, the inputs 33 and 34 of the counter 14, the inputs 35 and 36 of the switch 15, the input 37 of the unit 1. The block 1 (figure 2) contains a decryption. 38 microinstructions, the decoder 39 choice of the register, the group of elements And 40, the group of registers 41, the group of elements And 42, ШШ 43, И 44, And 45, OR 46, And 47, And 48, OR 49, NOT 50, ШШ 51, И 52, and 53,; and 54, and 55, and 56, and or 57, adder 58.,. the element AND 59, the element AND 60, the element And 61, the address register 62, the shift register 63, the element AND 64, the element AND 65 and the element OR 66. The address formation BLOCK 7 ((FIG. 3) contains the decoder 67 microinstrums, groups of elements And 68j And 69, And 70, And 71, And 72 and ShZh 73, register 74, group of elements And 75, read decoder 76, write decoder 77, item 78, And 79 item, triggers 80 and 81 elements And 82 and 83 and element 84., Introduced conventions: UI -addressing microcommand; PC-register group 41 used as a program counter; P-register 62 of block 1; P - shift register 1 / 4з 41 group 63 of block I; Psy of block 1 whose number is indicated by counter 13; P is the register 41 of the group of block 1 whose number is indicated by counter 14; С413 4 and С414 3 are microoperations for loading counters 13 and 14 with information on inputs 3 and 4 of the processor; C413 +1 and C414 + 1 — Micro-operations of incrementing the content of reversible counters 13 and 14 by a unit; 4 tons — micro-reading of information from an external memory block, indicated at the output 11 of the processor; T CO is an entry in trigger 80 of block 7 of the value at output 17 of block 1; C1 T is the trigger trigger value 80 of block 7 to the input 20 of block 1. The processor works as follows. To bring the processor back to its original state, input 8 is given a zero initial boot signal. Thus, at the output 21 of the unit 7, a zero address is formed, which is the starting address of the boot firmware. At this address from block 9, the micro-command Ml is selected. Each microman; Yes it consists of two parts: address and executive. The address part is fed to the input 22 controlling the address of block 7, and the executive part of the information inputs of register 10. According to the synchronization signal in accordance with the specified type, the transition to register 74 of block 7 records the address of the next microcommand, and the executive part of the current microcommand is written to register 10. Thus, the sample of the micro-command is one step ahead of its execution, therefore, in the first micro-command cycle, the operation block 1, the decoder 12 and the switch 15 perform unspecified actions, the corresponding code AM formed in register 10 after turning on the processor. After the first sync signal at course 16, the Initial Set signal is transferred to one state and the address from the output of register 74 Through the elements of Group 75 and 75 is fed to the input of the microprogram block. Thus, the selection of subsequent addresses is determined by the register 74 of block 7.

The address part of the microcommand consists of two parts: the first part indicates the type of transition, the second address of the transition. Signals corresponding to the type of conversion to the second transition address. The signals corresponding to the type of transition, are fed to the input of the decoder 67, and the signals corresponding to the address of the transition, to the second inputs of groups of elements And 68-71. Depending on which output of the decoder 67 produces a single signal, the address of the next micro-command is determined either unconditionally at the transition address specified in the address part of the micro-command, either taking into account the signals at input 18 of block 7, or taking into account the state of triggers 80 and 81 gshi | unconditionally on the code formed at the input 2 of block 7,

The address code of the next micro-command formed by one of the listed methods is fed through the groups of elements OR 73 to the information input of the register 74 and the back of the clock signal input 16 is recorded in the register 74.

The executive part of the micro-command consists of seven fields. The code supplied from the first output of register 10 to input 23 of block 7 determines the function of read decoder 76, depending on which at output 19 of block 7, either the contents of flip-flops 80 and 81, or the values of logical 0 or logical 1 are generated. the second output of register 10 to input 24 of block 7 determines the function of write decoder 77, depending on which the trailing edge of the sync signal at input 16 makes either write to one of the flip-flops 80 or 81 values present at input 18 of block 7, or the trigger values remain without and Menen.

The operation of block 7 in this case is as follows. If an entry is made to any data trigger on the input 18 of the block 7 TO, a single signal formed at one of the outputs of the decoder 77 opens the AND 7B or 79 element. The incoming one to. the input 16 of the sync pulse completes the recording of the signal value at the input 18 of block 7,

When a state of any trigger is triggered at output 19 of block 7, a single signal at the corresponding output of the decoder 76 is closed i

the element AND 82 or 83 and the content, respectively, 80 or 81 through the elements AND 82 and OR 84 or AND 83 and OR 84 enters output 19 of block 7. When performing many operations

the processor accesses an external memory block (not shown). When performing information recording operations in an external memory block, a control signal is set at control output 11,

5 corresponding to the recording mode.

The address to which the recording is made, and the data are generated at the outputs 5 and 6 of the processor, respectively. When reading information from the external memory block at the control output 11, a read signal is set, and the data from the external memory output is fed to inputs 2-4 of the processor.

5 The code received from the output of the register 10 to the input 28 of the block 12 defines one of the functions of the decoder 12, as a result of which the operations are performed: loading of reversible counters

0 53 and 14 data, formed respectively at inputs 4 and 3 of the processpai +1 in counter 13; -1 from counter 13; +1 in counter 14; -1 from counter 14.

The code coming from the output of register 10 to input 26 of block 15 determines the function of the decoder 85 of block 15,. which is to select the channel number to be connected to the output of the switch 15, the unit value at one of the outputs of the decoder 85 opens one of the groups of elements 86 - 88, and information, respectively, from one of the inputs 27, 35 and 36 of the block 15 enters through the corresponding group of elements AND and through the group of elements OR 89 at the input 37 of block 1.

Information recorded in reversible counters and coming from

 the output of register 10 to input 27 of block 15, in its own sense, is the number of one of the registers 41 of the group of block 1. Thus, the code coming from the output of switch 15 to the input

5 37 block 1, defines the function of the decoder 39 of block 1, which consists in choosing one of the group registers 41 as one of the operand 12 D000 The second operand and the type of action performed on the operands is determined by the code from the output of the register 10 on input 25 of block 1. 6 as the second operand can be selected either the register 63 of block 1, or the data formed at the inputs of 2-4 processors. On operations, block 1 performs arithmetic logic and shift operations. Arithmetic logic operations in block 1 are performed on two operands that come from the outputs of the group of elements OR 46 and from the outputs of the group of elements or 49. At the output of the group of elements OR 46, data is formed either from inputs 2–4 or from processor 6 output depending on which of the groups of elements AND 44 or 45 is open with a single signal after the output of the decoder 38. At the output of the group of elements OR 49, data is generated either from the outputs of the group of elements OR 43, or from the outputs 6 of the processor, also depending. Most importantly, the group of elements AND 47 or 48 is opened with a single signal coming from the output of the decoder 38. The selected operands arrive at the inputs of the groups of elements NOT 50, OR 51 and AND 52 and adder 58, the output of which results respectively logical operations NOT, OR, AND, or the sum of the operands. When the adder 58 overflows at its transfer output, a single transfer signal is generated, which enters the input element. And 65, and in the presence of a single signal at the second input of the element And 65, coming from the output of the decoder 38, the transfer signal through the elements And 65 and SHSh 66 enters the output 17 of block 1. Depending on which group of elements And 53 - 56 is opened with a single signal from the output of the decoder 38, the result of the corresponding operation is NOT, OR, AND, the sum goes through the corresponding group of elements AND and OR 57 to the inputs of registers 62 and 63 and to the inputs of registers 41 of the group. The result of the performed operation, depending on the presence of a single signal at the inputs of the And 59-61 elements, is recorded by the synchronization signal at input 16 into registers 62 and 63 and register 63 with a shift. 4, at the same time, from the shift output, the signal enters the input of the AND-64 element and, if there is a single signal at the second input of the element, AND 64 enters through the AND 64 and OR 66 elements at the output 17 of block I. Moreover, the synchronization signal results in the operation result one of the registers 4 of the grzztp, depending on which of the elements of group 40 and at the first input contains a single signal coming from the output of the decoder 39, Consider the algorithm for performing the operation of adding two registers (figure 4) in case of an increase in the number of registers about appointment. In the address part of the microcommand Ml, an unconditional transition to the microcommand M2 is formed, and the execution part is indicated by the operation of zeroing one of the registers 41 of the group, which is selected as the program counter (denoted by PC). It is assumed that if a code is generated at any output of the register 10, which indicates the absence of active actions of one or another block, then this output will not be mentioned when clarifying the principle of operation. Thus, in the micro-command Ml only block I takes active actions. In the address part of the micro-command M2, an unconditional transition to the micro-command of the MOH is indicated, and in the executive part - transferring data from the PC register to the register 62 of block 1, as a result zero external memory address. In the micro-command MZ at the output I1 of the processor, a read signal from the external memory is indicated, as a result of which the contents of the zero address of the external memory are fed to inputs 2-4 of the processor, in particular, the value at input 2 of the processor is fed to input 2 of block 7, To input 28 of the decoder I2 is supplied with a code indicating that the reversible counters 13 and 14 are loaded with information present at inputs 4 and 3 of the processor. According to the synchronization signal, the information is recorded in the counters 13 and 14. In its sense, this information is the register number 41 of the group 1 of the block 1, on which the command action must be performed. 9120 In the address part of the micro-command MZ, the transition to the micro-command M4 is specified, in the address part of which the transition is indicated by the code present at input 2 of block 7. As a result, elements of group 72 and code from input 2 through elements I are opened from the output of decoder 67 72 groups and OR 73 groups arrive at the input of register 74 and the synchronization signal records the address of the next microcommand M5, which is the starting address of the microprogram implementing the operation of adding two registers. The command M4 indicates an increment operation per unit content of the software counter PC. In the address part of the micro-command M5, an unconditional transition to the micro-command MB is specified, and in the execution part, the operation of transferring the contents of one of the group registers 41, the number of which is recorded in counter 13, to the register 63 of block 1. To do this, the input 26 of switch 15 is given a code , providing signaling the passage of signals from input 35 through elements AND groups and elements of group III of block 15 to input 37 of decoder 39 of block 1. 47 groups . When performing the operation of transferring one of the registers 41 groups to the register 63, at the outputs of the decoder 38, zero signals are formed, which go to the inputs of the elements of AND 44 groups, And 45 groups, And 48 groups, And 53 groups, And 54 groups And And 56 groups, and single signals, entering the 1 INPUTS of the elements of AND 47 groups and AND 56 groups. As a result, the operation is performed by adding the contents of the register 41 of the group to the input of the dryer through the elements AND 47 of the group and OR 49 of the group, with a zero value formed at the second input of the adder from the output of the elements OR 46 of the group. Next, the result of summing through the elements AND 56 of the group and OR 57 of the group enters the inputs of register 63. According to the synchronization signal, if there is a single signal at the input of element AND 60, the output of the decoder 4 records the result in register 63. In the address part of the microcommand MB, a transition is specified . M2, and in the executive part, the addition of the contents of the register 41 of the group of block 1, the number of which is indicated in the counter 14, and the contents of the register 63 of block 1. The result is written into the register 41 of the group of block 1, starting with the microcommand M2, the processor actions are repeated. Thus, adding two registers takes up five micro-instructions. The addition of two external memory cells will require a larger number of micro-instructions, since it is necessary to perform micro-operations for calculating the addresses of these cells and reading data from the external memory. Consider the microprogram algorithm for adding two pairs of registers (Fig. 4) in the case of processing operands of a higher size than the processor's width. The actions of micro-commands M2 and MH are described earlier. In the address part of the micro-command M4, a transition is made according to the code at the input 2 of block 7, i.e. to the M7 microhando, in the address part of which the transition to the M8 microcommand is indicated. In the executive part of the microcommand M7, the register register 41 of the group indicated by the counter 13 is indicated in register 63 of the block 1. The address part of the microcommand M8 indicates an unconditional transition to the microcommand M9, from which the transition to Ml O and further to M2 is completed, assuming The command for adding pairs of registries to the executive part of the micro-command M8 indicates the addition of the contents of the go register 63 of block 1 and the register 41 of the group, whose number is specified in the counter 14. The transfer formed by the output 17 of block 1 when added is fed to input 1B of block 7. At input 24 b eye 7 from the output register 10 receives a code indicating a value for recording on 1B input to flip-flop 80. The input 28 is supplied to the code decoder 12, indicating an increase in the content down counter 13 by one. The synchronization signal completes all of the listed actions, and the result of the addition is recorded in a register, 41 groups, the number of which is indicated in counter 14. In the M9 microcommand, the contents of group register 41, the number of which is indicated in counter 1 3, are sent to register 63 of block I. the input 28 of the decoder 12 indicates the operation of increasing the content of the counter 14 by one. In the Ml O microcommand, a complex

254

ig.1 942; register register 63 of block 1 with the contents of register group 41, the number of which is indicated in counter 14, To input 23 of block 7, a code is supplied to output the contents of register of trigger 80 to output 19 of block 7, which is fed to input 20 of the adder transfer 58 block i, i.e. addition is performed taking into account the transfer formed by adding the lower parts of the operands.

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Claims (2)

(57) 1. A PROCESSOR comprising an operation unit, an address generation unit, a firmware memory block and a micro-register, a sync input, an information input, a read control output, a write control output, a micro instruction instruction output and an operating field output which are connected respectively to a processor sync input, information the output of the microprogram memory block, ^ the inputs of the ca block, the first block and the first and second formation of the address input to the processor operating-control output, the third, fourth, fifth, sixth and seventh my inputs of the address generation unit are connected respectively to the input of the initial installation of the processor, the address output of the microprogram memory block, the transfer output of the operating unit, the clock input of the processor and the first information input of the processor, the first and second outputs of the address formation unit are connected respectively to the address input of the microprogram memory and the second the input of the operating unit, the address and information outputs of which are connected to the corresponding outputs of the processor, the third, fourth, fifth and w The clean inputs of the operating unit are connected respectively to the first, second and third information inputs and the sync input of the processor, characterized in that, in order to increase productivity, it contains a decoder, two reversible counters and a switch, the control input and the first, second and third information inputs and output of the switch connected _to a first respectively a yield yn · Sravlyayuschego field microinstruction register outputs of the first and second down counters, data output register and microinstruction sed the seventh input of the operating unit, sync input. g of the processor and the output of the second control field of the micro-command register are connected respectively to the control and information inputs of the decoder, the first output of which is connected to the recording inputs of the first and second reversible counters, and the second, third, fourth and fifth outputs, respectively, to the addition and subtraction inputs of the first and second reversible counters, the information inputs of which are connected respectively to the second and third information inputs of the processor. 2. The processor according to π. 1, with the fact that the operating unit contains a micro-instruction decoder, a register selection decoder, eleven groups of AND elements, five> OR element groups, register group, NOT element group, adder, five AND elements, OR element, address register and shift register, microinstructor decoder inputs and outputs are connected respectively to the first block input and the first inputs of the first, second, third, fourth and fifth elements And, the first inputs of the elements And the first, second, third, fourth, fifth, sixth, seventh and eighth groups, information input, parallel recording input, shift input, serial information input, output and serial output. of the second register are connected respectively with the outputs of the OR elements of the first group, the output of the first AND element, the output of the second AND element, the second input of the block, the information output of the block and the second input of the third AND element, the second inputs of the first and second elements AND are connected with the sixth input of the block, the second input the fourth AND element is connected to the adder transfer output, the first and second inputs and the output of the OR element are connected respectively to the outputs of the third and fourth AND elements and the block transfer output, information input, output, and sync the address register input is connected respectively to the output of the OR elements of the first group, the output of the block address, the output of the fifth AND element, the second input of which is connected to the sixth input of the block, the second input and output of the AND elements of the first group are connected respectively to the output of NOT group elements and the first input of OR elements the first group, the second input and output of the AND elements of the second group are connected respectively to the outputs of the OR elements of the second group and the second inputs of the OR elements of the first group, the second input and output of the elements AND of the third group are connected enes respectively to the outputs of the AND-ninth groups and the third OR input elements of the first group, a second input and output elements and the fourth group are respectively connected to output sum < ". Mathor and the fourth input of the OR elements of the first group, the first and second inputs and the output of the IDN elements of the third group are connected respectively to the outputs of the AND elements of the fifth and sixth groups and the first inputs of the OR elements of the second group, the AND elements of the ninth group and the adder, the first and second inputs and the output of the OR elements of the fourth group is connected respectively to the outputs of the AND elements of the seventh and eighth groups, the inputs of the NOT elements of the group and the second inputs of the elements of the OR of the second group, the elements of the AND ninth group and the adder, the input-transfer of which connected to the second input of the block, the second inputs of the elements And the fifth group are connected to the combined third, fourth and fifth inputs of the block, the second inputs of the elements And the sixth and eighth groups are connected to the information output of the block, the input and outputs of the decoder of the register selection are connected respectively to the seventh input of the block, the first inputs of the elements of the tenth and eleventh groups, the second input of the elements of the tenth group is connected to the sixth block input, clock inputs, information inputs and outputs of the group registers are connected respectively to the outputs and related; . elements AND of the tenth group, the outputs of the elements OR of the first group, the second inputs of the elements AND of the eleventh group, the second inputs and outputs of the elements of the OR of the fourth group are connected respectively to the outputs of the elements AND of the eleventh group and the second inputs of the elements AND the seventh group.