JPH03204028A - Central processing unit - Google Patents

Abstract

PURPOSE:To attain the effective use of the recording capacity by forming the next address based on the branching destination address when the arithmetic result of an arithmetic circuit which shows the satisfaction of conditions is applied to an addressing circuit at the time of execution of a conditional branching instruction. CONSTITUTION:An S5 selector 15 is provided into an addressing circuit. The selector 15 receives an SL field and value '1' from a program ROM 1 and a control logic part 3 respectively and works based on the control signal given from the part 3. In executing a condition checking/branching instruction, the SL field is selected as long as the conditions are satisfied. Then the SL field value is added to the present value of the address of a program ROM 1 via an adder 4. Thus the next address is formed to the ROM 1. Otherwise the selector 15 selects the value '1' received from the part 3 and actuates the adder 4 as a program counter. In such a constitution, the number of program steps related to the branching processing in particular can be extremely decreased.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a central processing unit, and in particular to a central processing unit for small school computers.
This invention relates to branch processing technology in U (central processing unit N).

[Prior art and its problems] In general, a conditional branch instruction performs an operation, checks whether a condition is satisfied based on the result of the operation, and moves to the branch destination program address when the condition is established. To achieve this, in conventional central processing units, it is necessary to separately execute two instructions: an instruction to perform an operation and an instruction to perform a conditional branch from the operation result, and each instruction word needed to be stored separately in program memory.

A conventional example will be explained with reference to FIGS. 4 to 9. In the circuit block diagram of FIG. 4, an instruction word output from a program ROMI that stores a program consists of an operation code indicated by OP and operand fields indicated by FU, FL, SU, and SL. FU and FL indicate the upper and lower parts of the first operand, respectively, and SU and SL indicate the upper and lower parts of the second operand. The operation contained in the instruction word is decoded by the decoder 2 and sent to each circuit (
5, 8 to lO, 13, 14, etc.) are controlled.

Normally, the circuit for addressing the program ROMI inputs 1 from the control logic unit 3 to the current value of the program address.
an adder 4 as a program counter that adds up , a selector 5 of S4 that selects the address in addition to the output of the adder 4 when branching to the address indicated by the operands FU, SU, FL, and SL; The L3 latch 6 latches the output of the L3 latch 6.

The addressing circuit for RAM 7 as a calculation memory uses fields FU and SU from the program ROMI.
, and an S2 selector that selects fields FU and SU from the program ROM 1. At the timing of the first operand, selectors 8.9 select FU and FL, respectively, to address RAM 7, and at the timing of the second operand, selectors 8.9 select SU and SL, respectively, to address RAM 7. .

The arithmetic circuit for RAM 7 is Ll data latch 11, L
It consists of a 2-day clutch, a selector 13 and an ALU 14. The data of the first operand output from the RAM 7 is latched by the latch 11, and becomes the A input of the ALU 14, and the RA
The second operand data output from M7 is latch 1.
2 and becomes the B input of the ALU 14. When an instruction that sets the second operand as an immediate value is output from the program ROMI, the lower SL of the second operand is selected by the selector 13 instead of the latch 12 output through the gate IO, and the ALU 14's B It becomes input. The calculation result data of the ALU 14 is returned to the RAM 7. Further, the status of the Z flag in the calculation result of the ALU 14 is inputted to the control logic unit 3 together with the decoding result of the operation decoder 2, and is used for branch checking and the like.

FIG. 7 shows the operation of the circuit of FIG. 4 in response to the instruction (X+Y+X). The RAM address or first operands FU and FL are determined, and the RAM address Y is determined by the second operands SU and SL. At the timing of TI, the RAM 7 is designated by the address Y indicated by the second operand, and its T-ta is latched into the latch 12.

At timing T2, the RAM 7 is designated by the address X indicated by the first operand, and the data X is latched into the latch 11. At the next T3 timing, data X and Y are
The LU 14 performs the addition, writes the addition result to the X address of the RAM 7, and ends the execution of the instruction.

FIG. 8 shows the operation for the instruction (x+3→X). In this case, at the timing of TI, the lower 5L (=3) of the second operand is transferred to the selector 1 via the gate IO.
3 is selected. At timing T2, the address X of the RAM 7 indicated by the il operand is specified, and the data X is set in the latch 11. At T3, the ALU 14 executes the addition, and the result is written to address X in the RAM 7.

FIG. 9 shows that this instruction for instruction (X/4) compares the first operand X and the immediate second operand 4, and
This is to check whether the condition 4=0 holds true. The instruction operates in the same way as the instruction shown in FIG. 8 up to the timing T2, and at the timing T3, the immediate value is subtracted from the data X in the ALU 14, and the states of the zero flag Z and carry flag CO are determined according to the result of the subtraction.

FIG. 5 shows a flow including a branch instruction, and FIG. 6 shows a program R of the above-mentioned conventional example to realize this flow.
Shows the contents of the program stored in OMI. In the conventional case, as shown in FIG. 6, a jump is made to the address (n+4) of the RAM 7 called JMP (n+4), which is the next address of the condition check instruction word (X/4) to obtain the conditional flag 78 in the conditional branch. It is necessary to store the jump instruction word.

As described above, in the prior art, two instruction words are required for each conditional branch processing, which has the problem of increasing the capacity of the program ROM.

[Object of the Invention] Therefore, an object of the present invention is to provide a central processing bag δ that reduces the number of program steps for conditional branch instructions.
The goal is to provide the following.

[Structure and operation of the invention] In order to achieve the above object, according to the present invention, there is provided a program memory means for storing a program, an addressing circuit means for addressing the program memory means, and a program memory means for addressing the program by the addressing circuit means. instruction decoding circuit means for decoding the opcodes and operands constituting the instruction word read from the storage location of the program memory; operating according to the decoding result of the instruction decoding circuit means to execute the operation of the operands; In the central processing unit, the program memory means stores an operation code, a first operand, and a second operand which is an immediate value of the first operand as an instruction word of a conditional branch instruction. It has means for storing a jump value indicating a branch destination in the field that remains when the two operands are made into immediate values,
” 2. The addressing circuit means determines the next address for the program memory means according to the branch destination address indicated by the jump value when the arithmetic circuit means receives an operation result indicating that the condition is met during execution of the conditional branch instruction. A means is provided for forming.

According to this configuration, the instruction word for one condition check and the jump instruction word are stored separately in the program memory means, and the same processing as the conditional branch processing that has been executed can be performed using the conditional check instruction and the jump instruction word. This can be achieved by executing the l instruction, J, which is a composite of the instructions. Therefore, the storage capacity of the program storage means can be used efficiently.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit block diagram of a central processing unit circuit according to an embodiment. Note that the same elements as those in FIG. 4 of the conventional example are given the same numbers, and their explanations will be omitted. The first difference from FIG. 4 is the addressing circuit that generates an address for the program ROMI. That is, a 35 selector 15 is added to the addressing circuit.

This selector 15 receives the SL field from the program ROMI and the value "l" from the control logic section 3, operates according to the M control signal from the control logic section 3, and when executing the condition check/branch instruction described later, holds, then S
The L field is selected, and the adder 4 adds the SL field value (indicating the displacement value of the branch destination address) to the current value of the program ROM address.
Allow the next address for the program ROMI to be formed. In other cases, the selector 15 selects the value "1" from the control logic section 3 and causes the adder 4 to operate as a program counter.

FIG. 2 shows a program stored in the program ROMI of the embodiment for the flow shown in FIG. 5 described above.
The instruction +(x/4+3) at address n is an instruction that combines a conditional check and a branch instruction. It can be seen that the number of program steps is reduced by one compared to the conventional example shown in FIG. The general format of this compound instruction is shown in Figure 3 (X
/n+m).

Here, X is the first operand, and its upper and lower parts are defined by the FU field and FL field of the instruction word. n is defined by the SL field, and 6m is defined by the SU field. The meaning of the instruction (X/n+m) is to check whether the value obtained by subtracting the immediate value n of the second operand from the data at the RAM7 address indicated by the first operand X is zero, and if it is zero, jump to the current address value of ROMI. Add the value m to obtain the ROMI branch address.

That is what it is. In the case of FIG. 2, the branch destination address is the address (n+3) that stores the instruction word (V3+3).

Taking this compound instruction (x / 4 + 3) as an example,
To explain the operation of the circuit shown in FIG. 1, at timing T1, the second operand SL field immediate value 4 is set to
At the timing of the 0th order T2 input to the B input of the ALU 14 through the selector 13, the first operands FU and F
RAM 7 is addressed with the value X in the L field, and the data value
entered into the input. At the next T3 timing (x-4)
The calculation is executed, and the state of the zero flag Z is determined as the result of the calculation.

On the other hand, 55 selector 1 of the ROMI addressing circuit
5 has the jump value °°3'' in the SU field added to one of its inputs.Furthermore, the control logic unit 3 receives the zero flag Z signal obtained at the timing T3.This zero flag A control signal (not shown) corresponding to Z is applied from the control logic section 3 to the selector 15. As a result, the selector 15 sets the zero flag Z=1 (X-40).
Sometimes, select the jump value "3" of the SU field,
When the zero flag Z=O (X-4≠0), the input data “l” is sent from the control logic unit 3! Choose. Therefore, depending on whether the condition is satisfied by the zero flag Z value, the adder 4 performs address operation on (n+1) or (n+3), and in the next cycle, the address (n+1) is either V1+1 or address (n+3). ) instruction v3+3 will be executed.

As shown in the column of S3C (CX (n→X)), the SU field is not used in an immediate instruction whose second operand is an immediate value n. In the embodiment, this SU field is used as a field for the jump value m in a conditional branch instruction which is a compound instruction, so there is no need to increase the number of bits of the instruction word compared to the conventional one.

[Effects of the Invention] As described in detail above, in the present invention, the program memory means stores an operation code, a first operand for condition checking, and this first operand as a composite instruction word of a conditional branch instruction. With the second operand being the immediate value of
Means for storing a jump value for a branch destination address in a field remaining when the second operand is an immediate value is provided, and the addressing circuit means for the program memory means is provided with a jump value for a branch destination address when the second operand is an immediate value. Since the means for forming the next address for the program memory means based on the branch destination address indicated by the jump value given the calculation result indicating that the condition is satisfied is provided, the storage capacity of the program memory means can be used efficiently. The number of program steps related to branch processing can be significantly reduced.

[Brief explanation of drawings]

1 is a block diagram of the central processing unit according to the embodiment, FIG. 2 is a diagram showing an example of a program stored in the program ROM of the embodiment of FIG. 1, and FIG. 3 is a block diagram of the central processing unit of the embodiment of FIG. 1. FIG. 4 is a block diagram of a central processing unit according to a conventional example; FIG. 5 is a diagram showing an example of a flow including branch processing; FIG. A diagram showing a program stored in the program ROM of FIG. 4 corresponding to the flow of FIG. 5, FIG. 7 is a diagram used to explain the operation of FIG. 8, and FIG. be. 1...Program ROM, 2...Operation decoder, 7...RAM, 4...ALU, 4...Adder, 5. ·····selector. Patent Applicant Casio Computer Co., Ltd. Address Contents X/4+3 n+1 1 +1 n+2 2 +2 n+3 V3 +3 Figure Figure 5 Figure Address Contents Input ALU output x+Y x+Y X+3→X I 2 3 RAM address BUS content S[=3 ALU output X+3 4 L4 carreg or Zero generation operand FU, [X SU Aki SL n=4 Fig.

Claims (1)

[Scope of Claims] Program memory means for storing a program; addressing circuit means for addressing the program memory means; and instruction words read from a storage location of the program memory addressed by the addressing circuit means. A central processing unit comprising: instruction decoding circuit means for decoding an opcode among the constituent opcodes and operands; and arithmetic circuit means operating according to the decoding result of the instruction decoding circuit means to execute the operation of the operand, The program memory means stores, as an instruction word of a conditional branch instruction, an operation code, a first operand, a second operand which is an immediate value of the first operand, and a branch destination in a field that remains when the second operand is set as an immediate value. The addressing circuit means stores a jump value indicated by the jump value, and the addressing circuit means stores a jump value indicated by the jump value when the arithmetic circuit means receives an operation result indicating that the condition is met during execution of the conditional branch instruction. A central processing unit characterized in that it comprises means for forming a next address for said program memory means by a previous address.