JPH01177647A - Information processor - Google Patents

Abstract

PURPOSE:To easily investigate the number of times of appearing of a certain command, etc., by holding the execution states of a certain command with a performance measuring mode in designated number of clocks, and comparing also times when a program flows in the case of the performance measuring mode and the case of the mode except for the performance measuring mode. CONSTITUTION:In the middle of executing the program, the command code of the command transferred from a command prefetching circuit 5 through a signal line 10 to an arithmetic processing circuit 4 is sent through a signal line 8 to a comparator 11, and the code is compared with the command code of a command code register 2 sent through a signal line 7. At the time of a coincidence, a coincidence signal is outputted from the comparator 11, and an arithmetic processing suppressing signal is outputted from a suppressing signal generating circuit 12 only in a designated number (n) of clocks. The arithmetic processing suppressing signal is outputted to the arithmetic processing circuit 4 and command prefetching circuit 5. Thus, a processing time T0 of the program can be known, and since a processing time T1 when the program is made to flow in a condition except the performance measuring mode is known beforehand, the number of times of appearing of the command can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information processing device having an arithmetic processing means.

[Conventional technology]

In order to speed up a program, it is necessary to know how much influence a certain instruction has on the program. Traditionally, it has been possible to analyze the program to find out how much influence a given instruction has on a program, for example, by checking the number of times the instruction appears, or when an instruction is executed, This has been done by providing a special circuit to output the signal and counting the signal externally.

[Problem that the invention seeks to solve]

Determining the number of instructions by analyzing a program as described above may be very difficult depending on the program being analyzed, and providing a special circuit to output signals to the outside requires a large amount of hardware. There is a drawback that.

[Means for solving problems]

The information processing apparatus of the present invention includes an instruction code holding means for holding an instruction code, a mode instruction means for indicating that the information processing apparatus is in the performance measurement mode, and a mode instruction means for indicating that the information processing apparatus is in the performance measurement mode. If instructed,
When the instruction instructed by the instruction code holding means is processed by the arithmetic processing means of the information processing device, the information processing apparatus includes an arithmetic processing inhibiting means for holding the arithmetic processing means in the same state for a specified number of clocks.

[For production]

Assuming that the number of occurrences of an instruction held in the instruction code holding means is m, the clock cycle time is Ct, and the specified number of clocks is n, the total time for the arithmetic processing means to maintain the same state is Ct −n −m It is.

On the other hand, the time T1 during which the program was run in a state other than the performance measurement mode is known in advance, and when the time T0 during which the program was run in the performance measurement mode is measured, T6 = T+ +ct - nm holds true.

Therefore, the number of occurrences m of the instruction is m-(T,) TI)/(Ct-n)-(1)
becomes. :,.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of an information processing apparatus of the present invention.

Mode register 1 is set to "1" when the information processing device is in performance measurement mode. The instruction code register 2 holds the instruction code of an instruction whose arithmetic processing state is to be maintained for a specified number of clock cycles n. The instruction prefetch circuit 5 prefetches instructions and transfers calculation data and control information to the arithmetic processing circuit 4. The arithmetic processing suppression circuit 3 includes a comparison circuit 11, a suppress signal generation circuit 12, and an ant gate 1.
The comparison circuit 11 compares the instruction code held in the instruction code register 2 and the instruction code sent from the instruction prefetch circuit 5, in which the performance measurement mode is instructed by the mode register 1. , if they are the same, outputs an arithmetic processing inhibit signal that causes the registers in the arithmetic processing circuit 4 and the instruction prefetching circuit 5 to be in the same state for a specified number of clocks n.

Next, the operation of this embodiment will be explained.

Set "1" to mode register 1 to put the information processing device into performance measurement mode, and set instruction code register 2 to "1".
Set the instruction code of the instruction for which you want to check the number of occurrences, and run the program. At this time, a timer measures the processing time of the program. During program execution, the instruction code of the instruction transferred from the instruction prefetch circuit 5 to the arithmetic processing circuit 4 via the signal line 10 is sent to the comparator circuit 11 via the signal line 8, and the instruction code is sent via the signal line 7 to the instruction code register 2. is compared with the instruction code of If they match, the comparison circuit 11 outputs a match signal, and the suppress signal generation circuit 12 outputs an arithmetic processing suppression signal for the specified number of clocks n. Since the output signal line 6 of the mode register 1 is "1", this arithmetic processing inhibit signal is sent to the AND gate 13.
The signal passes through the signal line 9 and is output to the arithmetic processing circuit 4 and the instruction prefetch circuit 5. As a result, the arithmetic processing circuit 4 and the instruction light receiving circuit 5 inhibit all updating of registers and the like within the arithmetic processing circuit 4. This means that the instruction in the instruction code set in the instruction code register 2 is sent to the instruction prefetch circuit 5.
The process is repeated every time the data is transferred from the computer to the arithmetic processing circuit 4. When the processing of the entire program is completed, the timer is stopped and the processing time To of the program is determined. Since the processing time T1 when the program is run without performance measurement mode is known in advance, the number of occurrences m of the instruction set in the instruction code register 2 is expressed as T6.
It is determined by substituting the values of TI, Ct, and n.

〔Effect of the invention〕

As explained above, the present invention maintains the execution state of an instruction in performance measurement mode for a specified number of clocks, and also compares the program flow time in performance measurement mode and in non-performance measurement mode. This has the effect of allowing you to check the number of occurrences of a certain instruction without analyzing the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of an embodiment of an information processing apparatus of the present invention. DESCRIPTION OF SYMBOLS 1...Mode register, 2...Instruction code register, 3...Arithmetic processing suppression circuit, 4...Arithmetic processing circuit, 5...Instruction prefetch circuit, 6-10...Signal line, 11 ... Comparison circuit, 12 ... Suppress signal generation circuit, 13 ... AND gate.

Claims (1)

[Claims] In an information processing apparatus having an arithmetic processing means, an instruction code holding means for holding an instruction code, a mode instruction means for instructing that the information processing apparatus is in a performance measurement mode,
When the performance measurement mode is instructed by the mode instruction means, when the instruction specified by the instruction code holding means is processed by the arithmetic processing means of the information processing device, the operation is performed for a specified number of clocks. An information processing device comprising: arithmetic processing inhibiting means for maintaining the arithmetic processing means in the same state.