SU1670688A1 - Device for checking programs - Google Patents

Abstract

The invention relates to computing and can be used in the means of monitoring the execution time of programs. The aim of the invention is to increase the depth of monitoring the progress of program execution by taking into account the execution time of cyclic program sections with a fixed number of loop repetitions. The device contains a block of 1 memory, a block of 2 registers, a group of 3 counters, a group of 4 flip-flops, a register of 5 addresses, a counter of 6 addresses, a multiplexer 7, a decoder 8, the first 9 and the second 10 groups of elements AND, a group of 11 elements OR, the first 12 and the second 13 elements are And, the second 14 and the first 15 elements are OR. The device allows you to speed up the debugging of programs by promptly making corrections to the program. 2 Il.

Description

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The invention relates to computing and can be used in the means of controlling the time of program execution.

A device for monitoring and debugging a program is known, which contains a memory block, a register, a counter, AND and OR elements.

A similar device is also known.

A common drawback of these devices is the low depth of control.

A device with a programmable electrical unit and a control unit is known that contains an address counter, an AND element, an OR element. the output of which is the output of the device error signal, and the first clock input of the device is connected to the counting input of the address counter.

The disadvantage of this device is the low depth of monitoring the progress of the programs due to the fact that it is impossible to determine a fixed portion of the program in which the algorithm for its execution is violated.

The purpose of the invention is to increase the depth of monitoring the progress of programs by taking into account the time of the execution of cyclic program sections with a fixed number of repetitions of cycles.

Figure 1 shows the structural-functional diagram of the device; figure 2 - timing diagram of the device.

The device contains a block of 1 memory, a block of 2 registers, a group of 3 counters, a group of 4 flip-flops, a register of 5 addresses, a counter of 6 addresses, a multiplexer 7, a decoder 8, the first 9 and the second 10 groups of elements And, a group of 11 elements OR, the first 12 and the second 13 elements are AND, the second 14 and the first 15 elements are OR, the input 16 of the address, the second clock input 17, the third clock input 18, the mode setting input 19, the first clock input 20, setup input 21, the input 22 of the program variable code, input 23 setting the start code, entry 24 of entry, exit 25 of address, information exit 26 and exit 27 of signal ala errors.

The device operates in two modes: in the initial installation mode and the program progress monitoring mode.

Before the operation of the device, all the memory elements are set to the initial (zero) state (the installation circuits to the initial one are not shown in the diagram).

Initial installation mode.

The input values of the device 23 are supplied to the codes of the initial installation of a group of 3 meters. According to the signal fed to the input 21, the values of these codes are written into a block of 2 registers and a group of 3 counters. This is necessary in order to record such an installation in each of the counters so that the remaining capacity of the counter determines the possible number of occurrences of the corresponding arbitrary variable during the execution of the program.

The need to store the initial installation codes in block 2 of registers is due to the following. During the execution

0 programs, any of the variables can characterize the processing by the program of the inner loop, in which it must be processed a fixed number of times.

5At this, this inner loop can be used an arbitrary number of times. To increase the diagnostics depth — the definition of the loop test and the moment it arrives, it is necessary to reset the corresponding counter at the time of the end of the cycle, i.e., write the initial installation code into it.

The signal applied to the input 19, the address code from counter 6 through multiplexer 7

5 is fed to the input of the address of memory block 1.

For each of the generated addresses, using the input 22 of the device and the input 24 of the record, information is recorded in block 1 of the memory. According to the address

0 is recorded and the variable code. If the variable is encountered in the loop for the last time, the label field of the variable code is complemented by one, in all other cases it is zero,

5After filling the memory block 1 on

the input 19 of the device supplies a control signal providing the address from the output of the register 5 of the address through the multiplexer 7 to the input of the address of the block 1 of the memory. The device is ready to work in the mode of monitoring the progress of the program.

The mode of monitoring the progress of the program.

With the arrival of the first clock pulse

5, at the device input 17, the address of the program variable currently being processed is input from register 16 to register 5. This address is fed through multiplexer 7 to the input address of memory block 1,

0 the information output of which forms the variable code, and the output of the label field is a zero signal. As a result, a single signal is generated at the output of the OR 14 element, whereby a single signal is also generated at the output of the And 12 element, as a result of which a single signal is also generated at the output of the 12 element, which enters the input group 9 of the And elements and prepares it for operation. In addition, the variable code from the block output

It goes to the information input of the decoder. With the arrival at the input 18 of the device of a clock pulse, at the output of the decoder 8, corresponding to the variable code, a single signal is generated, which through the open element AND of the group

9 elements And goes to the corresponding counting input of the counter of the group of 3 meters.

Thus, the fact of processing a program variable is fixed. The device operates similarly until a single signal appears at one of the cycles at the output of the t-th bit of memory 1 (indicating that the number of occurrences of the variable has reached its maximum value).

As a result, a single signal is formed at the output of element AND 13. This signal ensures the passage of information from the corresponding output of the decoder through a group of 9 elements AND and a group

I1 elements OR to the input of the control of a group of 3 meters. This leads to the fact that the initial setup code is written to the corresponding counter of group 3 from block 2 of registers.

Further, the operation of the device is similar to that described.

If a number more than the allowed number is written to one of the counters of group 3 (as a result of jamming), then the overflow signal of this counter translates to the one state its corresponding trigger group of 4 flip-flops. In addition, the overflow signal through the OR element 15 is fed to the output 27 of the device and interrupts the execution of the program, using the outputs 25 and 26 of the device, it is possible to determine where in the program a loop has occurred.

Claims (1)

Invention Formula A device for monitoring programs containing an address counter, the first AND element, the first OR element, whose output is the output of the device error signal, the first clock input of the device is connected to the counter input of the address counter, characterized in that, in order to increase the monitoring depth, the ability to control the execution time of cyclic program sections with a fixed number of cycle repetitions, a memory block, a register block, a group of counters, a trigger group, an address register, a multiplexer, frator, two groups of elements OR, second element I. second element OR. the device address is connected to the information input of the address register, the output of which is the output of the device address and connected to the first information input of the multiplexer, the second clock input of the device is connected to the clock input of the address register, the third clock input of the device is connected to the enable input of the decoder connected to the first inputs of the corresponding elements of the first and second groups; the input of the device mode setting is connected to the control input of the multiplexer, the output of which is the device's input input is connected to the first inputs of the corresponding elements of the OR group and the record entry of the register block whose outputs are connected to the information inputs of the corresponding group counters, the input setting the program variable code of the device connected to the information input of the memory block, the outputs the first (t-1) bits of which are connected to the corresponding information inputs of the decoder and the inputs of the second OR element, the input of setting the initial device code is connected to and by the formation input of the register block, the recording input of the device is connected to the recording input of the memory block, the output of the main bit of which is connected to the inverse input of the first element AND and the first input of the second element AND, the output of the second element OR is connected to the forward input of the first element AND the second input of the second element AND, the outputs of which are connected to the second inputs of the corresponding elements AND of the first and second groups, the outputs of the second group of elements AND are connected to the second inputs of the corresponding elements OR of the group, the outputs of which are connected to recording strokes corresponding counter group whose counting inputs connected to outputs of the respective AND gates of the first group, the group counter outputs are connected to respective outputs of the first OR gate and the adjusting input triggers group, the outputs of which form the information output device. fig 2