SU1513457A1 - Program debugging device - Google Patents

Abstract

The invention relates to computing and can be used when debugging programs and solving problems of evaluating the effectiveness and optimization of the computational process. The aim of the invention is to improve the reliability of debugging. The device contains a CPU status code register, a memory protection key register, two blocks of buffer memory, two flip-flops, control modes for reading and writing blocks of buffer memory, two address counters for addressing buffer memory cells, a time counter that is intended to calculate the absolute measurement time. The device allows you to memorize the state of the central processor, the time spent in this state and the memory protection key corresponding to each processor state during the execution of the program under study. This information is necessary to build the operating trace of the program. 1 il.

Description

The invention relates to computing and can be used to debug a program, as well as in solving problems of evaluating the effectiveness and optimizing the functioning of computer systems.

The purpose of the invention is to increase the reliability of debugging.

The drawing shows a block diagram of a device for debugging programs.

The device contains a register 1 of the code-state, a register 2 of the memory protection key, a counter 3 times, a comparison circuit 4, the first 5 and second 6 blocks of the buffer memory (W), the first 7 and second 8 counters of the address, the first 9 and the second 10 triggers, first 11, second 12 and third 13 delay elements.

the first 14, the second 15 and the third 16 blocks of the OR elements, the blocks 17-21 of the AND elements, the AND 22-27 elements, the OR elements 28-31, the mode setting input 32, the clock input 33, the rewriting input 34, the input 35 of the logical unit, the first information input 36, the second information input 37 of the device, the output 38 of the overwriting attribute, the information output 39 of the device.

The device works as follows.

In the initial state, the counters 3, 7, 8, triggers 9, 10, and register 1 are reset to the zero state, blocks 5 and 6 of the power supply unit are cleared.

At zero output, trigger 9 is set to a high potential, which

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t | appears at the input of the block 6, E | TORI element input AND 24 and the second E block input element AND 19, thereby setting the block 6 to the recording mode. At the same time, this potential is delivered to the read input of block 5, the first I stroke of the element 26 and the first input of the block of elements 18, thereby setting the block 5 to read mode.

A high potential is suitable to the control input 35 of the device, which is maintained for the entire period of operation of the device. The clock pulses of the computer, which are applied to the input 33 of the device, are transmitted through the element 22 and into the counter input of the counter 3 and the resolution input of the comparison circuit 4. (1 counter 3 records the absolute measurement time. The register 2 stores the code of the current key; 1 memory computer memory, which is recorded through group 37 of the information inputs of the device. On the 36 information inputs of the device (received from the computer the current code (for the central processor, for example, for an ES EC computer, this code corresponds to the value of the fourteenth and fifteenth bits of the program state word.) This code in diagram 4 (the comparison is compared with the previous state code stored in) e 1 (at the beginning of operation of the device, this code is taken equal to i-by.) In the case of a mismatch between these 1O codes, the next impulse, the output i of the output element And 22 to the resolution input of the comparison circuit 4, a pulse signal appears at its output.

This signal through the AND 24 element and the OR 30 element is fed to the read input of block 6. By this signal, through the group of information inputs of the jfca 6 block, the contents of counter 3, registers 1 and 2 are recorded in the next cell.

The address of the next cell of block 6 in: the record mode is determined by the contents of counter 7, which through block 1 of the AND elements and block 15 of the OR elements arrive at the group of address inputs of the Apple 6.

The impulse from the output of the comparison circuit 4 through the delay element 12 also goes to the counting input of the counter 7, increasing its content by one and thereby forming the address of the next cell, which will be

lead record. At the same time, this pulse, through the delay element 11, arrives at the second input of the blocks of elements AND of group 21 and allows writing the current state code to register 1.

After the information has been recorded in the last cell of block 6, counter 7 overflows and it is zeroed. The signal from the overflow output of the counter .7 through the OR element 28 is fed to the counting input of the trigger 9. and sets the latter to one state. At the single output of the trigger 9, a high potential is established, which is sent to the first control input of the unit 5. The second input of the AND 23 element and the second input of the blocks of the AND 17 elements, thereby sets the block 5 into the recording mode.

At the same time, this potential is fed to the read input of block 6, the first input of element I 25 and the first input of blocks of elements AND of group 20, thereby switching the block 6 to read mode. Writing to block 5 is carried out similarly to writing to block 6, while the address of the next cell, determined by the contents of counter 7, goes to the group of address inputs of block 5 through block 17 of elements AND and block 14 of elements OR, and the pulse from the output of circuit 4 compare to the read input of block 5 through the element And 23 and the element OR 31.

The signal from the overflow output of the counter 7 through the RSHI element 29 is postponed to the counting input of the trigger 10, and is set to one state. At the same time, a high potential from a single trigger output goes through the output 38 of the device to a computer, indicating that it is necessary to rewrite information from the completed power supply unit to an external memory. In order to overwrite the contents of the power supply unit from the computer, pulses begin to flow through the control input 34 of the device.

The next impulse, coming through the AND-23 element and the RSHI 30 element to the readout input of block 6, provides readout from the next BP cell, whose address is determined by the contents of counter 8, which goes through AND unit 20 and the OR block 15 group of address inputs of block 6,

Contents of the next cell from the group of information outputs of the block

6 through the block 16 of the elements OR arrives at the group of information outputs of the device 39. With the same impulse, the incoming through the element 13 of the delay and the element 27 at the counting input of the counter 8, the contents of the counter 8 become one unit, thereby forming the address of the next cell which will be read (rewrite).

After reading the contents of the last cell of block 6, counter 8 overflows and it is zeroed. The signal from the output of the overflow of the counter 8 through the OR element 29 arrives at the counting input of the trigger 10 and sets it to the zero state. The low potential at its single output signals the computer to read (rewrite), while the cells of unit 6 are zeroed when reading.

Reading from block 5 is carried out in a similar way, and the address of the next counting cell comes from counter 8 through block 18 of the elements AND and block 14 of the elements OR to the group of address inputs of the block

Upon completion of the operation of the device, it is necessary to read the contents of an incompletely filled power supply unit. For this, a forced reading (rewriting) mode is introduced. In this mode, the control input 32 of the device receives a pulse, which through the OR element 28 sets the trigger 9 to the opposite state, thereby setting the power supply unit, which is at the end of the device operation in the recording mode, into the read mode. At the same time, this impulse through the element OR 29 sets the trigger 10 to one state. Reading from the power supply unit is performed in the same way as described.

Claims (1)

Invention Formula A device for debugging programs containing the first block of buffer memory, the first address counter, the first trigger, the first delay element, the first, second, third and fourth blocks of AND elements, the first and second blocks of OR elements, the status code register, the comparison circuit, the first the OR element, and the group of information outputs of the code register neither is connected to the first group of information inputs of the comparison circuit, the output of which is connected to the input of the first delay element, the single output of the first trigger is connected to the recording input of the first block of the buffer memory, the outputs of the first and second blocks of the And elements are connected respectively to the first and second inputs the first block of elements OR, the outputs of the third and fourth blocks of elements AND are connected respectively to the first and second inputs of the second block 5 elements OR, the input setting the device mode is connected to the first input of the first OR element, characterized in that, in order to increase the reliability of debugging, 0 a second address counter, a second buffer memory block, a second trigger, a second and a third delay elements, a third OR block, a memory protection key register, 5 are entered into it And, the second, third and fourth elements OR, the first, second, third, fourth, fifth and sixth elements AND, and the clock input of the device is connected to the first input of the first element And whose output is connected with input of comparison resolution and with account the first time counter input, the output group of which is connected to the corresponding inputs of the information inputs of the first and second blocks of the buffer memory, the first group of information inputs of the device is connected to the information input group of the fifth block of I elements and the second group of information inputs of the comparison circuit The output of which is connected to the first input of the second and third elements I and to the input of the second 5th delay element, the output of which is connected to the counting input of the first address counter, the group of outputs of which connected to the first groups of the first and third blocks of elements 0 AND, the second group of information inputs of the device is connected to the group of inputs of the register of the security key of the memory, the group of outputs of which is connected to the corresponding inputs of the groups of informational inputs of the first and second blocks of the buffer memory; the outputs of the status code register are connected to the corresponding inputs of the information input groups of the first and second blocks of the buffer memory, the output of the first address overflow is connected to the first input of the second: element The LI and the second input of the first OR input, the output of which is connected to the counting input of the first trigger, the single output of which is connected to the second input of the second element AND, the engraving inputs of the first and fourth record blocks of the elements AND, the first input FROM the second block of the memory buffer and the first input of the fourth element I, the output of which is connected to the first input of the third element OR, the code of which is connected to the second input of resolution of the second block of the buffer memory, the group of information outputs of which is connected to the first frame PPE inputs etego block element or zero yu output of the first flip-flop is connected the control input of the second block of the AND chips, the first input of the read-: and the first block of the buffer memory; 1 is the recording of the second block of the buffer memory, the second input of the third, and AND control terminal of the third liro block of the AND elements and with the first input of the fifth AND element whose output is connected to the first input of the fourth OR element, the output of which connected to the second input of the first unit of the buffer memory, the group 1 of the informational outputs of which is combined with the second group of inputs of the third group of elements of the NL, the group of outputs of which is the group of informational outputs of the device, the input n five rewriting device is connected to the second inputs of the fourth and fifth elements And and the input of the third delay element, the output of which is connected to the first input of the sixth element And whose output is connected to the counting input of the second address counter, the overflow output of which is connected to the second input of the second element SH, output which is connected to the counting input of the second trigger, the unit output of which is connected to the second input of the sixth element I and is the output of the device rewriting sign, the output information output of the second The address counter is connected to the second groups of information inputs of the second and fourth blocks of the AND elements, the outputs of the second and third elements of AND are connected respectively to the second inputs of the fourth and third elements OR, the second input of the first element AND is connected to the unit potential bus of the device, the group of outputs of the first block of elements OR is connected to the group of address inputs of the first block of buffer memory, the group of outputs of the second block of elements OR is connected to the group of address inputs of the second block of buffer memory, output the first delay element is connected to the control at the input of the fifth element block, and, whose output group is connected to the status group of the status code register, the device mode setting input is connected to the third input of the second OR element. 37 36 38 j