SU1137472A1 - Debugging device - Google Patents

Abstract

DEVICE FOR DEBUGGING PROGRAMS containing the memory block, the first delay element and the trigger,. Moreover, the address, information inputs and the read input of the device are connected respectively to the address, information inputs and read input of the memory block, so that, in order to improve the speed when debugging programs, the device is entered the encoder of the Stop command, the group of elements AND, the group of elements OR, the second delay element, and an additional bit are entered into the memory block, the information bits of the memory block and the output of the additional bit of the memory block are connected respectively to the first input And group of elements and with a single trigger input, single and zero outputs of which are connected to the first inputs of the first and second elements AND, respectively, the output of the first element AND are connected to the second inputs of elements AND of a group, the outputs of which are connected to the first inputs of the elements of the OR group, output the second element I is connected to the input of the encoder of the Stop command, the outputs of which are connected to the second inputs of the corresponding OR elements of the group, the read input of the device is connected to the second through the first delay element E inputs of said first and second AND gates, the output of the second delay element connected to the zero input of the trigger input of the second delay element podksch) chen to an input of second AND, OR element outputs oo th group form a group of information outputs of the device.

Description

The invention relates to digital computing and can be used for debugging task programs of specialized computers that contain regular memory blocks (HVs) with work programs.

A device for debugging programs has been notified that contains a clock pulse generator, operating registers, a command counter, a program memory block, an address generation block, a mutation block and a control block, which, after executing each executed main program command using a switching unit, inserts and executes several ancillary service commands that print the contents of the main registers and the computer counter for commands. After printing, the control unit generates the address of the following command l.

A disadvantage of this device is the lack of operational control of the correctness of the program passing along the intended path of addresses and in real time.

The closest to the proposed technical entity is a device containing a program memory block, an address, information inputs and a read input of which are connected respectively to an address, information inputs and a device read input, an operational storage block, an analysis block, command code whose input is connected to the output of the program memory block, the information census organization block whose inputs are associated respectively with the address input of the program memory block and with the output of the instruction code analysis block. The output of the census organization unit is connected to the input of the operational storage unit.

The known device, if there is a conditional branch in the command code, records the address of this command in the corresponding cell 6 of the operative storage unit. Upon completion of the passage of the program or its part, the course of the computational process recorded in the operational unit 2J is displayed.

The disadvantage of the prototype device is the inability to operatively /

monitor the correctness of the passage of the program.

The purpose of the invention is to increase speed when debugging programs.

This goal is achieved by the fact that the Stop command is entered into the device for debugging programs containing the memory block, the first delay element and the trigger, the information, address inputs and the read input of the device corresponding to the address, information inputs and read input of the memory block. , a group of elements And, a group of elements of scientific research institutes, a second delay element, and an additional bit is inserted into the memory block, the information outputs of the memory block and the output of the additional bit of the memory block are connected respectively, with the first inputs of the elements of the AND group and with the single input of the trigger, the unit and zero outputs of which are connected to the first inputs of the first and second elements AND, respectively, the output of the first element AND is connected to the second inputs of the elements AND of the group whose outputs are connected to the first inputs of the elements of the OR group , the output of the second element I is connected to the input of the encoder of the Stop command, the outputs of which are connected to the second inputs of the corresponding elements of the OR group, the read input of the device through the first element of the output ki is connected to the WTO .rymi inputs of the first and second AND gates, the output of the second delay element connected to the zero input of the flip-flop, a second input of the delay element is connected to the input of the second AND gate, outputs of OR group elements form a group of information outputs of the device. .

The drawing shows a block diagram of the device.

The device contains a memory block 1, a cervical delay element 2, a trigger 3, whose single input is connected to the output of an additional bit of memory 1, the first and second elements 4 and 5, the first inputs of which are connected respectively to the zero and single outputs of trigger 3 , the second inputs are combined and connected with the output of delay element 2, the second delay element 6, the output of which is connected to the zero input of the igger 3, the group of elements And 7, the cipher

Torus of the Stop command and the group of OR elements, the output of which is the output of the device, the address, information inputs and the read input of the device, respectively, are connected to the address, information inputs and the read input of memory 1. The read input of memory block 1 is associated with the input of the first delay element 2. The input of the second element 6 delay combined with the input of the encoder 8 and connected to the output element And 5.

The information outputs of the memory block 1 and the output of the AND 4 element are connected respectively to the first and second inputs of the group of elements AND 7. The output of the group of elements AND 7 is connected to the first input of the group of elements OR .9, the second input of which is connected to the output of the encoder 8 Stop.

The device works as follows.

Through the information input of the device, the memory 1 is loaded with the initial version of the program to be debugged. Simultaneously by. these addresses are also recorded information in the additional bits of the memory 1. The value of the information recorded in the extra bit is determined by a trace oriented graph of the addresses used in the debugging process. In this case, the vertices of the route are understood as addresses of conditional jumps. Then, in the process of reading, the address code of the selected cell of memory 1 is fed to the address input of the device, and the interrogation signal is sent to the read input.

If the memory of the address code and the polling signal from the block is present at the inputs of block 1, information is read that goes to the first inputs of the group of elements And 7 information part) and to the single input of trigger 3 (information read from the additional bit).

The interrogation signal, which arrives at the corresponding input of the memory block 1, is simultaneously applied to the input of the first delay element 2. Further, this signal, delayed by the delay element 2 at the time of the operation of the memory block 1 and the installation of the trigger 3, is fed to the second input of the AND 4 and 5 elements.

Depending on the state of the trigger 3, the signal will pass through the element 4 or 5.

The first case corresponds to the course of the program along the intended path of the selected addresses. Bq second case promptly establishes the fact of inconsistency during the course of the program

From the output of the element And 4, the signal post goes to the second input of the group of elements And 7 and highlights the information located on the first input of this group. As a result, an information word read from memory block 1 appears at the output of the group of elements AND 7 and passes through the group of elements OR 9 to the output of the device. If a signal appears. At the output of the AND 5 element, then, firstly, after passing through the second delay element 6, sets the trigger 3 to the initial state, secondly, it enters the input of the stop command 8 encoder, which is transmitted through group of elements ШШ 9 on the device output.

The technical advantage of the proposed device is the ease of implementation of the correctness of the passage of the program in the process of debugging it.

Claims (1)

DEVICE FOR DEBUGGING PROGRAMS, containing a memory unit, a first delay element and a trigger, and the address, information inputs and read input of the device are connected respectively to the address, information inputs and read input of the memory unit, as a whole the fact that, in order to improve performance when debugging programs, the command encoder 'Stop', a group of AND elements, a group of OR elements, a second delay element are introduced into the device, and an additional bit is inserted into the memory block, and the information outputs of the memory block and the output of the additional discharge of the memory block is connected respectively to the first inputs of the elements of the And group and to the single input of the trigger, the unit and zero outputs of which are connected to the first inputs of the first and second elements And, accordingly, the output of the first element And is connected to the second inputs of the elements And groups, the outputs of which connected to the first inputs of the elements of the OR group, the output of the second element AND connected to the input of the encoder of the Stop command, the outputs of which are connected to the second inputs of the corresponding elements of $ OR groups s, the readout input of the device through the first delay element is connected to the second inputs of the first and second elements AND, the output of the second delay element is connected to the zero £ input of the trigger, the input of the second delay element is connected to the input of the second element AND, the outputs of the OR elements of the group form a group of information outputs' devices. > 1 1137472 2