JPH03157739A - Performance measuring system for epu - Google Patents

Abstract

PURPOSE:To measure the performance of an arithmetic processor (EPU) without affecting on the ordinary operation of the EPU by assembling hardware dedicated for performance measurement in a system. CONSTITUTION:A micro address designation register 1 is the one to set the entry address of the specific processing routine of a microprogram, and a current address 2 is the address of the microprogram running at present, and comparison with the output signal of the micro address designation register 1 is performed with a coincidence detection circuit 3. A measuring mode signal 4 goes to a high level while performing performance measurement, and at this time, when the coincidence detection circuit 3 detects coincidence with a micro address, an inter-one-clock cycle micro address coincidence detecting pulse 6 is inputted to the input terminal of a counter 7, and is counted up. In such a way, it is possible to measure the performance of the EPU simultaneously while the ordinary operation of the EPU is being performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an EPU performance measurement method, and more particularly to an EPU performance measurement method for measuring the number of times a microprogram is executed.

[Conventional technology]

Conventionally, the performance measurement methods for this type of processing unit include methods that measure various performances using soft-visible general-purpose registers using software, and methods that measure various performances using dedicated measurement equipment other than the system. is normal.

[Problem to be solved by the invention]

Performance measurement using the conventional software described above requires the creation of a dedicated program. Furthermore, since the performance measured here is based on a certain optimized state of the measurement environment, there is a possibility that the performance is different from the performance when the information processing apparatus is normally operating. In addition, in software, the number of executions of a certain instruction can be measured;
There are factors that cannot be seen by software, such as the number of times a particular interrupt occurs. In addition, depending on the software, performance may not be measured because it uses all the general-purpose registers that can be used for performance measurement.

In such cases, performance is measured using a dedicated measuring device other than the system, such as a logic tracer. In this case, there is a drawback that it takes a lot of time to set up the physical measurement environment and analyze the five measurement results.

In view of the above, an object of the present invention is to measure the performance of an EPU without affecting the normal operation of the EPU by incorporating hardware dedicated to performance measurement into the system.

[Means to solve the problem]

The EPU performance measurement method of the present invention is a performance measurement method for an arithmetic processing unit (hereinafter abbreviated as EPU) that operates by a microprogram, and includes a register in which a specific address of the microprogram can be set, and a register that can set a specific address of the microprogram, and a register that can set a specific address of the microprogram and an address that is currently running. and a counter that counts the number of matches.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the EPU performance measurement system of the present invention.

The performance measuring device of the first embodiment is composed of a microaddressing register 1, a -number output circuit 3, an AND circuit 5, and a counter 7, and the microaddressing register 1 and current address 2 are When they match, if the measurement mode signal 4 is in the measurement mode, a microaddress coincidence detection pulse 6 is generated and input to the counter 7.

Microaddress designation register 1 is a register for setting the entry address of a specific processing routine of the microprogram to be counted, and current address 2 is the address of the currently running microprogram.
-Micro address designation register 1 by several output circuit 3
Compare with the output signal of The measurement mode signal 4 becomes "high" level during performance measurement, and at this time - several sheet output circuit 3
When detecting a match between the micro addresses, the micro address match detection pulse 6 for one clock cycle of the match is input to the input terminal of the counter 7, and is counted up.

Next, the operation of this device will be explained.

First, it is assumed that the number of executions of a specific processing routine A whose entry address is XXXX, for example, is counted. First, the entry address XXXX is set in the microaddress designation register 1 and held until the measurement is completed. When the output of this register matches current address 2, which is the address of the currently running microprogram, the match detection circuit 3 generates a pulse for one clock cycle. This pulse is ANDed with the measurement mode signal 4 and transmitted to the counter 7 only in the measurement mode.

Therefore, this device uses the entry address ×× during measurement mode.
Since the count is incremented each time XX is passed, the number of executions of the specific processing routine A is counted.

FIG. 2 shows the configuration of a second embodiment of the present invention, and is a block diagram of a performance measuring device provided with a plurality of counters that share the current address 2 and measurement mode signal 4 in FIG. 1. It is a diagram. The second embodiment shown in FIG. 2 is composed of a plurality of microaddress registers 10, a coincidence detection circuit 11, an AND circuit 12, and a counter 13, and its basic operation is exactly the same as that shown in FIG. However, since the entry addresses of a plurality of specific processing routines can be set, it is possible to simultaneously measure the number of executions of a plurality of specific processing routines during a series of operations of the EPU.

〔Effect of the invention〕

As explained above, the present invention has the advantage of being able to measure the number of executions of a microprogram at a specific address, and thus making it possible to count the number of occurrences of a specific interrupt and to measure statistical data on the occurrence of that interrupt.

Furthermore, when the above address is designated as the execution microprogram address of a specific instruction, the number of times the instruction is executed can be measured, and when the instruction execution time is measured at the same time, the average instruction execution time of the information processing device can also be measured. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of a first embodiment of the invention, and FIG. 2 is a block diagram showing the structure of a second embodiment of the invention. 1・10...Micro address specification register, 2...
Current address, 3.13...-number output circuit, 4.
・・Measurement mode signal, 5・15・AND circuit, 6・
・・Micro address - several output pulses, 7・17...
counter.

Claims (1)

[Claims] 1. An arithmetic processing device (
In the performance measurement method of EPU (hereinafter abbreviated as EPU), a register that can set a specific address of a microprogram,
A method for measuring the performance of an EPU, comprising: a circuit for detecting a match between the address and a currently running address; and a counter for counting the number of matches. 2. The EPU according to claim 1, wherein the EPU comprises a plurality of the registers, a plurality of the match detecting circuits, and a plurality of the counters, each of which is independently connected.
performance measurement method.