JPH01243141A - Information processor - Google Patents

Information processor

Info

Publication number
JPH01243141A
JPH01243141A JP63070788A JP7078888A JPH01243141A JP H01243141 A JPH01243141 A JP H01243141A JP 63070788 A JP63070788 A JP 63070788A JP 7078888 A JP7078888 A JP 7078888A JP H01243141 A JPH01243141 A JP H01243141A
Authority
JP
Japan
Prior art keywords
counting
counter
instruction word
register
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63070788A
Other languages
Japanese (ja)
Inventor
Sadaji Asano
淺野 貞二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63070788A priority Critical patent/JPH01243141A/en
Publication of JPH01243141A publication Critical patent/JPH01243141A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To easily measure the processing speed and appearing frequency of an instruction word by providing a counter and controlling the counting action of the counter according to the execution of a specific instruction word. CONSTITUTION:Two kinds of actions are executed according to a mode signal 8, and when the instruction word set to a comparison register 3 beforehand is executed in the case where the mode signal is at a logical value '0', a counter 6 executes the counting action for each rise of a clock pulse 9. When the execution of the instruction word is completed, the logical value of a signal line 901 is made into '0', the counter 6 stops the counting action, and the processing speed of the instruction word is measured by the counted value. On the other hand, when the mode signal 8 is at a logical value '1', the counter 6 is counted up when the contents of an instruction register 1 and comparison register 3 coincide, and the appearing frequency is measured. Thus, the processing speed and executing frequency at the time of executing the specific instruction word can be easily measured.

Description

【発明の詳細な説明】 皮血立1 本発明は情報処理装置に関し、特に命令語の処理速度等
を測定することができる情報処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an information processing device capable of measuring the processing speed of command words.

良米孜韮 従来、情報処理装置の処理速度等を測定するために、ト
レーサ(Tracer )を設け、特定のアドレス値を
レジスタに格納しておき、実行中のアドレスと比較を行
い、一致した時にトレースを停止してその内容を調査し
ていた。
Traditionally, in order to measure the processing speed of information processing equipment, a tracer was installed, a specific address value was stored in a register, and the address was compared with the address being executed. I stopped the trace and investigated its contents.

しかし、その従来の方式では、特定のアドレス値に応じ
てトレースを停止していたため、サブルーチンの終了の
検出や特定命令群の出現頻度の測定等、特定の命令語の
実行に応じた測定ができないという欠点があった。
However, in this conventional method, tracing was stopped according to a specific address value, which made it impossible to measure the execution of a specific instruction word, such as detecting the end of a subroutine or measuring the frequency of appearance of a specific instruction group. There was a drawback.

九肌A旦週 本発明の目的は、特定の命令語の実行時の処理速度のみ
ならずその実行頻度をも極めて容易に測定することがで
きる情報処理装置を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that can extremely easily measure not only the processing speed when executing a specific instruction word, but also its execution frequency.

発明の構成 本発明の情報処理装置は、特定の命令語の実行開始から
終了までの間所定周期ごとに計数パルスを送出する第1
の計数パルス送出手段と、前記命令語の実行開始のとき
にのみ計数パルスを送出する第2の計数パルス送出手段
と、前記計数指令に応じて計数を行う計数手段と、前記
第1及び第2の計数パルス送出手段からの計数パルスを
外部指令に応じて択一的に前記計数手段に送出する切換
送出手段とを有することを特徴とする。
Composition of the Invention The information processing device of the present invention provides a first counting pulse that sends out counting pulses at predetermined intervals from the start to the end of execution of a specific instruction word.
counting pulse sending means, second counting pulse sending means for sending out counting pulses only when execution of the command word starts, counting means for counting in response to the counting command, and the first and second counting pulses. It is characterized by comprising a switching sending means for selectively sending counting pulses from the counting pulse sending means to the counting means in accordance with an external command.

火徂舅 以下、図面を用いて本発明の詳細な説明する。father-in-law of fire Hereinafter, the present invention will be explained in detail using the drawings.

第1図は本発明による情報処理装置の一実施例の構成を
示す系統図である。図において、本発明の一実施例によ
る情報処理装置は、命令レジスタ1と、マスクレジスタ
2と、比較レジスタ3と、レジスタ5と、カウンタ6と
、アンド回路71゜72.74及び75と、比較器73
と、オア回路76とを含んで構成されている。
FIG. 1 is a system diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention. In the figure, the information processing device according to the embodiment of the present invention includes an instruction register 1, a mask register 2, a comparison register 3, a register 5, a counter 6, AND circuits 71, 72, 74, and 75, and vessel 73
and an OR circuit 76.

命令レジスタ1は現在実行中の命令語を保持するもので
ある。
Instruction register 1 holds the instruction word currently being executed.

比較レジスタ3は測定したい命令語を予め保持させてお
くものである。
The comparison register 3 is used to hold in advance an instruction word to be measured.

比較器73はマスクレジスタの値に応じて命令レジスタ
1と比較レジスタ3との内容を比較するものでり、比較
結果が一致を示せば、出カフ31か論理値「1」になる
ものである。
The comparator 73 compares the contents of the instruction register 1 and the comparison register 3 according to the value of the mask register, and if the comparison result shows a match, the output value becomes 31 or the logical value "1". .

マスクレジスタ2はアンド回路71及び72により、命
令レジスタ1及び比較レジスタ3の内容にマスクをかけ
るものである。
Mask register 2 masks the contents of instruction register 1 and comparison register 3 by AND circuits 71 and 72.

レジスタ5はアンド回路74の出力を保持するものであ
る。
Register 5 holds the output of AND circuit 74.

カウンタ6はアンド回路75の出力の立上りに応じてカ
ウントアツプを行うものである。
The counter 6 counts up in response to the rise of the output of the AND circuit 75.

オア回路76はモード信号8とクロックパルス9との論
理和の信号を送出するものである。
The OR circuit 76 sends out a signal of the logical sum of the mode signal 8 and the clock pulse 9.

信号線901は通常、論理値「1」であり、命令語の実
行終了ごとに論理値「0」となるものである。
The signal line 901 normally has a logic value of "1", and changes to a logic value of "0" each time execution of a command word is completed.

かかる構成からなる情報処理装置は、モード信号8に応
じて2種類の動作を行うものである。
The information processing device having such a configuration performs two types of operations depending on the mode signal 8.

まず、モード信号が論理値rQJのときには、特定の命
令語の処理速度を測定することができる。
First, when the mode signal has a logical value rQJ, the processing speed of a specific command word can be measured.

この場合、予め比較レジスタ3に設定しておいた命令語
が実行されると、比較器73の出カフ31が論理値「1
」、アンド回路74の出力も論理値「1」となり、レジ
スタ5の保持値が論理値「1」となる。
In this case, when the instruction word set in the comparison register 3 in advance is executed, the output cuff 31 of the comparator 73 becomes a logical value "1".
”, the output of the AND circuit 74 also becomes a logical value “1”, and the value held in the register 5 becomes a logical value “1”.

すると、クロックパルス9がオア回路76を介してアン
ド回路75に入力されるため、カウンタ6はクロックパ
ルス9の立上り毎にカウント動作を行う。
Then, since the clock pulse 9 is input to the AND circuit 75 via the OR circuit 76, the counter 6 performs a counting operation every time the clock pulse 9 rises.

そして、その命令語の実行が終了すると信号線901の
論理値が「0」となるため、アンド回路74の出力が論
理値「0」になり、レジスタ5の保持値が論理値「0」
となる。これにより、カウンタ6はカウント動作を停止
する。このカウンタ6のカウント値により、その命令語
の処理速度を測定することができるのである。
When the execution of the instruction word is completed, the logic value of the signal line 901 becomes "0", so the output of the AND circuit 74 becomes the logic value "0", and the value held in the register 5 becomes the logic value "0".
becomes. As a result, the counter 6 stops counting. The count value of the counter 6 allows the processing speed of the instruction word to be measured.

一方、モード信号8が論理値「1」のときには、特定の
命令語の出現頻度(回数)を測定することができる。こ
の場合、予め設定しておいな命令語が実行されると比較
器73の出カフ31が論理値「1」、アンド回路74の
出力も論理値「1」となり、レジスタ5の保持値が論理
値「1」となる。
On the other hand, when the mode signal 8 has a logical value of "1", the frequency (number of times) of appearance of a specific command word can be measured. In this case, when the preset instruction word is executed, the output 31 of the comparator 73 becomes a logic value "1", the output of the AND circuit 74 also becomes a logic value "1", and the value held in the register 5 becomes a logic value "1". The value becomes "1".

= 5 = ここで、オア回路76は、常に出力か論理値「1」であ
り、この値がアンド回路75に入力されているため、カ
ウンタ6は「1」カウントアツプする。つまり、モード
信号8が論理値「1」の場合には、命令レジスタ1と比
較レジスタ3との内容が一致したときにカウンタ6がカ
ウントアツプすることになり、特定の命令語の出現頻度
を測定することかできるのである。
= 5 = Here, the OR circuit 76 always outputs the logical value "1", and this value is input to the AND circuit 75, so the counter 6 counts up "1". In other words, when the mode signal 8 has a logical value of "1", the counter 6 counts up when the contents of the instruction register 1 and the comparison register 3 match, and the frequency of appearance of a specific instruction word is measured. You can do what you want.

発明の詳細 な説明したように本発明は、カウンタを設け、このカウ
ンタのカウント動作を特定の命令語の実行に応じて制御
することにより、その命令語の処理速度や出現頻度を容
易に測定することができるという効果がある。
DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides a counter and controls the counting operation of this counter according to the execution of a specific instruction word, thereby easily measuring the processing speed and appearance frequency of that instruction word. It has the effect of being able to

【図面の簡単な説明】 第1図は本発明の実施例による情報処理装置の構成を示
す系統図である。 主要部分の符号の説明 1・・・・・・命令レジスタ 3・・・・・・比較レジスタ 6・・・・・・カウンタ 73・・−・・・比較器 71.72.74.75・・−・・・アンド回路76・
・・・・・オア回路
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. Explanation of symbols of main parts 1... Instruction register 3... Comparison register 6... Counter 73... Comparator 71.72.74.75... −...AND circuit 76・
...OR circuit

Claims (1)

【特許請求の範囲】[Claims] (1)特定の命令語の実行開始から終了までの間所定周
期ごとに計数パルスを送出する第1の計数パルス送出手
段と、前記命令語の実行開始のときにのみ計数パルスを
送出する第2の計数パルス送出手段と、前記計数指令に
応じて計数を行う計数手段と、前記第1及び第2の計数
パルス送出手段からの計数パルスを外部指令に応じて択
一的に前記計数手段に送出する切換送出手段とを有する
ことを特徴とする情報処理装置。
(1) A first counting pulse sending means that sends out counting pulses at predetermined intervals from the start to the end of execution of a specific command word, and a second counting pulse sending means that sends out counting pulses only when the execution of the command word starts. a counting pulse sending means for counting according to the counting command; and counting pulses from the first and second counting pulse sending means are selectively sent to the counting means according to an external command. 1. An information processing device comprising: switching and transmitting means.
JP63070788A 1988-03-24 1988-03-24 Information processor Pending JPH01243141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63070788A JPH01243141A (en) 1988-03-24 1988-03-24 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63070788A JPH01243141A (en) 1988-03-24 1988-03-24 Information processor

Publications (1)

Publication Number Publication Date
JPH01243141A true JPH01243141A (en) 1989-09-27

Family

ID=13441619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63070788A Pending JPH01243141A (en) 1988-03-24 1988-03-24 Information processor

Country Status (1)

Country Link
JP (1) JPH01243141A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008276683A (en) * 2007-05-07 2008-11-13 Nec Electronics Corp Testing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008276683A (en) * 2007-05-07 2008-11-13 Nec Electronics Corp Testing device

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