JPH0231247A - Data processor - Google Patents

Abstract

PURPOSE:To easily measure the processing performance of an instruction executed within a designated period by counting the executing time and the executing frequency of instructions for a period during which the instruction address is coincident with the 1st prescribed value set previously and then with the 2nd prescribed value set previously. CONSTITUTION:The registers 2 and 3 store the instruction addresses set previously and then set these addresses again by an address setting signal 114 received from a diagnosis processor 11. Then data are set at the counters 9 and 10 by a control signal 113 and at the same time the count value signals 111 and 112 are read out of both counters by the signal 113. Thus it is possible to count the instruction executing time and the instruction execution frequency for a designated period independently of the instruction processing actions carried out by an instruction processing circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a circuit for measuring the instruction processing performance of a data processing device.

Traditionally, data processing equipment uses a timer (counter) to measure the time required to process an instruction for each process.
A counter is provided for counting the number of executions of instructions processed for each process. These counters are constantly counting while instructions are being executed for process processing.

In such conventional data processing devices, instructions are executed for process processing using a counter for measuring the time required to process an instruction and a counter for counting the number of executions of the processed instruction. Since counting is always performed during the period, there is a drawback that it is impossible to measure the execution time and number of executions of an instruction in any specified period.

The present invention was made in order to eliminate the drawbacks of the conventional devices as described above, and provides a data processing device that can easily measure the processing performance of instructions executed within a specified period. For the purpose of providing.

A data processing device according to the present invention includes a first counting means for counting the execution time of an instruction, a second counting means for counting the number of executions of the instruction, and a first predetermined predetermined time. a first holding means for holding a value; a second holding means for holding a second predetermined value; and a first holding means for holding a second predetermined value; When it matches a predetermined value, the counting operations of the first and second counting means are started, and when the instruction address of the instruction matches the second predetermined value held in the second holding means. , and means for stopping counting operations of the first and second counting means.

K1'' Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 0, a data processing device according to an embodiment of the present invention includes an instruction processing circuit 1, a register 2.3, a comparison circuit 4. 5, a flip-flop 6, AND circuits 7 and 8, counters 9 and 10, and a diagnostic processor 11.

The instruction processing circuit l is a circuit that sequentially processes instructions specified by an instruction address in a computer or the like, and -
The output signal 101 is set to "1" every time an instruction is executed, and the instruction address indicating the instruction executed at this time is set to the output signal 1.
Output as 02.

The registers 2.3 each hold preset instruction addresses, and these instruction addresses are set by the address setting signal 114 from the diagnostic processor 11.

The comparator circuits 4.5 each receive the output signal 1 from the register 2.3.
03.104 and the output signal 102 from the instruction processing circuit 1
If a match is detected by the comparison, "1" is outputted to the flip-flop 6 as output signals 105 and 106, respectively.

Flip-flop 6 receives output signal 105 from comparator circuit 4
When the output signal 106 from the comparator circuit 5 becomes 1n, it is set to 1'', and when the output signal 106 from the comparator circuit 5 becomes 1n, it is set to 0. The output signals 107 of the flip-flops 6 are respectively output to AND circuits 7.8. That is, the flip-flop 6 is used as a valid condition when the counters 9 and 10 perform counting.

The AND circuit 7 outputs the output signal 10 from the flip-flop 6.
7 and the pulse signal 108 having a period of 1 us, and outputs the result to the counter 9 as a count pulse signal 109. That is, from the time when the comparison circuit 4 detects a match until the comparison circuit 5 detects a match, the AND circuit 7 outputs "1" to the counter 9 as a count pulse signal 109 every 1-by the pulse signal 106. Ru.

The AND circuit 8 performs an AND operation on the output signal 101 from the instruction processing circuit 1 and the output signal 107 from the flip 70 tube 6, and outputs the result of the operation to the counter 10 as a count pulse signal 110. That is, AND circuit 8
From then on, from when the comparison circuit 4 detects a match until the comparison circuit 5 detects a match, 1'' is outputted to the counter 10 as a count pulse signal 110 every time one instruction is executed in the instruction processing circuit 1.

Counter 9 receives count pulse signal 1 from AND circuit 7
09, the time during which the output signal 107 from the flip-flop 6 is "L" is counted, and the count is incremented every 1 tone.

The counter 10 outputs an output signal 107 from the flip roller 16 in response to a count pulse signal 110 from the AND circuit 8.
“Counts the number of instructions executed by the instruction processing circuit 1 during 1n.

The diagnostic processor 11 sets an address in the register 2.3 by the address setting signal 114, sets data in each of the counters 9.10 by the control signal 113, and
In response to a control signal 113, count value signals 111 and 112 are read out from counters 9 and 10, respectively.

As a result, independently of the instruction processing operation executed by the instruction processing circuit 1, the diagnostic processor 11 can set addresses in the registers 2 and 3, set data in the counters 9 and 10, and output the count value signals 111 and 112. Since reading etc. can be controlled, the instruction processing circuit 1 can process the job without affecting the processing.
It is possible to measure the instruction execution time and the number of instruction executions during an arbitrarily specified period. From this measurement result, the number of instruction executions per unit time, that is, the instruction processing performance can be determined.

FIG. 2 is a diagram showing a sequence of instructions processed in an embodiment of the present invention and their instruction addresses. These instructions are sequentially executed by the instruction processing circuit l''C'', where the instruction address is expressed in hexadecimal.

FIG. 3 is a diagram showing the values set in registers 2.3 in FIG. 1. In FIG.
0090' is set in register 3, and 12000004' is set in register 3, respectively. Here, the value set in register 2.3 is displayed in hexadecimal.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

The diagnostic processor 11 writes “13” to the registers 2 and 3 respectively.
00G09G"12000004' (see FIG. 3), the instruction processing circuit 1 sequentially executes the instruction sequence as shown in FIG. As the output signal 102 of “130
Since 00090' is output, a match is detected in the comparison circuit 4 and the output signal 107 of the flip-flop 6 becomes "1".

Therefore, the counter 9 is incremented every time the pulse signal 108 becomes 1", and the counter 10 is incremented every time the instruction processing circuit 1 executes an instruction, that is, the output signal 101 becomes 1n. The count is increased every time.

When the instruction a9 is executed in the instruction processing circuit 1 while the counters 9 and 10 are counting, the output signal 1G2 from the instruction processing circuit 1 is “12000004”.
Since "°" is output, the comparison circuit 5 detects a match and the output signal 107 of the flip-flop 6 becomes "0".

Therefore, from now on, the count pulse signals 109, 110 from the AND circuit 7.8 will be "0" in the counter 9.10.
”, so the count-up is stopped.

As a result, the pulse signal 106 of the counter 7 becomes 1'' while the output signal 107 from the flip-flop 6 is '1'', that is, from when the instruction b1 is executed to when the instruction a9 is executed in the instruction processing circuit 1. The number is counted up. Therefore, the instruction execution time for a period specified by the values set in registers 2 and 3 can be measured.

In addition, the counter 8 outputs a counter 8 while the output signal 107 from the flip-flop 6 is "IH", that is, every time one instruction is executed in the instruction processing circuit 1 from when the instruction b1 is executed to when the instruction a9 is executed in the instruction processing circuit 1. It is counted up and shows "17", and it is possible to measure the number of instruction executions in the period specified by the value set in the register 2.3.

In one embodiment of the present invention, in order to instruct the two counters 9 and 10 to start and stop counting, the instruction address and the specified address are compared, and when a match is detected by the comparison, the counting starts. Alternatively, although the stopping is controlled, the set/reset of the flip-flop 6 can also be directly controlled from the diagnostic processor 11.

In this case, the register 2.3 and the comparator circuit 4.5 are unnecessary, and the output signals 105 and 106 from the comparator circuit 4.5 that control the setting/resetting of the flip 70 knob 6 are outputted from the diagnostic processor 11. become.

In this way, while "1" is set in the flip-flop 6, that is, after the instruction address of the instruction executed by the instruction processing circuit 1 matches the value set in the register 2, the value is set in the register 3. By controlling the counter 9.10 to count the execution time and number of executions of the instructions executed in the instruction processing circuit 1 until they match the value set in the register 2.3, The processing performance of commands can be easily measured.

As explained above, according to the present invention, the command address of an instruction matches a predetermined first predetermined value until it matches a predetermined second predetermined value. By counting the period of time, the instruction execution time, and the number of executions, there is an effect that the processing performance of instructions executed within a specified period can be easily measured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a sequence of instructions processed in an embodiment of the invention and their instruction addresses, and FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a diagram showing values set in registers. Explanation of symbols of main parts 1...Instruction processing N circuit 2.3...Register 4.5...Hikyo circuit 6...Flip-flop 7. 8...AND circuit 9.10...Counter 11...Diagnostic processor

Claims (1)

[Claims] (1) A first counting means for counting the execution time of an instruction, a second counting means for counting the number of executions of the instruction, and a first holding means for holding a first predetermined value set in advance. , a second holding means holding a second predetermined value set in advance; and when the instruction address of the instruction matches the first predetermined value held in the first holding means, the first and starts the counting operation of the second counting means, and when the instruction address of the instruction matches the second predetermined value held in the second holding means, the first and second counting means
and means for stopping the counting operation of the counting means.