JPH05134901A - Analyzer - Google Patents

Abstract

PURPOSE:To debug the hardware and the software in a short time by displaying externally the using frequency of the address where the optional data is set in a processing mode of a device and also the using frequency of the data regardless of the operation of the device. CONSTITUTION:When a power supply is applied to a device containing an analyzer, a BSRST signal 17 is outputted. Then a counter 16 is reset and a display device 10a shows 0. Under such conditions, the desired data to be monitored are set at a data setting part 7. When the device starts its processing, an address signal 5 is outputted together with a data signal 6 and a WTC signal 13. A comparator 8 outputs an EQ signet 14 when the set data are coincident with the signal 5. At the same time, the signal 13 is outputted from the device together with a TC signal 15. A register 9 latches the signal 15 with output of the signal, 15, and the counter 16 adds 1 to the display data. The display devices 10a and 10b show the outputs of the register 9 and the counter 16 to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention receives the control signal, address signal and data signal from the control device of the mounted device to determine the address and the number of times of use for the arbitrarily set data during the operation of the mounted device. It relates to an analyzer that can be displayed externally regardless of the operation of the attached device.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional apparatus without an analyzer. In the figure, 1 is a central processing unit that inputs / outputs an address signal and a data signal by a control signal when executing an instruction stored in a predetermined storage device, and 2 is a control signal output from the central processing unit. An external input / output unit 3 for exchanging data with an external device specified based on the data is stored in an address specified based on a control signal output from the central processing unit, or outputs data at a specified address. Storage device section, 4 is a control signal for controlling each device, 5 is an address signal indicating address data, 6
Is a data signal for transmitting transfer data.

Next, the operation will be described. In such a device, when the central processing unit 1 performs a series of operations, the central processing unit 1 uses the data signal 6, the address signal 5, and the control signal 4 in the storage unit 3 to perform the central processing unit 1. Write the program executed by (the data input from the external input / output unit 2). When the writing is completed and the control signal 4 for starting the processing is received from the external input / output unit 2, the central processing unit 1 based on the program data stored in the storage unit 3, the data signal 6, the address signal 5, and the control signal 4 Is used for processing. During this process, it is impossible to externally monitor the process performed by the central processing unit 1 without interrupting the process. When the series of processing is completed, the central processing unit 1 transmits the result and the completion to the outside through the external input unit 2.

[0004]

In the case of the above apparatus, once the processing is started, the address of the data input / output by the central processing unit and the number of times the data is used can be grasped unless the processing is interrupted. Since it is not possible, there is a problem that debugging work of software and hardware takes time and cannot be performed easily.

The present invention has been made to solve the above problems, and when an apparatus to be mounted is executing a process, an address input / output by an apparatus to be mounted with certain data set arbitrarily and It is an object of the present invention to obtain an analyzer that can display the number of times the data is used, regardless of the device to be mounted.

[0006]

[Means for Solving the Problems] A signal is output when a data setting unit capable of arbitrarily setting data to be analyzed in a mounted device and the data set by the data setting unit and the data output by the mounted device match. Equipped with a comparator, a register that can latch the address output by the attached device when necessary, an indicator that can display the output data of the register and counter, and a buffer for receiving the signal from the attached device. An OR gate for generating a latch timing of an address output from the device and a signal of a count clock of the counter, and a counter for counting the number of times of use of the data set by the data setting unit are provided, and an arbitrary operation is performed in a series of operations of the attached device. The address corresponding to the data and the number of times of using the arbitrary data are externally displayed regardless of the operation of the mounted device. And it can be so.

[0007]

According to the present invention, the address at which the mounted device inputs / outputs arbitrary data set during processing and the number of times the data is used are externally displayed regardless of the operation of the mounted device.

[0008]

【Example】

Example 1. FIG. 1 shows an embodiment of a storage initialization device according to the present invention. In FIG. 1, 5 and 6 are the same as in the above-mentioned conventional technique, 7 is a data setting unit that can arbitrarily set the analyzed data in the mounted device, 8 is data set by the data setting unit 7 and data output by the mounted device. A comparator that outputs an EQ signal 14 when the signal 6 matches, a register 9 that latches the address output by the mounted device by a trigger of the TC signal 15, and 10a and 10b that output data from the register 9 and the counter 16. Display that can be displayed, 11a-
11d is a buffer for receiving a signal from the mounted device, 12 is a timing for latching the address signal 5 from the WTC signal 13 which is a data write signal output from the mounted device and the EQ signal 14 output from the comparator. An OR gate that generates a TC signal 15 that indicates that, 13 is a WTC signal that is one of the control signals that the mounted device outputs when writing data to an address, and 14 is a data setting unit 7.
The EQ signal output from the comparator 8 when the data set in 1 and the data signal 5 output from the mounted device match, 15 is the OR gate 12 when the address is taken into the register 9 and when the counter 16 counts. TC signal 16 is a counter for counting the number of TC signals 15, and 17 is a BSRST signal which is one of the control signals output from the device to be mounted when the power of the device to be mounted is applied.

The operation of the analyzer described above will be described with reference to FIG. When power is applied to the device equipped with the analyzer, the installed device outputs the BSRST signal 17, the counter 16 is reset, and the display on the display 10a shows 0. Here, the data to be monitored is set by the data setting unit 7. When the mounted device starts processing, the address signal 5, the data signal 6, and the WTC signal 1 which is one of the control signals
3 is output. When the data set by the data setting unit 7 and the data signal 5 match, the comparator 8 outputs the EQ signal 1
4 is output. At this time, since the WTC signal 13 is output from the mounted device, the TC signal 15 is output. TC
From the output of the signal 15, the register 9 latches the address signal 5 and the counter 16 adds 1 to the display data.
The contents of the register 9 and the output of the counter 16 are externally displayed on the display devices 10a and 10b.

[0010]

As described above, according to the present invention, the address and the number of times of writing the data to be monitored during the processing of the mounting device are displayed on the outside so that they can be seen at a glance. There is an effect that can be easily implemented in a short time.

[Brief description of drawings]

FIG. 1 is an embodiment of an analyzer according to the present invention.

FIG. 2 is an example of a conventional device without an analyzer according to the present invention.

[Explanation of symbols]

 4 control signal 5 address signal 6 data signal 11 buffer 12 OR gate 13 WTC signal 14 EQ signal 15 TC signal 17 BSRST signal

Claims (1)

[Claims] 1. A data setting unit capable of arbitrarily setting data to be analyzed in a mounted device, and a comparator which outputs a signal when the data set in the data setting unit and the data output from the mounted device match. , A register that can latch the address output by the attached device when needed,
A display capable of displaying output data of a register and a counter, a buffer for receiving a signal from a mounted device, an OR gate for generating a latch timing of an address output by the mounted device and a signal of a count clock of the counter. By having a counter that counts the number of times of use of the data set in the data setting unit, the address for arbitrary data and the number of times of use of arbitrary data in the series of operations of the attached device are independent of the operation of the attached device. An analyzer that can be displayed externally.