JP3158425B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a microcomputer.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a timer / counter built in a conventional microcomputer. As shown in FIG. 3, the timer / counter has an external input
Control register 18 corresponding to Tin109, frequency divider 19 corresponding to input of internal clock 109, count register 20, counter 21, display register 22, and built-in interrupt controller 23
It consists of.

In the count register 20, a count value or time is set. By inputting a microcomputer instruction from the internal bus 203 or a trigger signal to the external input Tin 109, the start bit of the control register 18 is set and the contents of the count register 20 are downloaded to the counter 21. In the counter 21, the internal clock
The counting is started only by the clock output by dividing the frequency of the _fCLK 110 in the frequency divider 19. Counter 21
When the value at becomes zero, the external output T _OUT 11
A signal is output as 1, the end bit of the display register 22 is set, and a signal is also sent to the built-in interrupt controller 23. Note that the supply source of the count clock is limited to the internal clock _fCLK .

For debugging a system using a microcomputer, an ICE (In Circuit Emulator) is generally used. Originally, instead of the microcomputer which should be placed on the board, the board is remotely operated from the evaluation chip placed in the pod of the ICE. The evaluation chip is obtained by adding a function of controlling the inside of the microcomputer from outside to a generally used microcomputer. Since the CPU is arranged away from the substrate, the load capacity of the wiring tends to increase. Therefore, even if the ICE is used for debugging a microcomputer system operating at a high frequency, the timing of a signal transmitted to the target is delayed, and it is impossible to expect normal operation of the target. ICE debugging environments for high-speed microcomputers are scarcely provided at present.

[Problems to be solved by the invention]

In the above-mentioned conventional microcomputer, the built-in timer counter uses only a clock obtained by _dividing the internal clock _fCLK 110 by the frequency divider 19 as a supply source of the count clock. The clock counting interval is always constant. For this reason, the function of the timer / counter itself is disadvantageous in that it is limited to signal output at specified time intervals and time measurement.

[Means for solving the problem]

A microcomputer according to the present invention is a microcomputer incorporating a timer / counter, which divides a predetermined internal clock and outputs it as a first count clock, and a predetermined reference address value set in advance. And compares the reference address value with the value in the program counter of the CPU at the present time, and outputs a predetermined pulse signal as a second count clock when the values match. And a clock control register that receives the first and second count clocks and selects and outputs one of the count clocks. .

〔Example〕

Next, the present invention will be described with reference to the drawings. First
FIG. 3 is a block diagram showing a timer / counter included in the first embodiment of the present invention. As shown in FIG.
The timer / counter according to the present embodiment corresponds to the internal bus 201, and includes a counter control register 1, a frequency divider 2, an address check register 3, and an address check unit 4.
, A clock control register 5 and a count register 6
, A counter 7, a display register 8, and a built-in interrupt controller 9.

In FIG. 1, a count value or time is set in a count register 6. CPU via internal bus 201
When the start bit of the counter control register 1 is set by the command sent from the external device and the external count timing input Tin101, the content of the count register 6 is downloaded to the counter 7. The counter 7 starts counting by the clock output from the clock control register 5. When the count value of the counter 7 becomes 0, the end bit of the display register 8 is set, a signal is output to the built-in interrupt controller 9, and a signal is output to the external output T _OUT 103.

In the present embodiment, the count clock supplied to the counter 7 is an internal clock.
The frequency _fCLK 102 is frequency- _divided by the frequency divider 2 and, in addition to the first clock supplied to the counter 7 at fixed time intervals, the value written in the address check register 3 and the value of A second clock selected by the clock control register 5 is prepared from among pulse signals at indefinite time intervals output from the address check unit 4 for detecting that the values match with each other. One of them is selected, output, and input to the counter 7.

Therefore, in this embodiment, it is possible to use another clock as the count clock of the built-in timer / counter in addition to the clock generated by _dividing the internal clock _fCLK of the microcomputer. Become.

Therefore, counting is performed once each time the value of the program counter reaches the value specified by the user. By reading this count value, the user can know the number of times the specified address has passed the program counter. Therefore,
By creating simple software, debugging operations such as measurement of coverage and setting of breakpoints can be performed. By applying this function to ICE, it is now possible to set breakpoints and measure coverage, which was previously performed by hardware and software in ICE, using only software, thereby reducing total cost. be able to.

In the case of a microcomputer operating at high speed, it has been difficult to provide a debugging environment using the ICE because of the problem of wiring capacity between the target and the CPU of the ICE. According to the present invention, by supporting a debugging function inside the microcomputer, it becomes possible to perform debugging such as setting a breakpoint or measuring coverage inside the microcomputer.

Next, a second embodiment of the present invention will be described. Second
The figure is a block diagram showing a timer / counter included in the second embodiment. As shown in FIG. 2, the timer / counter according to the present embodiment includes a counter control register 10, a frequency divider 11, a pulse generator 12, a clock control register 13, register
14, a counter 15, a display register 16, and a built-in interrupt controller 17.

In the count register 14, a count value or time is set. Through the command sent from the CPU and the external count timing input Tin104 via the internal bus 202,
When the start bit of the counter control register 10 is set, the contents of the count register 14 are downloaded to the counter 15. The counter 15 starts counting by a clock output from the clock control register 13. When the count value of the counter 15 becomes 0, the end bit of the display register 16 is set, a signal is output to the built-in interrupt controller 17, and a signal is output to the external output T _OUT 108.

As the timer / counter in the present embodiment, the count clock supplied to the counter 15 is an internal clock.
The _fCLK 105 is frequency- _divided by the frequency divider 11 and supplied to the counter 15 at regular time intervals. Trigger signals at indefinite time intervals obtained by detecting edges of the plurality of internal input signals Iin106 and the plurality of external input signals Oin107 input from the device are prepared as the second clock.

These first and second clocks are input to a clock control register 13, one of which is selected and output by the clock control register 13, and a counter 15
Is input to Therefore, the degree of freedom of control of the peripheral device such as an investigation of the number of operations of the peripheral device inside the microcomputer and an interruption due to the designated number of operations is expanded, and the same control can be performed by an external input signal.

〔The invention's effect〕

As described above, the present invention relates to a timer counter incorporated in a microcomputer, wherein a count clock generated by dividing an internal clock of the microcomputer is used as a count clock for a counter included in the timer counter. In addition, by providing clocks at indefinite time intervals, there is an effect that restrictions on the function of the timer / counter can be eliminated.

[Brief description of the drawings]

FIG. 1 and FIG. 2 are block diagrams of first and second embodiments of the present invention, respectively, and FIG. 3 is a block diagram of a conventional example. In the figure, 1,10... Counter control register, 2,11,19
... frequency divider, 3 ... address check register, 4 ...
Address check unit, 5,13 Clock control register, 6,14,20 Count register, 7,15,21 Counter, 8,16,22 Display register, 9,17,23 Built-in Interrupt controller.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/277 G06F 15/78

Claims (1)

(57) [Claims] 1. A microcomputer having a built-in timer / counter, a frequency divider for dividing a predetermined internal clock and outputting it as a first count clock, and holding a predetermined reference address value set in advance. An address check register to be compared with the reference address value and a value in a program counter of the CPU at the present time, and when the values match, a predetermined pulse signal is counted by a second count / counter.
An address check unit that outputs as a clock, and the first and second count clocks are input,
A clock control register for selecting and outputting any one of the count clocks, and a timer counter including: