JPH05143399A - Analyzer - Google Patents

Abstract

PURPOSE:To provide an analyzer capable of displaying the data of an optional address and the using frequency of the optional address on an external display in a series of operation of a loaded device independently of the operation of the device. CONSTITUTION:The analyzer is provided with an address setting part 7 capable of optionally setting up an address to be analyzed in a loaded device, a comparator 8 for outputting a signal when the address set up by the setting part 7 coincides with an address outputted from the loaded device, a register 9 capable of latching the data outputted from the loaded data when necessary, a display device 10a for displaying the output data of the register 9 and a counter 16, a buffer 11 for receiving the signal from the loaded device, an OR gate 12 for forming the latch timing of the data outputted from the loaded device and a counting clock signal of the counter 16, and the counter 16 for counting up the using frequency of the address set up by the setting part 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives a control signal, an address signal and a data signal from a control device of a mounted device, so that the data and the number of times of use for an arbitrarily set address during the operation of the mounted device can be obtained. It relates to an analyzer that can be displayed externally regardless of the operation of the attached device.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional apparatus without an analyzer. In the figure, 1 is a central processing unit that inputs / outputs an address signal and a data signal by a control signal when executing an instruction stored in a predetermined storage device, and 2 is a control signal output from the central processing unit. An external input / output unit 3 for exchanging data with an external device specified based on the data is stored in an address specified based on a control signal output from the central processing unit, or outputs data at a specified address. Storage device section, 4 is a control signal for controlling each device, 5 is an address signal indicating address data, 6
Is a data signal for transmitting transfer data.

Next, the operation will be described. In such a device, when the central processing unit 1 performs a series of operations, the central processing unit 1 uses the data signal 6, the address signal 5, and the control signal 4 in the storage unit 3 to perform the central processing unit 1. Write the program executed by (the data input from the external input / output unit 2). When the writing is completed and the control signal 4 for starting the processing is received from the external input / output unit 2, the central processing unit 1 based on the program data stored in the storage unit 3, the data signal 6, the address signal 5, and the control signal 4 Is used for processing. During this process, it is impossible to externally monitor the process performed by the central processing unit 1 without interrupting the process. When the series of processing is completed, the central processing unit 1 transmits the result and the completion to the outside through the external input unit 2.

[0004]

In the case of the above-mentioned device, once the processing is started, the data input / output to / from a certain address of the central processing unit and the number of times it has been used unless the processing is interrupted. Since it can be grasped, there is a problem that it is difficult and easy to debug software and hardware.

The present invention has been made in order to solve the above problems, and when a device to be mounted is executing a process, data input / output by the device to be mounted at an arbitrarily set address is set. It is also an object of the present invention to obtain an analyzer that can display the number of times the address is used regardless of the device to be mounted.

[0006]

[Means for Solving the Problems] An address setting unit that can arbitrarily set an address to be analyzed in a mounted device and a signal is output when the address set in the address setting unit and the address output by the mounted device match Equipped with a comparator, a register that can latch the data output by the attached device when necessary, a display that can display the output data of the register and counter, and a buffer for receiving the signal from the attached device. An OR gate that generates a latch timing of data output from the device and a signal of a count clock of the counter, and a counter that counts the number of times of use of the address set by the address setting unit are provided, and an arbitrary operation is performed in a series of operations of the attached device. The data for the address and the number of times of using the arbitrary address are independent of the operation of the mounted device. It was to be able to display on the outside.

[0007]

According to the present invention, the data input / output to and from the arbitrary address set by the mounted device during processing and the number of times of use are externally displayed regardless of the operation of the mounted device.

[0008]

【Example】

Example 1. FIG. 1 shows an embodiment of a storage initialization device according to the present invention. In FIG. 1, 5 and 6 are the same as in the above-mentioned conventional technique, 7 is an address setting unit that can arbitrarily set an address to be analyzed in the mounted device, and 8 is an address setting unit 7.
The comparator that outputs the EQ signal 14 when the address set in step 3 and the address signal 5 output by the attached device match, 9 indicates the data output by the attached device by the TC signal 15
Registers that are latched by the trigger of 10a, 10b are indicators that can display the output data of the register 9 and the counter 16, 11a to 11d are buffers for receiving signals from the attached device, and 12 is output by the attached device. An OR gate that generates a TC signal 15 that indicates the timing of latching the data signal 6 from the WTC signal 13 that is a data write signal and the EQ signal 14 that is output from the comparator, 1
3 is a WTC signal which is one of the control signals output when the attached device writes data to the address, and 14 is when the address set by the address setting unit 7 and the address signal 5 output by the attached device match Further, the EQ signal output from the comparator 8 is a TC signal output from the OR gate 12 when the data is loaded into the register 9 and when the counter 16 counts, 16 is a counter for counting the number of TC signals 15, 17 Is BS which is one of the control signals output from the mounted device when the power of the mounted device is applied.
This is the RST signal.

The operation of the analyzer described above will be described with reference to FIG. When power is applied to the device equipped with the analyzer, the installed device outputs the BSRST signal 17, the counter 16 is reset, and the display on the display 10a shows 0. Here, the address to be monitored is set by the address setting unit 7. When the mounted device starts processing, the address signal 5, the data signal 6, and the WTC signal 13 which is one of the control signals are output. If the address set by the address setting unit 7 and the address signal 5 match, the comparator 8 outputs E
The Q signal 14 is output. At this time, since the WTC signal 13 is output from the mounted device, the TC signal 15 is output. From the output of the TC signal 15, the data signal 6 is latched in the register 9 and 1 is added to the data in the counter 16. The contents of the register 9 and the output of the counter 16 are externally displayed on the display devices 10a and 10b.

[0010]

As described above, according to the present invention, the write data to the address to be monitored and the number of times during the processing of the mounting device are displayed externally and can be seen at a glance, so that the hardware and software can be debugged. There is an effect that can be easily implemented in a short time.

[Brief description of drawings]

FIG. 1 is an embodiment of an analyzer according to the present invention.

FIG. 2 is an example of a conventional device without an analyzer according to the present invention.

[Explanation of symbols]

 4 control signal 5 address signal 6 data signal 11 buffer 12 OR gate 13 WTC signal 14 EQ signal 15 TC signal 17 BSRST signal

Claims (1)

[Claims] 1. An address setting unit capable of arbitrarily setting an address to be analyzed in a mounted device, and a comparator which outputs a signal when the address set in the address setting unit and the address output by the mounted device match. , A register that can latch the data output by the attached device when necessary, an indicator that can display the output data of the register and counter, a buffer for receiving a signal from the attached device, and an output by the attached device By having an OR gate that generates a signal of a data latch timing and a count clock of the counter, and a counter that counts the number of times of use of the address set by the address setting unit, it is possible to perform an arbitrary address in a series of operations of the mounted device. External use of data and the number of times of use of any address regardless of the operation of the installed device An analyzer characterized by being able to be displayed on.