JPS6031062A - Pulse cycle measuring circuit - Google Patents

Abstract

PURPOSE:To make it possible to measure the cycles of two kinds of approaching input pulse signals, by providing an auxiliary counter for counting clock pulses generated during a period when two kinds of input signals are superposed, and correcting the count value of a main counter of the basis of the counted value. CONSTITUTION:When two input pulse signals A, B are inputted, output signal AB is sent out through an AND gate 6 and supplied to a microcomputer 5 and, at the same time, supplied to a latch circuit 4 as a control signal while supplied to a counter 2 as a reset signal through a delay circuit 1. The counter 2 counts clock pulses CP and resets every when an output signal is generated from the dalay circuit 1 to start new counting. A counted value Q directly before the counter 2 is reset is held to the latch circuit 4 and a value corresponding to the cycle between pulses of the output signal AB is successively held to the latch circuit 4. By correcting this counted value, the cycles of two kinds of approaching input pulse signals can be accurately measured.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a pulse period measuring circuit, and more particularly to a pulse period measuring circuit capable of measuring periods of a plurality of types of input pulse signals using a microcomputer.

Background technology In recent years, with the rapid development of microcomputers,
Microcomputers are used in control units of various devices. In this case, devices using microcomputers use pulse signals supplied from various sensors as input to execute various controls, but human pulse signals can provide various information such as rotational speed depending on their cycle. It is often expressed. Therefore, when using a microcomputer to handle various input pulse signals, it is first necessary to detect the period of the pulse signals.

FIG. 1 is a circuit diagram showing an example of a conventional pulse period measuring circuit using a microcomputer. In the figure, 1 is a delay circuit (not shown) that outputs an input signal with a slight delay using the vehicle speed supplied from a rotation sensor as a pulse period, and 2 is a clock pulse OP generated from a clock pulse oscillation circuit 3. The counter is reset by the output signal A' of the delay circuit 1.

A latch circuit 4 holds the count value of the counter 2 when the input pulse signal A is supplied. Reference numeral 5 denotes a microcomputer, which enters an interrupt mode when the input pulse signal A is supplied to the interconnected board (INT) and receives the count output signal of the latch circuit 4 via the input capacitor (IN).

In the pulse period measuring circuit configured in this manner, when the input pulse signal shown in FIG. 1 is supplied from a rotation sensor (not shown), the delay circuit 1 slightly delays this human power pulse No. 16 N. All counters 2 on the nozzle signal
is supplied to the reset input terminal of the counter 2 to reset the counter 2. Therefore, the counter 2 that counts the clock pulses CP generated from the clock oscillation circuit 3 is reset every time the pulse signal N' is supplied with the human pulse signal N.
The number of clock pulses CP generated during each cycle is counted and output.

However, since the latch circuit 4 is latch-controlled by the input pulse signal A, the latch timing of the latch circuit 4 is immediately before the reset timing of the counter 2, so one round of the input pulse signal A is latched. The count value of clock pulses during the period is held in the latch circuit 4. In addition, since the input pulse signal N is supplied as an interrupt signal to the interlaced port INT of the microcomputer 5, the microcomputer 5 enters the interrupt mode and inputs the output data of the latch circuit 4 to the interconnected port INT. Import via. The microcomputer 5 then multiplies the input data by a predetermined cycle of the clock pulse OP, thereby
The input pulse signal A is output at regular intervals. By performing such an operation every time the input signal A is supplied, the cycle of the input signal A is sequentially measured.

However, the pulse period measurement circuit with the above configuration can only perform period measurement for one type of input pulse signal, and when performing period measurement for two types of human input pulse signals, the above circuit can only perform period measurement for one type of input pulse signal. Therefore, the circuit becomes complicated and expensive.

As a solution to this problem, the method shown in Figure 2 (a)
, supplying the pulse signal AB shown in FIG. 2(c) obtained by taking out the two types of input pulse signals & and B shown in (b) through an AND gate to the pulse period measuring circuit shown in FIG. is possible.

However, if the two-man power pulse signals A and B are simply summed and supplied, a problem will occur if the two-man power pulse signals A and B are close to each other. Tsumashi, Figure 2 (a),
The 2wi input pulse signals A and B shown in (b) are logically summed to produce the pulse signal shown in FIG. 2 (c), and B is supplied to the pulse period measuring circuit shown in FIG. ,
When measuring the cycle of input pulse signals A and B, each rising time t! of input pulse signals A and B is measured. It is necessary to determine the period by sequentially measuring the time between each time point from t6 to t6, and adding the measured values between the rise time points υ of the same person's canolus signal. On the other hand, both human power pulse signals A and B are at the time point is
, when they approach each other as shown at t6, the pulse signal AB obtained by the logical sum becomes the "L"'' difference between the input pulse signals A and B as shown between time t4 and time 16 in FIG. 2(C). As a result, since the rising edge at time t5 is erased, the latch circuit 4 does not latch at time t5, and the latch circuit 4 outputs a single 'L' signal at time t6. A latched portion results.

In addition, since the counter 2 is no longer subjected to the reset process at time 15, it counts clock pulses CP between time t4 and t6, and this erroneous count value is held in the latch circuit 4 at time t6. Put it away. In this way, when the inner input signal &jB is brought close to each other, it becomes impossible to obtain latch control for the latch circuit w64 and reset control for the counter 2, making period measurement impossible.

DISCLOSURE OF THE INVENTION Accordingly, an object of the present invention is to provide an input pulse period measuring circuit that can reliably measure the periods of two types of input pulse signals generated in close proximity to each other with a simple configuration.

In order to achieve such an object, the present invention provides an auxiliary counter that counts clock pulses generated during overlapping periods for two types of input pulse signals, and uses the counted value of this auxiliary counter to By correcting the count value of the counter, the period of the coupler signals from two adjacent buildings can be accurately measured.

Therefore, in the Knolls period measuring circuit configured in this way, by adding only a few parts to the conventional pulse period measuring circuit, it is possible to measure the period of the two kinds of Knolls signals generated in close proximity. It has excellent effects that can be measured reliably.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 3 is a circuit diagram showing an embodiment of a pulse period measuring circuit according to the present invention, and the same parts as in FIG. 1 are indicated using the same symbols. In the same figure, 6 is the input pulse signal A, H
AND gate which calculates the logical product of the input pulse signals A and H and supplies the output signal AB to the delay circuit 1, the latch circuit 4, and the interconnected port INT of the microcomputer 5; 8 is a one-shot multi-novel circuit;
It is triggered by the output signal 0 of the OR gate 7, which is supplied via the OR gate 7. The output signal generated from the set output terminal Q of this one-shot multi-nobulator circuit 8 is supplied to the input port P1o of the microcomputer 5, and its pulse width is equal to the input pulse signal &,
It is set to be sufficiently long for the overlapping υ period of B. Reference numeral 10 denotes an exclusive-Jib-OR gate that inputs the input signals A and B and performs an exclusive OR, and reference numeral 11 denotes an output generated from the one-shot multi-noise ibrator circuit 8, which receives the output signal E generated from the exclusive-Jib-OR gate 10. 12 is a clock pulse OF generated from the clock oscillation circuit 3;
and the output signal F of the AND gate 11, and 13 is an auxiliary counter;
2, and supplies this counted value to the input terminal IN of the microcomputer 5, as well as the output port Pit of the microcomputer 5.
The count value is reset by the reset signal R8 generated from the reset signal R8.

14.15 is a rising edge delay circuit which inputs input pulse signals A and B and slightly delays the rising 9 portions, and its output signal is sent to the microcomputer 5.
Input port P! G+pso are respectively supplied.

In the input pulse period measuring circuit configured in this way,
For example, the first example shown in FIGS. When the second person coupler signals A and B are supplied, this first person coupler signals A and B are supplied. Since the second person coupler signals A and B are matched in the AND gate circuit 6, the output signal 5B shown in FIG. 4(C) is generated.
is sent. This output signal AB is supplied to the interlaced port INT of the microcomputer 5, and is also supplied to the latch circuit 4 as a latch control signal. Further, this output signal λB is slightly delayed in the delay circuit 1 and then supplied to the counter 2 as a reset signal.

Here, the counter 2 counts the clock pulses OP generated from the clock oscillation circuit 3, and the counter 2 counts the clock pulses OP generated from the clock oscillation circuit 3.
Each time an output signal is generated from , it is reset and starts a new counting. Then, slightly prior to resetting the counter 2, the count value Q before the resetting of the counter 2 is held in the latch circuit 4.

Since the counter 2 counts the number of clock pulses OPO between the output signal &B and the immediately preceding output signal &B, the latch circuit 4 sequentially holds values corresponding to the period between each pulse of the output signal λB. That will happen.

10,000, OR gate 7 inputs input pulse signals A and B, and as shown in FIG. is the output signal 0
It is taken out as. This output signal C triggers the one-shot multi-nobrator circuit 8 via the input signal (c), so the one-shot multi-nobrator circuit 8 is triggered at the falling edge of the output signal (c). As a result, an output with a predetermined time width T is generated as shown in FIG. 4(e), and both input pulse signals A and Plo are input to the microcomputer 5.
It is supplied as a signal indicating that a signal (which overlaps with the ``L'' period of B) is occurring.The setting time T of this platform and one-shot multi-nobulator circuit 8 is determined by the two-person power pulse signal &;
It is predetermined in advance to be sufficiently longer than the maximum period for the "L" period of H.

Next, the exclude-jib-or-gate 10 inputs both the input signals and inputs B, and removes the mismatched portion from IIHII.
An output signal E shown in FIG. 4(f) is generated. Then, this output signal E is outputted to the AND gate 11 at a low level.
As shown in FIG. 4 tgl, the meat input signals A, H are
An output signal F is generated which indicates the time difference between the input pulse signals & and B during the overlapping portion of the 1H'' period and the 1L'' period. Therefore, both human power pulse signals A and B
If the time difference Tx at the lifting platform is determined by the output signal F, the unmeasurable portion due to the overlap of the two-person force pulse signal &B can be calculated by calculation. You will be punished. The output signal F of the AND gate 11 is matched with the clock pulse CP in the AND gate 12, and its output is sent to the auxiliary counter 13.
is supplied to the clock input terminal OK. Therefore, the auxiliary counter 13 counts the clock pulses OP generated during the overlapping period Tx of the @H" period and the "L# period of the meat input signals N and B, and inputs the tt value Qx to the input terminal of the microcomputer 5. INF is supplied to the microcomputer 5, and the count value Qx of the auxiliary counter 13 is reset by the reset control signal FLS generated from the output port F'tt.
is cleared. Therefore, the OR gate 7, the one-shot multi-novel circuit 8, and the innovator 9 constitute an overlap detection section 16 that detects that the "L" periods of the flesh input signals A and B overlap. - Jib or gate 10° and gate 11 is ``'' of meat input signals A and B.
This constitutes a time difference detection section 17 that calculates the time difference between input signals A and B when the L# period overlaps. Clock pulses CP generated from the clock oscillation circuit 3 during the generation period of the output signal F of the time difference detection section 17 are counted by the auxiliary counter 13.

10,000, the rise delay circuits 14 and 15 delay the input pulse signals A and B to some extent, and then output the output signals p, /,
Input capo of microcomputer 5 as B/) P2
O+ Supplied to Pao.

Here, since the output signal AB of the AND gate 6 is supplied to the interrupt port INT of the microcomputer 5, when either or both of the input pulse signals N and B become 1L#, the microcomputer 5 interrupts the interrupt signal. Interrupt control is added to enter interrupt mode. and,
When this microcomputer 5 enters the interrupt mode, by determining the state of the input capo (Pzo + Pso), the input capo (Pzo + Pso) is in the "L" state.
By determining P3o, the type of input pulse signal to which the interrupt has been added is determined. Once the type of the input pulse signal is determined in this way, the type of the human pulse signal is set as the input number N1, the count value represented by the output signal of the latch circuit 4 is set as Q, and is stored in the internal memory as shown in FIG. 5, for example. are written sequentially. In the memory, input type is stored in one set and count value Q is stored in the other. Each time data is written to address OO, the address of this memory is shifted, and the oldest data is
By being flowed, a predetermined number of data are always held based on the newest data. For example, the input pulse signal A shown in FIG.
, B are supplied, the output value Q of the latch circuit 4 that holds the counted value of the clock pulse CP between each pulse of the output signal AB shown in FIG.
or B) will be held in the memory as shown in FIG.

The various data held in the memory in this way are obtained by taking two adjacent count values Q of the same manual type from the newer address side, and calculating the sum of the count values Q between them to determine the period of the clock pulse CP. The period can be found by multiplying by .

For example, the period To of the input pulse signal A shown in FIG. 6(a)
, it is determined by multiplying the sum of the count values Ql and Q2 held at addresses 01 and 02 by the period of the clock pulse CP. While sequentially executing the process, each person's callus signal input and B cycles are measured and output.

Here, the above explanation assumes that the 1L'' periods of the input pulse signals A and B do not overlap each other.

In the case of a violet signal, the rising edge of the input pulse signal shown in FIG. It becomes impossible to measure the period between the pulse signals A and B. For this,
In the case of such conditions, special processing is added to the period calculation. The process will be explained below using the flowchart shown in FIG.

When the microcomputer 5 enters the interrupt mode, it moves to step S1 shown in FIG.
Determine the state of O. Here, if the output signal of the one-shot multi-nobrator 8 supplied to the input capo PTO is "H#", it means that the "L1 period of the input pulse signal input and B overlaps with each other". It shows. If the determination in step 81 is NO, the process moves to step S2 and the state of the input card (Pro) is determined. Here, the condition for causing an interrupt is when either or both of the input pulse signals A and B are input at the same time. Therefore, if the determination in step S2 is NO, it means that the input pulse signal B has been input), and B is taken in as the input type in step S3. Further, if the determination in step 83 is YES, then in step 84, A is input as the input type.

Next, in step 85, the interrupt state is determined, and when the interrupt is released, the process moves to step S6.

In step S6, the output signal of the latch circuit 4 is stored as the count value Qo and then returned, so that the process of loading various data into the memory in a state where normal overlaps do not occur is performed. is completed.

Next, if the #L'' periods of the input pulse signals A and H overlap, the determination in step S1 becomes YES and the process moves to step S. (Capo) Determine the state of pro, and if the determination result is NO, set No = B, N, = person in step SS to indicate that input pulse signal B is leading. .

Further, if the determination in step S7 is YF3, the process moves to step S9 and the state of the input port pea is determined. If the determination result in step S9 is YES, the process returns to step S7 and waits for either input port P2G or PSO to become "H". Judgment is no
The process moves to step 810 where No-&, N1=B.
Set. Next, in step 811, it is determined whether to cancel the interrupt mode, and if the determination in step Stt becomes No, the process moves to step Sl. In step Sl, Qo is the count value Q of the auxiliary counter 13.
Set x and set b Ql to L - Qx. In other words, the number L-Qx of clock pulses OP generated between the input pulse signals & and B shown as Tx in FIG. 4 1al is determined and stored in j' and Qx.

Each input type and count value taken in in this way is summed with respect to the count value of the same adjacent manual type, and based on this, the summation is calculated in relation to the predetermined period of the clock pulse CP. The period of each human power pulse signal A, H is determined. In this case, in recent years, microcomputers have been created that also incorporate two counters, a latch circuit, a clock oscillation circuit, and a delay circuit, and when such a one-chip microcomputer is used, The advantage is that only a few circuit parts need to be added, which greatly simplifies the process.

As explained above, although the pulse period measurement circuit according to the present invention has a simple configuration, it can be used for two types of human pulse signals that are supplied partially overlapping each other. It has an excellent effect of being able to reliably measure the period.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional pulse period measurement circuit, FIGS. 2(a) to (c) are waveform diagrams illustrating conventional examples of period measurement for two types of human pulse signals, and FIG. The figure is a circuit diagram showing an embodiment of the pulse period measuring circuit according to the present invention, and Figures 4 (a) to (g) and Figures 6 (,) to (c) explain the operation of the circuit shown in Figure 3. 5 and 7 are diagrams showing the data holding state of the microcomputer shown in FIG. 3, and FIG. 8 is a flowchart showing the operation of the circuit shown in FIG. 3. DESCRIPTION OF SYMBOLS 1... Delay circuit, 2... Counter, 3... Clock oscillation circuit, 4... Launch circuit, 5... Microcomputer, 6, 11.12... AND gate,
7... OR gate, 8... One-shot multi-novelizer circuit, 9... Inverter, 10... Excludor gate, 13... Auxiliary counter,
14.15... Startup delay circuit, 16... Overlapping shift detection section, 17... Time difference detection circuit. Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] (1) A first gate circuit that performs a logical sum on multiple types of human input pulse signals to be measured, and a main counter that counts clock pulses and is reset by a signal obtained by slightly delaying the output signal of the first gate circuit. , a latch circuit that holds the counted value of the main counter immediately before its reset, an overlapping detection section that detects overlapping occurrences of the human power pulse signal to be measured and generates an output, and this overlapping circuit. ) a time difference detection unit that generates a pulse according to the time difference of the human power pulse signal to be measured only when the output of the detection unit is generated; and an auxiliary counter that counts the number of clock pulses generated during the output generation period of the time difference detection unit; , a microcomputer that inputs the output value of the latch circuit and the count value of the auxiliary counter by using the output signal of the first gate circuit as an interrupt control signal, and the microcomputer receives the output value of the latch circuit and the count value of the auxiliary counter as an interrupt control signal, and the microcomputer receives the output value of the latch circuit and the count value of the auxiliary counter. The type of the input pulse signal is determined by monitoring the pulse signal, and the determined type and the output signal of the latch circuit are sequentially stored as a set, and when the shape detection section generates an output, the output value of the latch circuit is The value obtained by subtracting the count value of the auxiliary counter from the input pulse signal type is set as a set, and the count value of the auxiliary counter and the type of input pulse signal are stored as a set. A new pulse period measuring circuit is characterized in that it calculates and outputs the period of each input pulse signal from the sum of count values of the same type and the clock pulse period.