JPS63169826A - Counter circuit - Google Patents

Abstract

PURPOSE:To relieve the software load of a CPU by using a reset signal produced by retarding a timing signal generated by the edge detection of a 1st input signal so as to reset a counter, thereby eliminating the need for the subtraction processing of the CPU in measuring the pulse width or the pulse period of the 1st input signal. CONSTITUTION:A binary up-counter 2 repeats up-count successively by using an input signal phi. An edge detection circuit 1 detects the edge of an input signal (x) and its timing signal L latches a saving latch circuit 3 by counting of the counter 2. Simultaneously, an interruption generating circuit 5 is started. Moreover, a detection circuit 1 sends a signal L to a delay circuit 7 after edge detection and the delay circuit 7 uses a reset signal R to initialize the counter 2. A CPU 6 uses the circuit 5 to recognize the edge detection and the execution of latch, reads the value of the circuit 3 through a data bus 4 to recognize the pulse period or pulse width of the signal (x).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter circuit that accurately measures the pulse width or pulse period of an input signal.

[Conventional technology]

A conventional counter circuit is shown in FIG. In Figure 3,
1 is an edge detection circuit that detects the rise or fall of the pulse of the first input signal X, or the rise and fall of the pulse; 2
is a binary up counter that is incremented by the second input signal φ, 3 is a latch circuit for saving and holding the value of the binary up counter 2 at the pulse edge of the input signal X detected by the edge detection circuit 1, and 4 is a saving latch circuit. A data bus 5 sends the data latched in the latch circuit 3 to the CPU 6, and an interrupt generating circuit 5 notifies the CPU 6 that the data has been launched.

Next, the operation will be explained. binary up counter 2
is constantly incremented by the input signal φ (see FIG. 4(a)). The edge detection circuit 1 detects the edge of the input signal X at the rise or fall of the pulse of the input signal X, or the rise and fall of the pulse of the input signal X, and latches the value of the pinary up counter 2 in the evacuation launch circuit 3 at this timing.

At the same time, in order to notify the CPU 6 that it has been latched,
Activate the interrupt generation circuit 5.

The CPU 6 connects to the backup latch circuit 3 via the data bus 4.
By reading the value of , the time at which the edge of the input signal X occurs can be known as the value of the binary up counter 2. Therefore, when measuring the time from the rise to the rise of the pulse of the input signal X, t3-tl (Figure 4(b),
Figure 4 (see +31), when measuring the time from fall to fall, t4-t2 (Figure 4 (C), Figure 4 (e)
) is calculated and obtained by the CPU 6. Furthermore, if the width of the pulse of input signal X is "1", t2-tl (fourth
(see Figure cd), Figure 4 (e)), if the width is "0", t
3-t2 (see FIGS. 4(d) and 4(e)) can be similarly calculated by the CPU 6. However, t
l, t2. t3 and t4 are sequential values of the evacuation latch circuit 3 which detects and latches the pulse edge.

[Problem that the invention seeks to solve]

Since the conventional counter circuit for measuring pulse width or pulse period is configured as described above, it is necessary to perform subtraction processing in the CPU 6 when measuring either pulse width or pulse period, which causes problems in terms of software load. Ta.

The present invention has been made in view of these points, and its purpose is to provide a counter circuit that can measure the pulse period or pulse width of the input signal X without performing subtraction processing in the CPU 6. It's about getting.

[Means for solving problems]

In order to achieve such an object, the present invention provides an edge detection circuit that detects the rising edge or falling edge, or the rising edge and the falling edge, of a first input signal and outputs a timing signal; a counter that counts the number of edges; a save latch circuit that saves the count value held in the counter when an edge of the first input signal is detected; a delay circuit that resets the counter with a reset signal generated by inputting a timing signal; This system includes an interrupt generation circuit that is activated by a detection circuit and generates an interrupt signal, a CPU that performs processing in response to the interrupt signal, and a data bus that transfers the value of the save latch circuit.

[Effect]

In the counter circuit according to the present invention, there is no need for subtraction by the CPU in measuring the pulse width or pulse period.

〔Example〕

An embodiment of a counter circuit according to the present invention is shown in FIG. In FIG. 1, 1 is an edge detection circuit that detects the rise or fall of the first input signal X, or the rise and fall of the first input signal counter, 3
4 is a save launch circuit that saves and holds the value of the binary up counter 2 according to a timing signal output from the edge detection circuit 1 when an edge of the input signal X is detected;
is a data bus for sending the value latched by the evacuation launch circuit 3 to the CPU 6, 5 is an interrupt generation circuit that notifies the CPU 6 of the edge detection timing, and 7 is an input signal X.
This is a delay circuit that generates a reset signal R for resetting the binary up counter 2 when an edge of is detected.

Next, the operation will be explained. binary up counter 2
is constantly incremented by the input signal φ. The edge detection circuit 1 is a latch circuit for detecting the edges of the input signal X at the rising edge or falling edge or the rising edge and the falling edge of the pulse of the input signal Latch to 3. At the same time, the interrupt generation circuit 5 is activated to notify the CPU 6 that the count value has been latched.

Further, after detecting an edge, the edge detection circuit 1 sends an edge detection signal, that is, a timing signal, to the delay circuit 7. This delay circuit 7 generates a reset signal R for resetting the binary up counter 2. Therefore, after the edge is detected, the binary up counter 2 is initialized to "0".

The CPU 6 learns from the interrupt generation circuit 5 that the edge has been detected and launch has been performed, and then activates the evacuation latch circuit 3.
By reading the value of through the data bus 4, the pulse period or pulse width of the input signal X can be known.

FIG. 2 shows how the period from the rise to the rise of the pulse of the input signal X is measured. In FIG. 2, a rising edge of the input signal X shown in FIG. 2('b) occurs immediately after time t1 shown in FIG. 2(a), this edge is detected by the edge detection circuit 1, and the second A timing signal shown in Fig. 2 (C1) is generated. This timing signal causes the count value of the binary up counter 2, that is, the time tl (Fig. 2 (e)
)) is held in the evacuation latch circuit 3, and the CPU
6, and the CPU 6 reads the count value via the data bus 4. Further, the delay circuit 7 generates a reset signal R shown in FIG. 2(d) based on the timing signal, thereby resetting the binary up counter 2 as shown in FIG. 2(a).

Next, a second latch is performed at time t2. The operation in this case is similar to the first latch operation at time t1, so the explanation thereof will be omitted. In this way, the pulse period from rise to rise of the input signal X can be measured only at time t2, regardless of time t1.

In the above embodiment, the operation was explained from the rising edge to the rising edge of the input signal It becomes an action.

〔Effect of the invention〕

As explained above, the present invention resets the pulse width or pulse period of the first input signal by resetting the counter with the reset signal generated by delaying the timing signal generated by edge detection of the first input signal. Since there is no need for CPU subtraction processing when measuring , there is an effect that the software load on the CPU is reduced.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing one embodiment of a counter circuit according to the present invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a system diagram showing a conventional counter circuit, and FIG.
The figure is a time chart for explaining the operation. l...Edge detection circuit, 2...Binary up counter, 3...Evacuation launch circuit, 4...Data bus, 5...Interrupt generation circuit, 6...-CPU, 7...
Evacuation circuit.

Claims (1)

[Claims] (1) An edge detection circuit that detects a rising edge or a falling edge, or a rising edge and a falling edge, of a first input signal and outputs a timing signal; a counter that measures the number of pulses of a second input signal; a save latch circuit that saves the count value held in the counter when an edge of the input signal is detected; a delay circuit that resets the counter with a reset signal generated by inputting the timing signal; and an interrupt activated by the edge detection circuit. An interrupt generation circuit that generates a signal, and a CP that processes according to the interrupt signal.
1. A counter circuit comprising: a data bus for transferring a value of the save latch circuit;