JPS63174131A - Interruption controller - Google Patents

Abstract

PURPOSE:To respond with equal priority to plural interruption requests, by providing a shift pulse generation circuit, and setting the leading of plural outputting pulses as the sampling timings of corresponding interruption inputs. CONSTITUTION:The leading of the pulses p1, p2, p3, and p4 outputted from the shift pulse generation circuit 1 are set as the sampling timings of the corresponding interruption inputs. And when interruption input signals i1 and i3 are inputted, and first leading transition occurs in the p3, an OR circuit 6 asserts a common interruption signal (i) by asserting the output of a q3 by an FF4, then, all of the shift pulses are invalidated. Next, an interruption processing on the interruption i3 is performed, and when it is completed, all of the shift pulses are validated again. And next, the interruption processing is performed on the interruption i1 with a similar procedure. In this case, it is likely that the i1 is processed first based on the phase state of the shift pulse, therefore, it is possible to set the priority of the interruption i1, i2, i3, and i4 on equal terms.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an interrupt control device that responds to interrupt requests from external devices to a microprocessor.

(Prior Art) Conventionally, when multiple interrupt signals are placed at the same level, the signal lines for the interrupts are input to a priority encoder,
The common signal was given to a microprocessor and the like. In this case, when multiple interrupts are input at the same time,
An interrupt signal is enabled when it is connected to the encoder as a higher priority in order of priority.In other words, even if multiple interrupt elements appear to be at the same level to the microprocessor, their priorities are actually determined in more detail. This is inconvenient for a system that handles multiple interrupt elements that are located at the same level, have approximately the same probability of occurrence, and have the same interrupt processing.

〔the purpose〕

The present invention uses a time-sharing method to divide each interrupt signal into a microprocessor with equal priority for a plurality of interrupt elements whose probability of occurrence at the same level is almost constant when viewed from the microprocessor, and whose interrupt processing is the same. This ensures that the data is input to the processor.

〔Example〕

The present invention will be explained below based on preferred embodiments.

FIG. 1 shows an embodiment of the present invention, in which four interrupt signals are processed. 1 is a shift pulse generation circuit pi, p
2. p3. It outputs four types of pulses p4.

2, 3, and 4.5 are flip-flops (F/F) respectively.
When the CLR input is low, the Q output is high, and the Q output becomes low only when the CLR input is high and a falling pulse is input to CK. 6 is a four-input negative logic OR gate, and 7 is a priority order encoder. (S line it,
i2. i3. i4 is an interrupt input signal, ql, q
2. q3. q4 is the Q output of F/F2, 3, 4.5, respectively, and i is the interrupt input signal it, i2. i3. i4 is the common interrupt signal, C is the interrupt input signal it, i2゜i3.
It is a code signal for distinguishing i4 and has a 2-bit configuration.

Next, the operation shown in FIG. 1 will be explained together with FIG. 2 which is an operation timing diagram. Four types of pulses pt, p2°p3. are output from the shift pulse generation circuit 1. p4 is as shown in FIG. 2, and the rising edge of each pulse is the sampling timing of the corresponding interrupt input. In the example in Figure 2, 11
and 13 interrupts are input almost simultaneously (1)
.

Looking at the respective shift pulses pi and p3, p3 is the first to undergo a rising transition after the interrupts if and i3 are input.

Due to the rising transition of p3, F/F4 asserts the q3 output (2). By asserting q3, OR circuit 6
asserts the common interrupt signal i (3). This disables all shift pulses.

When the processing routine for interrupt i3 is activated and the interrupt factor is canceled, q3 is negated (4). q
3 also negates the common interrupt signal i, and all shift pulses become valid again (5).

Interrupt 11 that has been waiting for processing until now is the common interrupt signal i
The signal is sampled at the first rising transition of pl after negation of ql, and the common interrupt signal i is asserted to start the interrupt processing (b).

In the example of FIG. 2, the interrupts input at approximately the same time
, the interrupt IA filling was performed first for interrupt i3, but depending on the phase state of shift pulses p1 to p4, there is a possibility that interrupt processing for 11 is performed first, so the overall If you look at interrupt it, i2. i3. i4
Both have the same probability that their own interrupt processing will be performed first. Therefore, interrupts il, i2°i3. All i4s have the same priority.

This interrupt control circuit is effective for systems that need to handle multiple interrupts with the same priority.

(Effects) As described above, according to the present invention, it is possible to respond to a plurality of interrupt requests with equal priority.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an interrupt control circuit with four interrupt elements, and Fig. 2 is an operation timing diagram of the interrupt control circuit, where 1 is a shift pulse generation circuit, 2, 3, and 4.5 are flip-flops, and 7 is a shift pulse generation circuit. It is a priority encoder.

Claims (1)

[Claims] An interrupt control device characterized in that an absolute priority is not given to interrupts input at the same level, and each interrupt signal is given to a microprocessor in a time-sharing manner.