JPH0561813A - Data transfer system - Google Patents

Abstract

PURPOSE:To speed up a data transfer processing by permitting a DMA controller to search/extract all storage circuits storing input data when the DMA controller is DMA-started for once so as to transfer data in order. CONSTITUTION:An interruption signal 33 informs a control processor 1 that input data is stored in either one of the storage circuits 10-13, and the control processor 1 starts the DMA controller. The DMA controller 3 extracts (searches) all the storage circuits 10-13 storing input data. All the extracted storage circuits 10-13 sequentially transfer input data which the circuits store to a memory 2. Thus, DMA start by the control processor 1 can be reduced to one-time. Thus, the search time, the DMA start time and the transfer destination address calculation time of the storage circuits 10-13 storing effective data can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system,
In particular, the present invention relates to a data transfer system of a data processing device which is connected to a plurality of external devices and controls data transferred from the external devices by a DMA controller.

[0002]

2. Description of the Related Art A conventional data transfer system has a plurality of storage circuits for temporarily storing data from the outside, and when performing DMA transfer between the storage circuits and an internal memory, the order of data transfer is set. To determine, the control processor searches the memory circuit storing valid data and, based on the result, instructs the DMA controller to transfer the data to the specific memory circuit. Therefore, one DMA transfer is basically a data transfer between one memory circuit and a memory, and when it is desired to perform a DMA transfer from a plurality of memory circuits to the memory, the DMA transfer is performed by the number of the memory circuits. Must be done at that time, in the control processor, DM
It is necessary to calculate the transfer destination address before activating A.

[0003]

In the above-mentioned conventional data transfer method, when it is desired to perform a DMA transfer from a plurality of storage circuits to a memory, it is necessary to perform the DMA transfer by the number of the storage circuits. It has a drawback that it takes time to search a circuit, set a DMA controller, and perform a DMA start-up process, resulting in deterioration of performance.

[0004]

A data transfer system of a first invention is a control processor, a memory accessible by the control processor, a plurality of storage circuits for temporarily storing data inputted from the outside, and DMA for controlling data transfer between a memory and a plurality of said memory circuits
In a data transfer system of a data processing device including a controller, (A) first control means for causing the control processor to recognize that externally input data is stored in at least one of the storage circuits; In order to transfer the data from the memory circuit storing the input data to the memory, the control processor recognizing that the input data has been stored by the first control means outputs the D
Second control means for activating the MA controller, and (C)
Search means for searching the memory circuit in which data from the outside is stored in the DMA controller;
(D) When the data transfer from one of the memory circuits to the memory is completed, the data is continuously transferred from the other memory circuit, which is designated by the search means and stores external data, to the memory. And a third control means for carrying out the above, and successively transferring the data stored in the plurality of storage circuits to the memory.

In the data transfer system of the second invention, a control processor, a memory accessible by the control processor, a plurality of memory circuits for temporarily storing data inputted from the outside, the memory and a plurality of memory circuits. In a data transfer method of a data processing device including a DMA controller for controlling data transfer between the storage circuits,
(A) Notifying the control processor that externally input data is stored in at least one of the storage circuits, and (B) notifying the control processor from the storage circuit in which the input data is stored. Activating the DMA controller to transfer data to memory,
(C) The activated DMA controller extracts all the storage circuits in which input data is stored at that time, and (D) the input stored in each of the extracted storage circuits. The data is sequentially transferred to the memory under the control of the DMA controller.

Further, the data transfer system of the third invention is
A control processor, a memory accessible by the control processor, a plurality of storage circuits for temporarily storing data input from the outside, and a DMA controller for controlling data transfer between the memory and the plurality of storage circuits. In a data transfer system of a data processing device including: (A) an interrupt signal generation circuit for notifying the control processor with an interrupt signal that externally input data is stored in at least one of the storage circuits;
Input data is stored at that time by a DMA activation circuit that activates the DMA controller from the control processor that has detected an interrupt signal from the interrupt signal generation circuit, and (C) the DMA controller activated from the DMA activation circuit. The input data stored in each of the search circuits for extracting all the storage circuits that are stored, and (D) all the storage circuits that are extracted by the search circuit, are sequentially transferred to the memory. And an output enable signal generation circuit of the DMA controller.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data transfer system of the present invention. As shown in FIG. 1, the data processing apparatus of this embodiment has an address bus 4 which is an internal bus.
And a data bus 5, and a control processor 1, a memory 2, a DMA controller 3 and a FIF are provided on both buses.
Four storage circuits 10, 11, 12, 13 for temporarily storing external data are connected by O.

The control processor 1 can access the memory 2 via the address bus 4 and the data bus 5, and the memory circuits 10, 11, 12,
13 can also transfer data to the memory 2 via the address bus 4 and the data bus 5 under the control of the DMA controller 3. It is necessary to arbitrate the internal bus between the control processor 1 and the DMA controller 3. However, this arbitration circuit is not shown in FIG. 1 for simplicity. The DMA controller 3 outputs a bus request signal (not shown) to the arbitration circuit, receives a bus permission signal (not shown) from the arbitration circuit, and uses the address bus 4 and the data bus 5.

On the other hand, the memory circuits 10, 11, 12, 13
Are data valid signals 100, 110, 120,
It outputs 130 and sends it to the DMA controller 3.
The data valid signals 100, 110, 120, 130 are data stored in the storage circuits 10, 11, 12, 1 respectively.
3 is set to ON when it is stored in the memory 3, all the stored data is transferred to the memory 2, and when it becomes empty, it is reset to OFF.

Data valid signals 100, 110, 1
20 and 130 are input to the OR gate 34 having four inputs and become the interrupt signal 33, which is notified to the control processor 1. That is, the four storage circuits 10, 11, 12, 1
The control processor 1 confirms that at least one of the data stored in 3 stores the data transferred from the outside.
Can be known by the interrupt signal 33. The control processor 1 uses this interrupt signal 33 as a trigger for DM
The transfer destination memory address is set in the A controller 3 and the DMA is activated.

On the other hand, the DMA controller 3 internally has an address register 30 which holds the start address of the transfer destination memory, and data valid signals 100, 110, 120 and 13.
Storage circuit 10, 1 storing valid data by 0
A search circuit 31 for searching 1, 12, 13 and output enable signals 320, 321, 3 for any of the memory circuits 10, 11, 12, 13 according to the result of the search circuit 31.
Output enable signal generation circuit 3 for generating 22, 323
Includes 2. Then, the address register 30 is
It has a function of automatically increasing the held address every time data is transferred by MA transfer.

FIG. 2 shows the DMA controller 3 of this embodiment.
3 is a circuit diagram showing an example of a search circuit 31 in FIG. As shown in FIG. 2, the search circuit 31 realizes a priority encoder with enable, as can be seen from the truth table of the search circuit 31. Then, the search of the storage circuits 10, 11, 12, and 13 is performed in the order of the storage circuit 10, the storage circuit 11, the storage circuit 12, and the storage circuit 13 from the highest one according to the priority.

That is, the output signal 31 of the search circuit 31.
2 is a signal indicating that the DMA is being activated, and when the negative value of the output Q of the flip-flop 50 is "0" and at least one of the data valid signals 100, 110, 120, 130 is "1". It becomes “1” and is sent to the output enable signal generation circuit 32 to be stored in the storage circuits 10, 11, 1.
It becomes the output condition of the output enable signal for 2 and 13. Further, the output signals 310 and 311 of the search circuit 31
Is the output of the priority encoder that receives the data valid signals 100, 110, 120, and 130, and is sent to the output enable signal generating circuit 32 to be stored in the storage circuit 1.
Used as 0, 11, 12, 13 select signals.

On the other hand, the flip-flop 50 is an RS type flip-flop, and when it is on, it instructs the DMA transfer and activates the DMA controller 3. As can be seen from the truth table of the RS type flip-flop 50, the flip-flop 50 is turned on by the instruction of the control processor 1, and turned off by the reset signal due to the fall of the output signal 312. .. Also,
The flip-flop 51 is a D-type flip-flop, and as can be seen from the truth table of the D-type flip-flop 51, forms a trailing edge differentiating circuit that generates a reset signal for the flip-flop 50 together with the NOR gate 52. There is.

FIG. 3 shows the DMA controller 3 of this embodiment.
3 is a circuit diagram showing an example of an output enable signal generation circuit 32 in FIG. As shown in FIG. 3, the output enable signal generation circuit 32 includes the transfer source storage circuits 10 and 1 of the DMA transfer.
Output signals 320, 3 designating any one of 1, 12, 13
21, 322, 323, which operates according to the truth table of the decoder 60, so that the input signals 310, 311 from the search circuit 31 are "0", "0".
When the input signals 310 and 311 are "0" and "1", the output enable signal 320 for designating the memory circuit 10 is set to "1", and the output enable signal 321 for designating the memory circuit 11 is set to "1". , Input signal 31
When 0 and 311 are “1” and “0”, the memory circuit 12
When the input signals 310 and 311 are "1" and "1", the output enable signal 323 designating the memory circuit 13 is set to "1".

FIG. 4 shows the DMA controller 3 of this embodiment.
3 is a time chart showing an example of the operation of FIG. The DMA transfer operation in the case where the data transferred from the outside is stored in the memory circuits 11 and 13 of the four memory circuits 10, 11, 12, and 13 will be described with reference to FIG.

First, since valid data is stored in the memory circuits 11 and 13, the data valid signals 110 and 130 are stored.
Respectively become "1" and are notified to the control processor 1 through the interrupt signal 33. And the control processor 1
When the valid data is stored in any of the memory circuits 10, 11, 12, and 13, the flip-flop 50 is set to “1” after setting the address register 30 to the DMA controller 30. Set to DMA
Start up. Therefore, since "0" is input to the EN terminal of the search circuit 31, the search circuit 31 is activated. Then, the output signal 312 of the search circuit 31 becomes "1", and the output signals 310, 311 are the data valid signals 100, 110, 120, 130, respectively, "0", "1", "0", "1". So, "0",
It becomes "1".

Further, the output enable signal generating circuit 32
Receives "0" and "1" of the input signals 310 and 311 and outputs "1" only to the output signal D1 of the decoder 60, and outputs "1" of the data valid signal 110 and the input signal 312.
Of "1", the memory circuit output enable timing signal, and the input signal D1.
Since only 1 supplies the timing signal of the memory circuit 11, DMA transfer is performed from the memory circuit 11 to the memory 2.

When all the data stored in the memory circuit 11 has been transferred to the memory 2, the data valid signal 11
Although 0 is reset from “1” to “0”, since the data valid signal 130 continues to be “1”, the output signal 312 of the search circuit 31 holds the state of “1”,
Output signal 3 of search circuit 31 without ending DMA transfer
10, 311 changes to "1", "1". Therefore,
The output of the decoder 60 is "1" only in D3, and only the output enable signal 323 supplies the timing signal of the memory circuit 13 this time.
A DMA transfer will be performed for.

In this way, when all the data stored in the memory circuit 13 has been transferred to the memory 2, the data valid signal 130 is reset from "1" to "0", and the data valid signals 100 and 110 are generated. , 120, 130
Are all "0", the output signal 3 of the search circuit 31
12 becomes "0", and one clock after receiving this, the flip-flop 50 is reset and the DMA transfer is completed.

In this embodiment, the signal 312 is "1".
During the DMA transfer, the data valid signals 100, 11
Since 0, 120, and 130 must not be changed indiscriminately, when DMA transfer is not in progress, or when the memory circuit 10,
The data valid signals 100, 110, 120, and 130 are changed at the timing when the transfer of 11, 12, and 13 is completed.

[0023]

As described above, according to the data transfer method of the present invention, when DMA transfer is performed from a plurality of storage circuits for storing data from the outside to the internal memory, the DMA transfer can be performed only once by starting the DMA. At this point, all memory circuits storing valid data are searched and the data is transferred in order. Therefore, the DMA is divided into plural times by the control processor.
The processing time required for start-up, that is, the search time of the memory circuit storing valid data, the DMA start-up time, the transfer destination address calculation time, and the like can be reduced, so that the data transfer processing can be speeded up. It has the effect that

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer system of the present invention.

FIG. 2 is a circuit diagram showing an example of a search circuit 31 and its peripheral circuits in the DMA controller 3 of this embodiment.

FIG. 3 is a circuit diagram showing an example of an output enable signal generation circuit 32 in the DMA controller 3 of this embodiment.

FIG. 4 is a time chart showing an example of the operation of the DMA controller 3 of this embodiment.

[Explanation of symbols]

1 Control Processor 2 Memory 3 DMA Controller 4 Address Bus 5 Data Bus 10, 11, 12, 13 Storage Circuit 30 Address Register 31 Search Circuit 32 Output Enable Signal Generation Circuit 33 Interrupt Signal 34 OR Gate 50, 51 Flip Flop 60 Decoder 100, 110, 120, 130, 310, 311 and 3
12,320,321,322,323 signal

Claims (3)

[Claims] 1. A control processor, a memory accessible by the control processor, a plurality of storage circuits for temporarily storing data input from the outside, and data transfer performed between the memory and the plurality of storage circuits. In a data transfer system of a data processing device including a DMA controller for controlling, (A) first control means for causing the control processor to recognize that externally input data is stored in at least one of the storage circuits; (B) In order to transfer data from the memory circuit storing input data to the memory, the DMA controller is activated from the control processor that has recognized that the input data is stored by the first control means. Second control means, and (C) before the DMA controller stores data from the outside (D) another search means for searching the storage circuit, and (D) storing the external data specified by the search means when the data transfer from one of the storage circuits to the memory is completed. A third control means for continuously transferring data from the storage circuit to the memory, and the data stored in the plurality of storage circuits are sequentially transferred to the memory. 2. A control processor, a memory accessible by the control processor, a plurality of storage circuits for temporarily storing data input from the outside, and data transfer performed between the memory and the plurality of storage circuits. In a data transfer method of a data processing device including a controlling DMA controller, (A) notifying the control processor that externally input data is stored in at least one of the memory circuits, and (B) notifying The control processor activates the DMA controller to transfer data from the memory circuit storing input data to the memory, and (C) the activated DMA controller stores the input data at that time. All the memory circuits that are present, (D) all the memory circuits that have been extracted Transferred sequentially to the memory input data being paid by the control of the DMA controller, the data transfer method, characterized in that. 3. A control processor, a memory accessible by the control processor, a plurality of storage circuits for temporarily storing data input from the outside, and data transfer performed between the memory and the plurality of storage circuits. In a data transfer system of a data processing device including a controlling DMA controller, (A) an interrupt signal generation circuit for notifying the control processor by an interrupt signal that externally input data is stored in at least one of the storage circuits. (B) a DMA activation circuit that activates the DMA controller from the control processor that has detected an interrupt signal from the interrupt signal generation circuit, and (C) the DMA controller activated from the DMA activation circuit, Search to extract all the memory circuits that store input data in A circuit, and (D) an output enable signal generation circuit of the DMA controller that sequentially transfers the input data stored in each of the storage circuits extracted by the search circuit to the memory. A data transfer method comprising: