JPH07182272A - Dma controller circuit - Google Patents

Abstract

PURPOSE:To attain DMA transfer operation without stopping the processing of a CPU and respective DMA controller circuits and to improve processing speed. CONSTITUTION:When a DMA transfer request is generated at the time of accessing from a CPU 4 to another device, a transfer request arbitrating circuit 11 outputs a wait request signal to the CPU 4 and inserts wait for DMA transfer into the machine cycle of the CPU 4. When the DMA transfer inserting cycle is started, a data bus control circuit 15 selects the CPU 4 and an I/O data register 3 in order in accordance with a signal from a memory control circuit 2 and connects the selected unit to a memory 5. At the time of starting the DMA transfer inserting cycle, an address control circuit 16 selects an address signal from the CPU 4 and a DMA address signal from an address calculating circuit 12 in order in accordance with a signal from the circuit 2 and sends the selected unit to the memory 5. The circuit 2 gives instruction on the switching timing of data and address signals at the time of starting the DMA transfer inserting cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller circuit, and more particularly to a DMA transfer operation for a memory device by a DMA (Direct Memory Access) controller circuit.

[0002]

2. Description of the Related Art Conventionally, in a DMA controller circuit, when the DMA controller circuit performs a DMA transfer, a hold signal is output to the CPU, and the operation of the CPU is temporarily stopped before the memory access. .

That is, when the CPU is operating,
When the DMA controller circuit operates, the address and data from the CPU collide with the address and data from the DMA controller circuit on the address data bus.
By outputting a hold signal from the DMA controller circuit to the CPU, the operation of the CPU is temporarily stopped before the DM
A transfer is performed.

In the technique disclosed in Japanese Patent Laid-Open No. 59-214931, the data set time in the I / O device is added to the CPU mode wait time during the DMA control by the DMA controller circuit to form the wait signal, and each I There has been proposed a method for achieving the most efficient synchronization with the / O device.

Also in the above technique, since the DMA controller circuit is connected to the same address bus as the CPU, the operation of the CPU must be temporarily stopped by outputting a hold signal when performing the DMA transfer. .

[0006]

In the above-described conventional memory access contention arbitration method, since the CPU and the DMA controller circuit generate hold signals to occupy the address data bus, the DMA controller circuit is used. There is a problem that the CPU is put in the hold state and the operation is temporarily stopped during the DMA transfer control.

Further, when the memory is accessed by the CPU, the DMA controller circuit is in the hold state, and the DMA
Since the DMA transfer by the controller circuit is stopped, D
There is a problem that the MA transfer takes time.

When the operation of the CPU is temporarily stopped by the hold signal, when the CPU is performing a certain process, it does not enter the stopped state until the process is completed, which further lengthens the DMA transfer time.

Therefore, an object of the present invention is to solve the above problems and to perform DMA transfer without stopping the processing of each of the CPU and the DMA controller circuit, and to increase the processing speed. To provide a controller circuit.

[0010]

A DMA controller circuit according to the present invention provides direct memory access to a memory device in response to a direct memory access request to the memory device from an input / output device connected to a central processing unit. A DMA controller circuit for performing, the detecting means for detecting the direct memory access request input from the input / output device when the central processing unit accesses another device, and the detecting means detects the direct memory access request. Wait inserting means for inserting a wait for performing the direct memory access in a machine cycle of access processing between the central processing unit and the other device when detected, and access between the central processing unit and the other device Processing and processing of the direct memory access It said weights and means for controlling to perform in the inserted machine cycles a.

In addition to the above-mentioned configuration, another DMA controller circuit according to the present invention has a counting means for counting the number of times of transfer with the memory device by the direct memory access, and a count value of the counting means is a predetermined value. And a notification means for notifying the central processing unit of that fact.

[0012]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a DMA controller circuit (DMAC) 1 includes a decoder 10 and a transfer request arbitration circuit 1
1, an address calculation circuit 12, and a transfer count calculation circuit 13
An interrupt generation circuit 14 and a data bus control circuit 15
And an address control circuit 16.

The decoder 10 decodes the address signal from the CPU 3 and sends various signals to each circuit in the DMA controller circuit 1 and an I / O device (not shown). For example, a transfer count setting signal to the transfer count calculation circuit 13 and a DMA transfer valid / invalid signal to the transfer request arbitration circuit 11 are generated and sent to the respective circuits.

The transfer request arbitration circuit 11 arbitrates access to the memory 5 based on the address strobe signal from the CPU 4, the DMA transfer request from the I / O device, and the set value match signal from the transfer number calculation circuit 13. Incidentally, CPU4
The address strobe signal from is output when the CPU 4 accesses the memory 5 and the I / O device.

The transfer request arbitration circuit 11 determines whether the DMA transfer is valid or invalid according to a signal from the decoder 10. When the transfer request arbitration circuit 11 determines that the DMA transfer is valid, it inserts a cycle for processing the DMA transfer into the machine cycle of the memory access by the CPU 4 and sets the machine cycle as the DMA transfer insertion cycle.

That is, when a DMA transfer request from the I / O device is generated at the falling edge of the clock, the transfer request arbitration circuit 11 starts at the rising edge of the address strobe signal input from the CPU 4 after the DMA transfer request is generated. The above operation is performed so that the machine cycle to be performed becomes the DMA transfer insertion cycle. The transfer request arbitration circuit 11 resets the DMA transfer request within the cycle each time one DMA transfer is completed, and waits for the next DMA transfer.

Further, the transfer request arbitration circuit 11 determines the number of waits required for the memory or I / O device to be DMA-transferred at that time based on the access request from the CPU 4 to the memory 5 and the DMA transfer request from the I / O device. The number of waits for DMA and the memory or I to be accessed at that time
The number of waits for the CPU 4, which indicates the number of waits required for the / O device, is added to the machine cycle of the CPU 4.

The address calculation circuit 12 generates a DMA address signal for DMA transfer based on the data transfer start address by DMA, setting of increase / decrease of address, and the signal from the transfer request arbitration circuit 11, and the DMA address is generated. The signal is output to the address control circuit 16.

The transfer count calculation circuit 13 calculates the number of DMA transfers by the signal from the transfer request arbitration circuit 11, and when the calculated value reaches the transfer count set by the signal from the decoder 10, transfers the set value match signal. Output to the request arbitration circuit 11 and the interrupt generation circuit 14.

The interrupt generation circuit 14 is a transfer number calculation circuit 1
When the set value matching signal is input from 3, an interrupt signal is generated and output to the CPU 4. When the interrupt signal is input from the interrupt generation circuit 14, the CPU 4 knows that the DMA transfer has been performed the number of times set in the transfer number calculation circuit 13, and processes the data DMA-transferred to the memory 5.

When the data bus control circuit 15 is informed by the signal from the transfer request arbitration circuit 11 that the DMA transfer insertion cycle has been entered, the data between the CPU 4 and the memory 5 is transferred according to the signal from the memory control circuit 2. The I / O data register 3 for storing the data of the I / O device and the data between the memory 5 are sequentially selected.

That is, when the access by the CPU 4 is writing data to the memory 5 and the DMA transfer is transferring data from the I / O data register 3 to the memory 5,
The data from the CPU 4 and the data in the I / O data register 3 are sequentially selected by the data bus control circuit 15 and written in the memory 5.

Further, the access by the CPU 4 is performed by the memory 5
By reading data from the
In the case of data transfer to the / O data register 3, the data read from the memory 5 is the data bus control circuit 15
Selected in step S1 and sent to the CPU 4 and the I / O data register 3 in order.

The access by the CPU 4 is writing of data to the memory 5, and the DMA transfer is I / O from the memory 5.
In the case of data transfer to the data register 3, or C
Access from the PU 4 is reading data from the memory 5, and DMA transfer is from the I / O data register 3 to the memory 5.
The operation is the same as above when transferring data to.

Also, when the access by the CPU 4 is writing / reading of data to / from the I / O device, the same operation as above is performed.

The address control circuit 16 is the memory control circuit 2
The address signal from the CPU 4 and the DMA address signal generated by the address calculation circuit 12 are sequentially selected in accordance with the signal from the memory 5 and sent to the memory 5.

The memory control circuit 2 includes a transfer request arbitration circuit 11
When it is notified that the DMA transfer insertion cycle has been entered by the signal from, a signal for instructing the switching timing of the data and address signals is output to the data bus control circuit 15 and the address control circuit 16.

Further, the memory control circuit 2 controls the memory 5 by a read signal and a write signal from the CPU 4 and a signal from the transfer request arbitration circuit 11, that is, the CPU.
Read / write signals for actual operation, read / write signals for DMA control, and chip select (memory DR
If it is AM, it generates and outputs a RAS, CAS) signal or the like.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

When a DMA transfer request from the I / O device occurs while the CPU 4 is accessing the memory 5, the transfer request arbitration circuit 11 enables or disables the DMA transfer according to the signal set by the decoder 10. To judge.

When the transfer request arbitration circuit 11 determines that the DMA transfer is valid, the transfer request arbitration circuit 11 operates so that the machine cycle started at the rising edge of the address strobe signal becomes the DMA transfer insertion cycle.

That is, the transfer request arbitration circuit 11 uses the DMA
When a transfer request is generated, a wait request signal is sent to the CPU 4 to insert a wait into the next machine cycle in the CPU 4. Thereafter, the transfer request arbitration circuit 11 instructs the address calculation circuit 12 to generate a DMA address signal for DMA transfer, and notifies the transfer count calculation circuit 13 of the DMA transfer.

The transfer request arbitration circuit 11 includes a memory control circuit 2, a data bus control circuit 15, and an address control circuit 1.
6 and 6 are notified that the DMA transfer insertion cycle has been entered. Upon receiving the notification of the DMA transfer insertion cycle from the transfer request arbitration circuit 11, the memory control circuit 2 generates and outputs a control signal for DMA transfer to the memory 5.

At this time, in the data bus control circuit 15, I
The / O data register 3 side is selected, and the address control circuit 16 selects the DMA address signal from the address calculation circuit 12.

Therefore, in the first half of this DMA transfer insertion cycle, DMA transfer is performed between the I / O device and the memory 5.

At the timing when the DMA transfer between the I / O device and the memory 5 is completed, the memory control circuit 2 causes the memory 5 to move.
To generate and output a control signal for CPU actual operation. At the same time, the memory control circuit 2 is replaced by the data bus control circuit 1
5 and the address control circuit 16 to output a switching instruction signal.

Upon receiving the switching instruction signal from the memory control circuit 2, the data bus control circuit 15 switches from the I / O data register 3 side to the CPU 4 side. When the address control circuit 16 receives the switching instruction signal from the memory control circuit 2, the address control circuit 16 switches the DMA address signal from the address calculation circuit 12 to the address signal from the CPU 4.

Therefore, in the latter half of this DMA transfer insertion cycle, access is performed between the CPU 4 and the memory 5.

When the CPU 4 is accessing the I / O device and a DMA transfer request is issued from another I / O device, the CPU 4 and the CPU 4 Access between I / O devices and other I / O
The DMA transfer by the device is performed in the same machine cycle.

In this way, the CPU 4 causes the memory 5 and I / O
When a DMA transfer request is made to the memory 5 from another I / O device while accessing the device, the transfer request arbitration circuit 11 sends a wait request signal to the CPU 4 to send a machine cycle of the access process of the CPU 4. Is inserted into the DMA transfer insertion cycle, and the access processing by the CPU 4 and the DMA transfer from the other I / O device to the memory 5 are performed within the DMA transfer insertion cycle, so that the operation of the CPU 4 is not stopped. Further, the access processing of the CPU 4 and the DMA transfer of the I / O device can be executed in the same machine cycle without stopping the operation of the DMA controller circuit 1.

Therefore, even if a DMA transfer request is issued while the CPU 4 is accessing another device, the CP
Since the DMA transfer can be performed without stopping the processing of U4, it is possible to reduce the time until the CPU4 is brought into the hold state, and the access processing of the CPU4 and I
It is possible to increase the processing speed in the DMA transfer of the / O device.

Since the DMA transfer of the I / O device is performed without stopping the operation of the CPU 4 itself, the CPU 4
The only signal for the request is the wait request signal, and the DMA transfer control can be simplified.

[0044]

As described above, according to the present invention, when a direct memory access request from an input / output device is detected while the central processing unit is accessing another device, the central processing unit is A wait for direct memory access is inserted in the machine cycle of access processing with the device, and direct memory access and access processing with other devices by the central processing unit are inserted in the machine cycle in which the wait is inserted. By controlling so that the processing is performed, the DMA transfer can be performed without stopping the processing of each of the CPU and the DMA controller circuit, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 1 DMA controller circuit 2 Memory control circuit 3 I / O data register 4 CPU 5 Memory 10 Decoder 11 Transfer request arbitration circuit 12 Address calculation circuit 13 Transfer count calculation circuit 14 Interrupt generation circuit 15 Data bus control circuit 16 Address control circuit

Claims (2)

[Claims] 1. A DMA controller circuit for performing direct memory access to a memory device in response to a direct memory access request to the memory device from an input / output device connected to the central processing unit, the central processing unit comprising: Detecting means for detecting the direct memory access request input from the input / output device when the device accesses another device; and the central processing unit and the other device when the detecting means detects the direct memory access request. Between the central processing unit and the other device and the direct memory access processing, the wait insertion means for inserting a wait for performing the direct memory access in the machine cycle of the access processing between As done within the machine cycle in which the And a means for controlling the DMA controller circuit. 2. Counting means for counting the number of transfers to and from the memory device by the direct memory access,
2. The DMA controller circuit according to claim 1, further comprising a notification unit that notifies the central processing unit of the fact that the count value of the counting unit reaches a predetermined value.