JP3016812B2 - Wait cycle controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a wait cycle control device for controlling insertion of a wait cycle in a bus cycle when transferring parallel data. .

[Conventional technology]

Control device and arithmetic device of information processing device (hereinafter collectively
When performing parallel data transfer between a storage device (hereinafter collectively referred to as memory) or a peripheral device (hereinafter collectively referred to as I / O) and a certain sequence, respectively. The data is transferred by the bus cycle. Each bus cycle is divided into T states that change every clock, and T1 state, T2 state
It is composed of states. FIG. 4 shows a bus cycle when writing data to the memory as an example.
The memory requested to input data in the bus cycle of FIG. 4 corresponds to the address value within a predetermined time of the bus cycle from the output of the address until the CPU outputs the data to the data bus. It is necessary to enter data. If data cannot be output or input within the fixed time of this bus cycle, and data is input / output to / from memory or I / O that is slow in data input / output, the bus A bus cycle can be extended by inserting a cycle called a wait cycle so that the input and output of low-speed memory and I / O data can be performed in time during the cycle. FIG. 5 shows a bus cycle when a wait cycle is inserted twice into the bus cycle shown in FIG.

The CPU controls the insertion of the wait cycle by the arrow 501,5.
Check the ▲ ▼ signal at the timing indicated by 02,503,
If the signal is high, wait
If a cycle is inserted and the level is low, no wait cycle is inserted. The weight cycle is ▲
▼ As many signals as necessary can be inserted as long as the signal is high.

In order to control the insertion of such a wait cycle, a wait cycle controller is used. FIG. 7 shows a block diagram of a conventional wait cycle control device.

The wait cycle control device shown in FIG. 7 includes a bus cycle determining unit 101 for determining the type of a bus cycle, a wait cycle number setting register 102 holding the set number of wait cycles, and a wait cycle number. Wait cycle number selection unit 103 for selecting and decoding
A counter 105 for counting the number of inserted wait cycles, a comparator 106 for comparing the counter 105 with the set number of wait cycles, a signal 109 for controlling the signal ▼, a signal 109 generator 107, a bus cycle Status signal 10 that outputs the type of
Consists of eight.

 The operation will be described below with reference to the block diagram of FIG.

When a bus cycle is issued, the bus cycle determination unit 101 makes the address bus and bus status signal 108
The type of the bus cycle is determined from the
Tells you which value to choose from. The wait cycle number selection unit 103 selects and decodes the number of wait cycles to be inserted from the wait cycle number setting register 102 from the type of bus cycle determined by the bus cycle determination unit 101. The counter 105 counts the number of inserted wait cycles and outputs it to the comparator 106. The comparator 106 counts the number of wait cycles determined by the wait cycle number selection unit 103 and the counter 1
The outputs of 05 are compared, and until the number of counted wait cycles reaches the number determined by the wait cycle number selection unit 103, the signal is output to the signal generation unit.
Continue to request the signal to go high.

As described above, the conventional wait cycle control method sequentially processes the issuance of a bus cycle to the output of a signal for inserting a wait cycle from the issuance of a bus cycle.
It is not suitable for controlling a wait cycle when the time until signal detection is short.

[Problems to be solved by the invention]

FIG. 6 shows a bus cycle by a conventional CPU. A bus cycle by a conventional CPU is composed of T states of four clocks T1, T2, T3, and T4. Detection of a signal for inserting a wait cycle is performed at the rise of the T3 state indicated by an arrow 601. From issue of bus cycle ▲
▼ The time until signal detection is 100 nsec per cycle when the clock frequency is 10 MHz, for example.
From the time the CPU issues a bus cycle to the time the CPU detects a signal, the bus cycle shown in FIG.
0 nsec, and there is a time of 250 ns in the conventional bus cycle shown in FIG. Until now, the wait cycle control device has been able to determine the type of bus cycle during this period, decode the set number of wait cycles, and control the output of the signal. However, such as increasing the clock frequency or shortening the bus cycle required to execute an instruction,
From the issuance of bus cycles due to the higher performance of CPU ▲
▼ The time required to detect a signal is getting shorter. The conventional sequential control of the signal has the disadvantage that the control of the wait cycle in such a high-performance CPU cannot be performed in time.

[Means for solving the problem]

The wait cycle control device according to the present invention includes: a determination unit that determines a bus cycle to be executed; and, in response to a determination result from the determination unit, represents a number of wait cycles to be inserted for the bus cycle to be executed. Data
Means for outputting the data; and outputting a signal which becomes active when the number of wait cycles represented by the data is not 0, wherein the number of wait cycles inserted during execution of the bus cycle indicates a wait represented by the data. A wait cycle control device having means for maintaining the number of cycles until the number of cycles is reached, and generating means for generating a wait cycle insertion request in response to the active level of the signal, wherein the determination result from the determination means is Further comprising means for outputting information indicating whether or not the bus cycle to be executed requires a wait cycle, wherein the generating means receives the information and requires the information to require a wait cycle. Indicates that the wait cycle insertion is required even if the signal is not at the active level. Characterized in that it is configured to generate.

That is, after the conventional bus cycle is issued,
In controlling the signal, the type of the bus cycle is first detected, then the number of set wait cycles is selected and decoded, and the sequential control for controlling the signal is performed.

In the present invention, after a bus cycle is issued,
▼ Before issuing the signal, first select the specific wait cycle number setting register, and
Detect if the number of cycles is greater than or less than a certain number.

For example, when indicating whether the number of specific wait cycles is 0 or 1 or more, if the number of selected wait cycles is 1 or more, first issue 1 wait cycle and subtract the bus cycle. extend. Then, the set number of arbitrary wait cycles is decoded at the time extended by the insertion of the one wait cycle, and after the completion of one wait cycle, the remaining wait cycles are inserted.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the drawings.

A bus cycle determination unit 101 that determines the type of a bus cycle. Arbitrary wait cycle number setting register that holds the number of wait cycles inserted in the bus cycle
102. The number of set wait cycles is 0 or 1
A specific wait cycle number setting register 110 holding the above information. A type of bus cycle obtained from the bus cycle determination unit 101 and a wait cycle number selection unit 103 for selecting the number of wait cycles from the wait cycle number setting register 102. Bus cycle judgment unit 1
Check the type of bus cycle obtained from 01 and whether the number of wait cycles is 0 or 1 or more from the specific wait cycle number setting register 110, and if it is 1 or more, insert 1 wait cycle. Signal generator 10
Wait cycle number 0 detector 104 required for 7. ▲
▼ Counter 108 counts the number of signals and outputs the counted number to comparator 106, compares the set number of wait cycles with the number of bus cycles, and
A comparator 106 for requesting the signal generation unit 107 to generate a signal, and a signal generation unit 107 for controlling the output of the signal. bus·
Bus status signal 108 indicating the type of cycle, ▲
▼ Signal 109 is connected.

The operation of this embodiment will be described below with reference to the block diagram of FIG.
This will be described with reference to the timing charts of FIGS.

First, the case where the number of inserted wait cycles is 1 will be described with reference to the timing chart of FIG.

Bus cycle judgment unit when bus cycle is issued
101 indicates that after the address value of the address bus and the bus status signal 108 are determined near the rising edge of the T1 cycle,
The type of the issued bus cycle is determined, and the type of the bus cycle is output.

The wait cycle number 0 detection unit 104 determines the specific wait cycle number setting register 11 based on the type of bus cycle.
It is checked whether the number of wait cycles to be inserted is 0 or 1 or more from 0. In this case, since it is set to insert 1 wait cycle, the signal generation unit 107 is supplied with 1 wait cycle. Like inserting
▼ Request signal generation.

The signal generator 107 inactivates the signal during the T2 state. CPU is T2
At the rise of the state, it detects that the signal is inactive and inserts one wait cycle.

Also, the wait cycle number selection unit 103
Similarly to the cycle number 0 detection unit 104, the number of wait cycles to be inserted is selected from the arbitrary wait cycle setting register 102 from the type of the bus cycle output to the bus cycle determination unit 101, and is decoded.
The number of decoded wait cycles is output to 106.

The counter 105 counts the number of ▲ ▼ signals since the bus cycle was issued at the rising edge of the ▲ ▼ signal and outputs it to the comparator 106.
When the ▲ ▼ signal is output, 1 is input to the comparator 106.

The comparator 106 determines that the input wait cycle set value 1 and the count number 1 of the counter 105 match, and sends the signal to the signal generator 107.
▼ Request to keep the signal low, and end the insertion of the wait cycle.

Next, the case where the number of wait cycles is 0 will be described with reference to the timing chart of FIG.

Bus cycle judgment unit when bus cycle is issued
After the address value of the address bus and the bus status signal 108 are determined, the type 101 determines the type of the issued bus cycle and outputs the type of the bus cycle.

The wait cycle number 0 detection unit 104 determines the specific wait cycle number setting register 11 based on the type of bus cycle.
It is checked whether the number of wait cycles to be inserted is 0 or 1 or more from 0. In this case, since the setting is to insert 0 wait cycles, the ▲ ▼ signal is sent to the ▲ ▼ signal generator 107. Request to stay at the active level.

The wait cycle number selection unit 103 determines the wait cycle to be inserted from the arbitrary wait cycle setting register 102 based on the type of the bus cycle output from the bus cycle determination unit 101, similarly to the wait cycle number 0 detection unit 104. Is selected and decoded, and the number of decoded wait cycles, 0, is output to the comparator 106, and is input to the comparator.
Requests the signal generator 107 to keep the signal at a low level.

Here, the specific wait cycle number setting register and the arbitrary wait cycle number setting register will be described in detail. FIG. 9 shows an example of a specific wait cycle number setting register, which has one bit for each type of bus cycle. In FIG. 9, CPU memory cycle, CP
One bit is assigned to each UI / O cycle, DMA cycle, and refresh cycle. If the bit corresponding to the issued bus cycle is "1", insert one or more waits; if "0", insert zero wait. Insertion. FIG. 10 shows an example of an arbitrary wait cycle number setting register, which has three bits for each type of bus cycle and can insert up to seven waits. First, when a bus cycle is issued, whether a 0 wait or more than 1 wait is inserted is detected at a high speed by a specific wait cycle number setting register, and the signal is controlled. When more than one wait is inserted, the number of waits corresponding to the bus cycle is selected and decoded from the arbitrary number of wait cycles setting register at the same time. -Insert a cycle.

In another embodiment 2 of the present invention, the number of wait cycles is further reduced to 0 by the wait cycle number 0 detector of the first embodiment.
In addition to detecting the case of 1, the weight of 2 or more
When a cycle is inserted, two wait cycles are inserted first. In the first embodiment, a time corresponding to one wait cycle is obtained, whereas a time corresponding to two wait cycles is obtained. Things.

FIG. 8 is a block diagram of the present embodiment. Although the configuration is the same as that of the embodiment shown in FIG. 1, the number of wait cycle number setting registers 110 in the embodiment shown in FIG. The cycle 0 detection unit 104 is replaced with a wait cycle 0, 1 detection unit 804 that detects 0 or 1, 2 or more.

The operation of the present embodiment is the same as the operation of the first embodiment when one or less wait cycles are inserted. When inserting two or more wait cycles, the wait cycle 0, 1 detector first requests the signal generator to insert two wait cycles, and decodes the number of wait cycles to be inserted during this period. Then, after inserting two wait cycles, the remaining wait cycles are inserted.

〔The invention's effect〕

Among the demands for improving the performance of information processing devices, reduction of the time required for control and calculation is one of the greatest demands. The CPU operation speed has been remarkably increased in order to reduce the time required for this control and operation, and CPU performance will continue to increase due to the increase in clock frequency and the number of clocks required for bus cycles. Conceivable.

When controlling a wait cycle in a system using such a high-performance CPU, in the conventional sequential control of the wait cycle, processing is performed within a predetermined time of the bus cycle. ▼ It is difficult to control signals, and if the processing time for wait cycle control is shortened due to the improvement of CPU performance, the conventional sequential processing is ▲ ▼
Control of the signal may not be possible.

However, by using the present invention, even in a system using a high-performance CPU in which the clock frequency has been improved or the number of clocks required for a bus cycle has been reduced, for example, a method as shown in the first embodiment can be used.・ Cycle control can be performed. And even CPU
In the case where the time for controlling the weight cycle is shortened due to the performance improvement, the set number of weight cycles is not 0 or 1 or more as shown in the second embodiment.
By having an output indicating whether the set number of wait cycles is 0, 1 or 2 or more, the time of 2 wait cycles can be gained, and it is possible to cope with an increase in the speed of the CPU.

As described above, according to the present invention, it is possible to configure a wait cycle control device that can cope with a CPU that operates at a high speed, and there are sufficient effects.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention,
2 and 3 are timing charts for explaining the operation of the embodiment of FIG. 1, FIGS. 4, 5, and 6 are timing charts showing basic bus cycles, and FIG. Is a block diagram showing a configuration of a conventional weight cycle control device, FIG. 8 is a block diagram showing another embodiment of the present invention,
FIG. 9 is a block diagram of a specific wait cycle number setting register, and FIG. 10 is a block diagram of an arbitrary wait cycle number setting register. 101: Bus cycle determination unit, 102: Arbitrary wait
Cycle number setting register, 110,810 …… Specific wait
Cycle number setting register, 103: Wait cycle number selection unit, 104: Wait cycle number 0 detection unit, 804
... Wait cycle number 0, 1 detector, 105, counter, 106, comparator, 107, signal generator 108, address bus and bus status signal, 109, ▲ ▼ signal, 401,501,502,503,6
01 …… The timing when the CPU detects the ▲ ▼ signal.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-88763 (JP, A) JP-A-59-114639 (JP, A) JP-A-59-114638 (JP, A) 132249 (JP, U) Actually open 63-75960 (JP, U) Hitachi microcomputer data book 8-bit / 16-bit microprocessor, (September 1985), Hitachi, Ltd., p462-464

Claims (1)

(57) [Claims] A determining means for determining a bus cycle to be executed; and responding to the determination result from the determining means, obtaining data indicating the number of wait cycles to be inserted for the bus cycle to be executed. Means for outputting data;
A signal which becomes an active level when the number of wait cycles represented by the data is not 0 is output, and is maintained until the number of wait cycles inserted during execution of the bus cycle becomes the number of wait cycles represented by the data. Means for generating a wait cycle insertion request in response to the active level of the signal, wherein the execution is performed in response to the determination result from the determination means. And a means for outputting information indicating whether the bus cycle requires a wait cycle. The generating means receives the information, and when the information indicates that a wait cycle is required, generates the signal when the signal indicates the wait cycle. It is configured to generate the wait cycle insertion request even when the state is not the active level. Wait cycle controller according to claim Rukoto.