JPS6488763A - Input/output control circuit - Google Patents

Input/output control circuit

Info

Publication number
JPS6488763A
JPS6488763A JP24613187A JP24613187A JPS6488763A JP S6488763 A JPS6488763 A JP S6488763A JP 24613187 A JP24613187 A JP 24613187A JP 24613187 A JP24613187 A JP 24613187A JP S6488763 A JPS6488763 A JP S6488763A
Authority
JP
Japan
Prior art keywords
input
cpu
ram
sets
weight number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24613187A
Other languages
Japanese (ja)
Inventor
Toshio Kikukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24613187A priority Critical patent/JPS6488763A/en
Publication of JPS6488763A publication Critical patent/JPS6488763A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To omit the change of a READY signal generating circuit in case of replacement with a high-speed CPU by producing a READY signal by counting CPU clocks based on data obtained via a RAM. CONSTITUTION:A CPU 11 sets an address on an address line to turn on a flip-flop 13 and sets a RAM 14 under a writing ready state. Then the CPU 11 sets the weight number necessary for an input/output port to the RAM 14 to set the RAM 14 in a read mode to obtain weight number data out of the desired input/output port. Then a READY signal generating circuit 16 is actuated and the input/output read/write signals extended by the weight number are sent to an input/output device 15. Thus no change is required for the circuit 16 even though the CPU 11 or the device 15 is replaced with a high-speed type one.
JP24613187A 1987-09-30 1987-09-30 Input/output control circuit Pending JPS6488763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24613187A JPS6488763A (en) 1987-09-30 1987-09-30 Input/output control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24613187A JPS6488763A (en) 1987-09-30 1987-09-30 Input/output control circuit

Publications (1)

Publication Number Publication Date
JPS6488763A true JPS6488763A (en) 1989-04-03

Family

ID=17143940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24613187A Pending JPS6488763A (en) 1987-09-30 1987-09-30 Input/output control circuit

Country Status (1)

Country Link
JP (1) JPS6488763A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278158A (en) * 1990-03-27 1991-12-09 Nec Corp Wait cycle controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278158A (en) * 1990-03-27 1991-12-09 Nec Corp Wait cycle controller

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