JPS57198595A - Dynamic memory driving circuit - Google Patents

Dynamic memory driving circuit

Info

Publication number
JPS57198595A
JPS57198595A JP56081077A JP8107781A JPS57198595A JP S57198595 A JPS57198595 A JP S57198595A JP 56081077 A JP56081077 A JP 56081077A JP 8107781 A JP8107781 A JP 8107781A JP S57198595 A JPS57198595 A JP S57198595A
Authority
JP
Japan
Prior art keywords
signal
circuit
display
clock
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56081077A
Other languages
Japanese (ja)
Inventor
Shigeru Hirahata
Masutomi Oota
Tetsuya Ikeda
Tsuguji Tateuchi
Shigeru Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56081077A priority Critical patent/JPS57198595A/en
Publication of JPS57198595A publication Critical patent/JPS57198595A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To improve the processing speed, by generating the clock signal of an operation processing circuit (MPU) independently of a display signal. CONSTITUTION:A clock generating circuit 6 generates the output to determine the clock signal of an operation processing circuit MPU1 independently of a display timing signal generating circuit 21. A clock stretcher 7 consists of three or four flip flops and divides the oscillation output signal by 4 to issue the output to a signal line 18 when a signal 17 is low-level, and the circuit 7 allows the output signal to rise in accordance with the oscillation output signal and does not allow the output signal to fall when the signal 17 is high-level. An address swiching circuit 8 controls a RAM23 for display and a data RAM3. Further, a character pattern display circuit 2, a display timing signal generating circuit 21, and an address switching circuit 22 are provided.
JP56081077A 1981-05-29 1981-05-29 Dynamic memory driving circuit Pending JPS57198595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56081077A JPS57198595A (en) 1981-05-29 1981-05-29 Dynamic memory driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56081077A JPS57198595A (en) 1981-05-29 1981-05-29 Dynamic memory driving circuit

Publications (1)

Publication Number Publication Date
JPS57198595A true JPS57198595A (en) 1982-12-06

Family

ID=13736321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56081077A Pending JPS57198595A (en) 1981-05-29 1981-05-29 Dynamic memory driving circuit

Country Status (1)

Country Link
JP (1) JPS57198595A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62135881A (en) * 1985-12-10 1987-06-18 オリンパス光学工業株式会社 Image display unit
JPH01259685A (en) * 1988-04-08 1989-10-17 Matsushita Electric Ind Co Ltd Display device
JPH02304481A (en) * 1989-05-18 1990-12-18 Mitsubishi Electric Corp Display controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS539442A (en) * 1976-07-13 1978-01-27 Fujitsu Ltd Micro processor control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS539442A (en) * 1976-07-13 1978-01-27 Fujitsu Ltd Micro processor control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62135881A (en) * 1985-12-10 1987-06-18 オリンパス光学工業株式会社 Image display unit
JPH01259685A (en) * 1988-04-08 1989-10-17 Matsushita Electric Ind Co Ltd Display device
JPH02304481A (en) * 1989-05-18 1990-12-18 Mitsubishi Electric Corp Display controller

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