JPH02304481A - Display controller - Google Patents

Abstract

PURPOSE:To reduce power consumption by cutting off the transfer of a clock signal to the first control circuit with a gate circuit when a signal from a central processor instructs that the first control circuit is under an inactive state. CONSTITUTION:When access from a CPU 3 is stopped, the control circuit 5 becomes the inactive state that it does not particularly execute any action. Since the output of an OR gate 10 becomes at an 'L' level and the reset of a programable counter 11 is released, the clock signal from a clock input terminal 16 is started to be counted by the programable counter 11 and a carry output RCO becomes at an 'H' level. Besides, since the reset of an R-S flip-flop 12 is released and the signal of the 'H' level is given to a set terminal S from the carry output RCO of the programable counter 11, the R-S flip-flop 12 is set and a 'not output Q' becomes at the 'L' level. Due to that, an AND gate 13 cuts off the clock signal transmitted to a control circuit system timing generation circuit 8 from the clock input terminal 16. Thus, the control circuit 5 is stopped and the power consumption in the control circuit 5 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control device for controlling display devices such as CRTs and plasma displays.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional display control device and peripheral circuits. The display@control device 1 includes a central processing unit (hereinafter referred to as CPU) 3 and a D constituting a frame memory.
Signals and display data for controlling the display device 2 are supplied from the RAM 4 and the like.

Signals and data input from the CPU 3 via the system bus 14 are input to n registers R1 to Rk, and then applied to the control circuit 5.

Further, data input from the DRAM 4 is given to the control circuit 5 via the memory control circuit 6 and the data Φ address bus 15.

A clock signal having a frequency of several MHz to several tens of MHz input from the clock input terminal 16 is applied to a control circuit timing generation circuit 8 and a memory control circuit timing generation circuit 9 in the timing generation circuit 7. The control circuit system timing generation circuit 8 divides the frequency of this clock signal as necessary and supplies it to the fI4111 circuit 5. In addition, the $1 ga circuit timing generation circuit 9 for memory is as follows:
This clock signal is frequency-divided as necessary and applied to the memory control circuit 6.

Next, the operation will be explained. The first action is,
Control commands and display data from the CPU 3 are sent via the system bus 14 and further to the register R1 in the display control device 1.
~Rn to the control circuit 5. The control circuit 5 is operated by a clock signal from the timing generation circuit 8 of the control 1 circuit system, and supplies this display data to the display device 2 to display predetermined characters, images, etc.

Further, as a second operation, a control command and display data from the CPU 3 are given to the t4 control circuit 5 via the system bus 14 and further via the registers R1 to R1 in the display control device 1. The ma1 circuit 5 is operated by a clock signal from the control circuit system timing generation circuit 8, and sends this display data to the memory control circuit 6 via the data address bus 15, and further stores the display data in the DRAM 4.

Then, as a third operation, a wi control command from the CPU 3 is given to the control circuit 5 via the system bus and further via the registers R1 to Rn in the display iNiw device 1. The fI411 circuit 5 reads out display data stored in advance from the DRAM 4 via the data address bus 15 and the memory Ma1 circuit 6, and supplies this display data to the display device 2 to display predetermined characters, images, etc.

Since the operations directly related to display as described above need to be performed at high speed, a relatively high frequency clock signal is input to the control circuit 5.

Furthermore, the operation of j14 includes a refresh operation for holding display data stored in the DRAM 4 based on a control command from the memory control circuit 6. The memory ms circuit 6 is operated by a clock signal from the memory 1079 circuit timing generation circuit 9. Note that this refresh operation is always performed in parallel with other operations. Also, it may be performed at a lower speed compared to other actions.
It operates reliably even with relatively low frequency clock signals.

[RWJ to be solved by the invention] Since the conventional display control device is configured as described above, a relatively high frequency clock signal is always given to the control circuit 5 which is not involved in the refresh operation, and the CP
There is a problem in that power consumption is large even when there is no access from U3 and the control circuit 5 is in an inactive state in which it does not perform any particular operation.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a display control device that reduces power consumption while retaining stored data.

[Means to solve the problem]

A display control device having a first configuration according to the present invention is a display control device that is connected to a central processing unit, a display device, and a storage device, receives a signal from the central processing unit, and controls the display device and the storage device. a first control circuit that is given a signal from the central processing unit and controls data transfer between the central processing unit, the display device, and the storage device; a second control circuit that controls the storage device while refreshing data; a clock input terminal that receives a clock signal used for the operation of the first and second control circuits; and a clock input terminal that receives a signal from the central processing unit as a control signal. and a gate circuit that cuts off transmission of the clock signal to the first control circuit when the signal from the central processing unit indicates the inactive state of the first control circuit.

Further, a display control device having a second configuration according to the present invention is connected to a central processing unit, a display device, and a storage device, receives a signal from the central processing device, and provides a display control device that controls the display device and the storage device. The device includes a first control circuit that receives a signal from the central processing unit and controls data transfer between the central processing unit, the display device, and the storage device; a tJ2 control circuit that controls the storage device while refreshing data in the device; and a first clock input that receives a first clock signal having a relatively high frequency used for operating the first and second control circuits. a second clock input terminal receiving a second clock signal having a relatively low frequency used for a data refresh operation by the second control circuit; and a second clock input terminal receiving a signal from the central processing unit as a control signal; When the signal from the central processing unit instructs the first control circuit to be inactive, the second clock signal is applied to both the first and second control circuits, or to the second control circuit. A second clock signal is given to the first control circuit of *i.
and clock signal selection means that does not apply any of the second clock signals.

[Effect]

The gate circuit in the first configuration of the present invention blocks transmission of the clock signal to the first control circuit when a signal from the central processing unit instructs the first control circuit to be inactive.

Further, in the second configuration of the present invention, the clock signal selection means transmits the clock signal to both the first and second control circuits when the signal from the central processing unit instructs the first control circuit to be inactive. a second clock signal or a second
The second clock signal is supplied to the control circuit of the first control circuit, and neither the first nor the second clock signal is supplied to the first control circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the configuration of a display@control device and peripheral circuits according to an embodiment of the present invention.

In the figure, n signal lines in the display control device la connected to the system bus 14 are connected in parallel to the input of the OR gate 10. The output of the OR gate 1° is applied to the reset terminal R of the programmable counter 11 and the reset terminal R of the R-S flip-flop 12. The carry output RCO of programmable counter 11 is applied to the set terminal S of R-S flip-flop 12, and the negative output page of R-S flip-flop 12 is applied to the input of AND gate 13. The clock signal from the clock input terminal 16 is applied to the clock input terminal CLK of the programmable counter 11 and the other input of the AND gate 13, and the control circuit system timing generation circuit 8 is applied to the output of the AND gate 13. Other configurations and connections with peripheral circuits are the same as those of the conventional display control device 1 shown in FIG. 3 described above.

Next, the operation will be explained. The display control device 1a is a CPU
When control commands and display data are input to the registers R1 to R through the system bus 14, the R-S flip-flop tube 12 is reset and the negative output is enabled. H
° level. Since the clock signal from the clock input terminal 16 is applied to the control circuit system timing generation circuit 8 via the AND gate 13, the operation is similar to that of the conventional display control device 1 shown in FIG. 3 described above.

When access from CPU 3 stops, OR gate 10
All inputs become 'L' level. At this time, the control circuit 5 enters an inactive state in which no particular operation is performed. The output of the OR gate 10 becomes 'L° level, and the reset of the programmable counter 11 is released. Therefore, the programmable counter 11 starts counting the clock signal from the clock input terminal 16. If no access is made from the CPU 3 for a certain period of time or more, the programmable counter 11 counts a preset number of clock signals, and the carry output RCO becomes "H" level.

The reset of the R-S flip-flop 12 has been released, and the "H" level signal is given to the set terminal S from the carry output RCO of the programmable counter 11, so the R-S flip-flop 12 is set and outputs a negative output. Possible is “L” level. Therefore, AND gate 13
blocks the clock signal from the clock input terminal 16 to the control circuit system timing generation circuit 8, so the control circuit 5
is stopped, and the power consumption in the control circuit 5 is significantly reduced.

However, when the access from the CPU 3 is started, the output of the OR gate 10 becomes "H° level" and the normal operation described above is restored.

Note that since the clock signal to the timing generation circuit 9 of the memory control circuit system is always supplied, the refresh operation is always performed and the data in the DRAM 4 is held.

FIG. 2 is a block diagram showing the configuration of a display control device and peripheral circuits according to another embodiment of the invention.

In the figure, in addition to the clock input terminal 16, the display control device lb includes a second terminal. A clock input terminal 17 is provided. A clock signal having a frequency lower than that of the clock signal input to the clock input terminal 16 but high enough to perform a refresh operation is input to the second clock input terminal 17.

Further, a selector 18 is provided in place of the AND gate 13 shown in FIG. Clock input terminals 16 and 17 are connected to inputs of selector 18, respectively. The output of the selector 18 is commonly given to the control circuit system timing generation circuit 8 and the memory control circuit system timing generation circuit 9.

The negative output Q of the R-S flip-flop 12 is $I I1
It is applied to the select terminal SL' of the selector 18 as a 1 signal. The other configurations and connections with other peripheral circuits are the same as the display control device 1a shown in FIG. 1 described above.

Next, the operation will be explained. Display #Control device 1b is CPU
3, the negative output enable of the R-S flip-flop 12 becomes -H' level. Since the selector 18 receives this signal and selects a relatively high frequency clock signal from the clock input terminal 16, the operation is similar to that of the conventional display control device 1 shown in FIG. 3 described above.

When access from the CPU 3 stops for a certain period of time or more, the R-S
The negative output Q of the flip-flop 12 becomes 'L° level. Selector 18 receives this signal and selects a relatively low frequency clock signal from second clock input terminal 17.

The control circuit system timing generation circuit 8 and the memory control circuit system timing generation circuit 9 are supplied with a relatively low frequency clock signal via the selector 18. Since the frequency of this clock signal is set to a level that allows a sufficient refresh operation, the memory control circuit 6 can refresh the data in the DRAM 4, and the data in the DRAMJ is retained.

Furthermore, during this period when access from the CPU 3 is stopped, the control circuit 5 is given a relatively low frequency clock signal, so it enters a standby state, for example, and power consumption is reduced. Display control device 1 shown in FIG. 1 described above
Similarly to a, when access from CPU3 is started,
Return to normal operation.

Note that by combining the embodiments shown in FIGS. 1 and 2, when access from the CPU 3 stops, the supply of the clock signal to the control circuit 5 is stopped, and a relatively low frequency signal is sent to the memory control circuit 6. The display controller may be configured to provide the clock signal.

〔Effect of the invention〕

As described above, according to the present invention, when the signal from the central processing unit instructs the inactive state of the first control circuit, the gate circuit in the first configuration controls the clock to the first control circuit. Block the transmission of signals.

In addition, the clock signal selection means in the second configuration transmits the second signal to both the first and second control circuits when the signal from the central processing unit instructs the first control circuit to be inactive. A clock signal is provided, or a second clock signal is provided to the second control circuit and neither the first nor the second clock signal is provided to the first control circuit.

Therefore, it is possible to obtain a display control device that reduces power consumption while retaining stored data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a display control device and peripheral circuits according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a display control device and peripheral circuits according to another embodiment of the invention. FIG. 3 is a block diagram showing the configuration of a conventional display control device and peripheral circuits. In the figure, la and lb are display control devices, 2 is a display device, 3 is a CPU, 4 is a DRAM, 5 is a control circuit, 6 is a memory control circuit, 10 is an OR gate, 11 is a programmable counter, and 12 is an R- S flip-flop, 13 is A
ND gate, 16 is a clock input terminal, 17 is a second clock input terminal, and 18 is a selector. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A display control device that is connected to a central processing unit, a display device, and a storage device, receives signals from the central processing device, and controls the display device and the storage device, a first control circuit that is connected to the storage device and controls data transfer between the central processing unit, the display device, and the storage device; a second controller that controls the storage device while performing refresh;
a control circuit, a clock input terminal receiving a clock signal used for the operation of the first and second control circuits, and a clock input terminal receiving the signal from the central processing unit as a control signal; A display control device comprising: a gate circuit that blocks transmission of the clock signal to the first control circuit when the signal indicates an inactive state of the first control circuit. (2) A display control device that is connected to a central processing unit, a display device, and a storage device, receives signals from the central processing device, and controls the display device and the storage device, a first control circuit that is connected to the storage device and controls data transfer between the central processing unit, the display device, and the storage device; a second controller that controls the storage device while performing refresh;
a control circuit, and a first clock signal input with a first clock signal having a relatively high frequency used to operate the first and second control circuits.
a second clock input terminal receiving a second clock signal having a relatively low frequency used for the data refresh operation by the second control circuit; and the signal from the central processing unit. is given as a control signal, and when the signal from the central processing unit instructs the first control circuit to be inactive, the second clock signal is sent to both the first and second control circuits. or the second clock signal to the second control circuit and the first and second clock signals to the first control circuit.
and clock signal selection means that does not provide any of the clock signals.