JPS5752905A - Step type memory sequencer - Google Patents
Step type memory sequencerInfo
- Publication number
- JPS5752905A JPS5752905A JP12680480A JP12680480A JPS5752905A JP S5752905 A JPS5752905 A JP S5752905A JP 12680480 A JP12680480 A JP 12680480A JP 12680480 A JP12680480 A JP 12680480A JP S5752905 A JPS5752905 A JP S5752905A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- output
- signal
- input
- multiplexer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/045—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Programmable Controllers (AREA)
Abstract
PURPOSE:To freely change the order of selection of input, by writing in the input selection signal of a multiplexer in a memory and selecting the advancement signal with a desired order with the multiplexer. CONSTITUTION:The output of a latch circuit latching the output of a memory 4 is divided into two parts. The 1st output is an address signal of a memory 6 and the data written in the memory is transmitted to a control objective via an output conversion circuit 7. The 2nd output is transmitted to a multiplexer 2 and selects the input signal inputted via an input conversion circuit 1. When a selected signal is inputted, a clock generating circuit 3 outputs a clock and an advance signal, and the next data to the memory 4 is applied to a latch circuit 5 and advances the sequence.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12680480A JPS5752905A (en) | 1980-09-12 | 1980-09-12 | Step type memory sequencer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12680480A JPS5752905A (en) | 1980-09-12 | 1980-09-12 | Step type memory sequencer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5752905A true JPS5752905A (en) | 1982-03-29 |
Family
ID=14944365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12680480A Pending JPS5752905A (en) | 1980-09-12 | 1980-09-12 | Step type memory sequencer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5752905A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60114376A (en) * | 1983-11-22 | 1985-06-20 | Kubokou Paint Kk | Ornamental finishing method |
JPS60200308A (en) * | 1984-03-24 | 1985-10-09 | Matsushita Electric Works Ltd | Control circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52144580A (en) * | 1976-05-27 | 1977-12-01 | Tadao Totsuka | Program control apparatus |
-
1980
- 1980-09-12 JP JP12680480A patent/JPS5752905A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52144580A (en) * | 1976-05-27 | 1977-12-01 | Tadao Totsuka | Program control apparatus |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60114376A (en) * | 1983-11-22 | 1985-06-20 | Kubokou Paint Kk | Ornamental finishing method |
JPS60200308A (en) * | 1984-03-24 | 1985-10-09 | Matsushita Electric Works Ltd | Control circuit |
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