JPS579152A - Code converter - Google Patents

Code converter

Info

Publication number
JPS579152A
JPS579152A JP8256580A JP8256580A JPS579152A JP S579152 A JPS579152 A JP S579152A JP 8256580 A JP8256580 A JP 8256580A JP 8256580 A JP8256580 A JP 8256580A JP S579152 A JPS579152 A JP S579152A
Authority
JP
Japan
Prior art keywords
parallel
produces
conversion
circuits
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8256580A
Other languages
Japanese (ja)
Inventor
Toshiro Kato
Kenji Ogami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP8256580A priority Critical patent/JPS579152A/en
Publication of JPS579152A publication Critical patent/JPS579152A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To enable to use low speed ICs by taking the time required for the processing longer, by independently making the control of mode selection for code conversion in pulse train in serial-parallel conversion of input data corresponding to each word. CONSTITUTION:An input data (1) is written in a 4Q bit shift register 11 with a clock signal 2, where Q is the number of words processed in parallel. A 4Q-bit memory 12 produces a parallel output signal (5) to keep it for 4Q-bit. Further, the signals (5) are inputted to a 4B/3T conversion circuits 4-1-4-Q sequentially in 4 consective words. The output of the circuits 4-1-4-Q is applied to data selectors 5-1-5-Q and mode selection is made according to the result of discrimination of discrimination circuits 6-1-6-Q. A parallel serial conversion circuit 14 produces a pulse (10) at tri-state signal in Q-word and a tri-state forming circuit 10 produces an output consisting of 4B/3T codes.
JP8256580A 1980-06-18 1980-06-18 Code converter Pending JPS579152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8256580A JPS579152A (en) 1980-06-18 1980-06-18 Code converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8256580A JPS579152A (en) 1980-06-18 1980-06-18 Code converter

Publications (1)

Publication Number Publication Date
JPS579152A true JPS579152A (en) 1982-01-18

Family

ID=13778003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8256580A Pending JPS579152A (en) 1980-06-18 1980-06-18 Code converter

Country Status (1)

Country Link
JP (1) JPS579152A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892466A (en) * 1995-03-29 1999-04-06 Sgs-Thomson Microelectronics Limited Coding scheme for transmitting data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892466A (en) * 1995-03-29 1999-04-06 Sgs-Thomson Microelectronics Limited Coding scheme for transmitting data

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