JPH05109270A - D-ram refresh controller - Google Patents

Abstract

PURPOSE:To unnecessitate executing a specific refresh cycle, then to unnecessitate a complex control circuit for this and to refresh a D-RAM without reducing the operational efficiency of a CPU by using the waiting state interval of the CPU. CONSTITUTION:By an AND gate 5, the waiting state in a read cycle to the D-RAM of the CPU is detected, by a NAND gate 4, a RAS signal is made a non-active state in a prescribed interval in the waiting state and a hidden refresh is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (hereinafter referred to as "D-") used in electronic devices such as personal computers and word processors.
Abbreviated as "RAM") D-R for refresh control
The present invention relates to an AM refresh controller.

[0002]

2. Description of the Related Art A conventional D-RAM refresh control device measures a refresh operation time of a D-RAM, and a central processing unit (hereinafter abbreviated as "CPU") at regular intervals according to the timer. ) Cycle (DR
A suspending means for suspending a cycle of access operation to the AM and the input / output device is provided, and RAS only refresh and C are provided during suspension of the CPU cycle by the suspending means.
It was common to insert a refresh cycle to perform AS before RAS refresh.

However, at each refresh operation, the CPU
If the cycle is interrupted, the operating efficiency of the CPU will drop. Further, as the control circuit, a circuit of a considerable scale corresponding to one channel of the timer and the DMA controller is required.

On the other hand, as the operating speed of CPUs has increased, some operating speeds of CPUs have become faster than the operating speeds of memories.
Cycles are becoming more common.

FIG. 6 shows an example of a circuit configuration in the case where the CPU controls the access operation of the D-RAM.

In FIG. 6, the CPU unit 1 is a CP
It is composed of U and D-RAM controller and operates in synchronization with the basic clock (CLK) input to them.
The D-RAM controller generates each memory control signal such as RAS, CAS, WE, and READY according to an instruction from the CPU. Each of the RAS, CAS, and WE signals is D along with an address bus and a data bus (not shown).
-It is directly connected to the memory unit 2 composed of RAM, controls the operation of the memory unit 2, and writes and reads data.

At this time, CLK, RAS, CAS, RE
7 and 8 are timing charts of ADY signals.
Shown in. Figure 7 shows the case of no wait cycle.
FIG. 8 shows a case where one wait cycle is provided in the first cycle.

This one wait cycle is D- when the operating speed of the memory is slower than the operating speed of the CPU.
When the CPU receives the fact that the RAM controller (possibly the memory unit 2) generates the READY signal and instructs the CPU to extend its operation cycle,
Normal CPU machine cycle (ie T1 and T
The weight state (TW) is inserted in the two states.

The CPU uses the end of each machine cycle (end of T2 or TW state: RE in FIGS. 7 and 8).
The READY signal is sampled at the timing indicated by the arrow below the ADY signal), and if the level of the READY signal is "H" as shown in FIG. 7, the cycle is ended and the process proceeds to the next cycle. If it is "L", it is determined that the state immediately before that (state that should be T2 when the level of the READY signal is "H") is the wait state (TW), and the memory control signal The T2 state is executed again while keeping the state as it is. Furthermore, even at the end of this T2 state, READY
The signal is sampled, and if it is "H" as shown in FIG. 8, this cycle is ended and the next cycle is started. (If it is "L", another wait state is added, and it becomes 2 wait cycles.
Wait states are added until the signal becomes “H”. )

[0010]

As described above, the access control of the CPU provided with the wait state is performed, but during this wait state, the CPU simply wastes time.

Further, the conventional D-RAM refresh controller has to interrupt the CPU cycle in order to refresh the D-RAM as described above.
However, it has a drawback in that it requires a large-scale control circuit at the same time as it has a low operating efficiency.

The present invention has been made in order to eliminate such a drawback of the conventional D-RAM refresh control device, and it is not necessary to execute a special refresh cycle, and therefore, a complicated control circuit therefor is required. An object of the present invention is to provide a D-RAM refresh control device capable of refreshing the D-RAM without requiring reduction in the operating efficiency of the CPU by utilizing the wait state period of the CPU.

[0013]

SUMMARY OF THE INVENTION A D-RAM refresh control device according to the present invention comprises a detecting means for detecting a wait state during a read cycle of a CPU with respect to a D-RAM, and the CPU detected by the detecting means. RA for setting the RAS signal supplied from the D-RAM controller controlled by the CPU to the D-RAM to a non-active state for a predetermined period during the wait state.
S signal control means is provided.

Further, after the detecting means detects the wait state of the CPU, it starts the time counting operation,
A timer is provided which outputs a signal for adding refresh when a predetermined time is measured.

Further, a timer that repeats the time counting operation within a set time, and the weight
A counter that counts the number of D-RAM read cycles including states and outputs a signal indicating that when the count value reaches a predetermined value, and a counter that counts when the set time of the timer elapses. When the numerical value is discriminated and the counted value does not reach the predetermined value, a discriminating means for supplying a signal for stopping the time counting operation of the timer to the timer and outputting a signal for adding refresh. Is provided.

Further, a timer that repeats a time counting operation within a set time, a counter that counts the number of read cycles of the D-RAM including the wait state detected by the detecting means, and the set time of the timer. When the count value of the counter reaches the predetermined value before the passage of, the prohibiting means for prohibiting the refreshing within the set time of the timer is provided from this point.

[0017]

The D-RAM refresh controller of the present invention is
When the detecting means detects the wait state during the read cycle of the CPU for the D-RAM, the D-RAM controller controlled by the CPU supplies the wait state to the D-RAM during a predetermined period during the wait state of the CPU. The RAS signal control means brings the RAS signal to the non-active state. As a result, since the hidden refresh of the D-RAM is performed during the wait state of the CPU, it is not necessary to execute a special refresh cycle, a complicated control circuit therefor is not required, and C
The D-RAM can be refreshed without lowering the operating efficiency of the PU.

When a predetermined time elapses after the detecting means detects the wait state of the CPU, the timer outputs a signal for adding refresh. As a result, the hidden refresh of the D-RAM is performed once within the predetermined time set in the timer,
Memory including wait state within the predetermined time
Even at an electronic device that does not generate a read cycle, refresh can be performed at regular intervals.

Further, the counter counts the number of read cycles of the D-RAM including the wait state detected by the detecting means, and the discriminating means discriminates the count value of the counter when the set time of the timer has elapsed. If the count value has not reached the predetermined value, the signal for stopping the time counting operation of the timer is supplied to the timer and the signal for adding refresh is output. As a result, when the refresh operation is not performed a predetermined number of times within the set time, the timer is stopped and the refresh operation is performed up to the predetermined number of times. Therefore, the refresh operation is performed a predetermined number of times within the set time or a time close thereto. It is always performed, and even when the memory read cycle is not executed for a long time within the set time, the refresh can be performed a predetermined number of times.

Further, the counter counts the number of read cycles of the D-RAM including the wait state detected by the detecting means, and within the set time of the timer after the counted value reaches a predetermined value. , Prohibition means prohibit refresh. As a result, the refresh operation is not performed a predetermined number of times or more within the set time, and the power consumption required for the refresh operation is not wasted.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the D-RAM refresh control device of the present invention.

In FIG. 1, the same components as those of the conventional example of FIG. 6 are designated by the same reference numerals, and the description thereof will be omitted.

CPU unit 1 and memory unit 2
The D-RAM refresh control device 3 of the present embodiment is provided between and.

The D-RAM refresh controller 3 has a C
A 4-input AND gate 5 used as a detecting means for detecting a wait state during a read cycle of the PU D-RAM, and a predetermined one of the wait states of the CPU detected by the 4-input AND gate 5. And a 2-input NAND gate 4 used as a RAS signal control means for bringing a RAS signal supplied from the D-RAM controller controlled by the CPU to the D-RAM into a non-active state for a period.

The input terminal of the 4-input AND gate 5 has a REDY signal with negative logic, a CAS signal with negative logic, and a W signal with positive logic.
The E signal and the CLK signal with positive logic are input respectively. Four
The output terminal of the input AND gate 5 is connected to one input terminal of the 2-input NAND gate 4 in negative logic, and the RAS signal is input to the other input terminal of the 2-input NAND gate 4 in negative logic.

FIG. 2 is a timing chart of this embodiment.

As shown in FIG. 2, in the present embodiment,
CLK signal is "H" level, WE signal is "H" level,
When the CAS signal becomes the "L" level and the REDY signal becomes the "L" level and the wait state TW is reached during the read cycle of the D-RAM of the CPU, the output signal level of the AND gate 5 becomes the "H" level. Become. As a result, the output signal level of the NAND gate 4 becomes "H" level,
The RAS signal input to the memory unit 2 is in the non-active state. This non-active state is CL
It is canceled at the fall of the K signal, and the D-RAM in the memory unit 2 is hidden refreshed from the latter half of this TW state to the T2 state.

In this embodiment, the refresh control device 3 is constructed as an independent circuit unit, but this is a CP.
It may be incorporated in the D-RAM controller in the U unit.

According to this embodiment, the operating speed of the CPU is high, one or more wait states are required for the memory read cycle, and a memory read cycle including such a wait state is executed. , The D-RAM is applied to an electronic device that is executed a predetermined number of times or more within a predetermined time defined by the standard for refreshing the D-RAM, so that the CPU cycle is interrupted and a special refresh Since the refresh is automatically performed without executing the cycle, the operation efficiency of the CPU is not lowered.

Further, the refresh control device can be constructed with a simple logic circuit configuration.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing the circuit configuration of the second embodiment of the present invention. 3, the same components as those of the first embodiment of the present invention shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In the D-RAM refresh control device 3 of the present embodiment, after the AND gate 5 detects the wait state state of the CPU, the clocking operation is started, and when the predetermined time (15 μsec) is measured, it becomes “H”. A level timeout signal (hereinafter abbreviated as "TO signal") is a wait request terminal (hereinafter abbreviated as "WAITRQ terminal") of the D-RAM controller in the CPU unit 1.
To the D-RAM read cycle.
A timer 6 is provided for instructing to insert a state. The reset terminal of the timer 6 is connected to the output terminal of the AND gate 5, and is reset when the output level of the AND gate 5 becomes “H” (that is, reset at the last refresh operation), and then a new time measurement is performed. start. When there is no next reset input for 15 .mu.sec (that is, the next refresh operation is not performed), the "H" level TO signal is output and stopped. The TO signal is input to the WAITRQ of the memory controller in the CPU unit (when the input signal level of this terminal is "H", one wait state period is inserted in the memory read cycle), Request to insert wait state forcibly in the next memory read cycle. In response to that, D-RA
The M controller is ready for the next memory read cycle.
By inserting the wait state, the hidden refresh operation similar to that described in the first embodiment is added.

In this embodiment, the predetermined time of the timer is set to 15
μsec is defined as, for example, the standard for refreshing the target D-RAM is 256 refresh / 4.
In the case of msec (refreshing is required at least 256 times within 4 msec) and refreshing is performed at regular intervals of 256 times within 4 msec according to this standard, 4 ms / 256
This is because it is necessary to perform refreshing once or more within 15.6 μsec, and when various loss times such as signal delay are set to 0.6 μsec, the predetermined time of the timer becomes 15 μsec. That is, 15.6 μs
During ec, memory memory including wait state even once
Even in the case of an electronic device in which no read cycle occurs, according to the present embodiment, the wait state can be forcibly requested and the D-RAM can be refreshed.

In this embodiment, the hidden refresh method is adopted as the refresh operation to be added, but it goes without saying that another refresh method such as CAS before RAS refresh may be adopted.

Next, a third embodiment of the present invention will be described.

FIG. 4 is a block diagram showing the circuit configuration of the third embodiment of the present invention. 4, the same components as those of the first embodiment of the present invention shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

The D-RAM refresh control device 3 of the present embodiment includes a timer 7 that repeats a timing operation within a preset time (3.7 msec) and a D-RAM including a wait state of the CPU detected by the AND gate 5. -The number of RAM read cycles is counted, and the counted value is a predetermined value (25
6) When the counter 8 outputs a signal indicating that when it reaches 6) and the count value of the counter 8 when the set time of the timer 7 has elapsed, the count value does not reach the predetermined value. In this case, a signal for stopping the time counting operation of the timer 7 is supplied to the timer and
-D- which outputs a signal for instructing to insert a wait state in the read cycle for RAM-
A flip-flop circuit 9 is provided.

The counting terminal CK of the counter 8 is connected to the output terminal of the AND gate 5, and outputs an "H" level signal until the counter 8 counts a predetermined count value and counts up to a predetermined value. After that, the output terminal CO that outputs a signal of "L" level is connected to the D input terminal of the D-flip-flop circuit 9 and the clear terminal (CLR terminal) that is cleared by the "L" level signal. D-flip
The Q output terminal of the flop circuit 9 is an enable (EN) terminal of the timer 7 (when the input signal of the EN terminal is at "L" level, the timer 7 performs its time counting operation, and when it is at "H" level, the timer 7 is set to " It is connected to the WAITRQ terminal of the CPU unit 1 while maintaining the state immediately before it becomes H ″ level). The TO output terminal of the timer 7 is the reset (RES) terminal of the counter 8 and the D-flip-flop circuit 9
Is connected to the clock (CK) terminal.

Next, the operation of this embodiment will be described.

The timer 7 continuously measures time for a preset 3.7 msec when the input signal level of the EN terminal is at "L" level, and T is counted every time the time of 3.7 msec is completed.
A TO signal which is a positive pulse signal is output to the O terminal. E
When the input signal of the N terminal is at "H" level, the state immediately before the signal becomes "H" level is maintained.

The counter 8 counts the rising edge of the output signal of the AND gate 5 every time when the output signal of the AND gate 5 becomes "H" level and the CPU executes the read cycle including the wait state, and the TO signal of the timer 7 is output. Reset on falling edge. After that, the counting operation is started again by the output signal from the AND gate 5, and when counting up to 256, the counting operation is continued until the falling edge of the next TO signal is input while keeping the signal level of the CO terminal at the “L” level. Stop.

The D-flip-flop circuit 9 samples the output signal from the CO terminal of the counter 8 at the rising edge of the TO signal output when each timer 7 completes timing.

The CPU unit 1, the memory unit 2, the AND gate 5 and the NAND gate 4 perform exactly the same operation as in the first embodiment, and execute the necessary refresh operation. Then, the timer 7, the counter 8 and the D-flip-flop circuit 9 monitor and control the execution status of the refresh operation. That is, the timer 7 is 3.7
TO signal output every msec, 3.7 msec
The output signal from the CO terminal of the counter 8 which counts the number of refreshes executed during the period is sampled by the D-flip-flop circuit 9 to check the number of refreshes within the set time.

If refresh is performed 256 times or more, the D-RAM standard has already been satisfied, so that the output signal level of the CO terminal of the counter 8 becomes "L" level, and the output signal is The signal is input to the CLR terminal of the D-flip-flop circuit 9, clears the D-flip-flop circuit 9 (sets the output signal level of the Q terminal to "L" level), and changes the signal level of the WAITRQ terminal of the CPU unit 1. By setting it to the "L" level, the CPU does not request a wait cycle.

On the contrary, if 3.7 msec.
When only refreshing is performed less than or equal to the number of times, the signal level at the CO terminal of the counter 8 is "H", which is sampled by the D-flip-flop circuit 9 and Q-valued by the D-flip-flop circuit 9. The output signal level of the terminal becomes "H" level, the signal level of the WAIRQQ terminal of the CPU unit 1 becomes "H", and the CPU is forced to insert the wait state in the subsequent memory read cycle. Request and thereby
Add hidden refresh.

This request is maintained until the counter 8 counts 256, the signal at the CO terminal becomes "L" level, and the D-flip-flop circuit 9 is cleared. That is, the refreshes of less than 256 times (the number of times of the difference between the predetermined value and the count value of the counter 8) are collectively added.

In this way, it is always 25 within 4 msec.
You can refresh 6 times or more.

This embodiment is set even in a system in which a memory read cycle may not be executed for a long time (15.6 μsec or more and 3.7 msec or less) (for example, when using DMA in Block transfer mode). Since a certain number of refresh operations are always performed within the specified time,
The present invention can be applied to virtually any system.

Next, a fourth embodiment of the present invention will be described.

FIG. 5 is a block diagram showing the circuit configuration of the fourth embodiment of the present invention. 5, the same components as those of the third embodiment of the present invention shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, the AND gate 5'is provided with the enable terminal EN, and the enable terminal EN is connected to the CO terminal of the counter 8. The output signal level of the AND gate 5'is always kept at "L" level when the input signal level of the enable terminal EN is "L" level.

With this configuration, in this embodiment, when the counter 8 counts a predetermined number of refresh operations and the output signal level of the CO terminal of the counter 8 becomes "L" level, that is, 3.7 msec. If the refresh operation is completed 256 times before the time is less than, the signal level of the EN input terminal of the AND gate 5 ′ becomes “L” level, and the signal level of the output terminal of the AND gate 5 ′ becomes “L”. It is kept at the level and the refresh operation thereafter is prohibited. This state is maintained until the timer 7 measures a preset value (3.7 msec), the TO signal output as a result resets the counter 8, and the signal level at the CO terminal becomes "H" level. To be done.

With the above operation, in the present embodiment, 3.7.
Every msec to 4.0 msec, the refresh is performed exactly 256 times. As a result, D-RA
It is possible to perform the minimum necessary refresh prescribed by the standard regarding the refresh of M, prevent unnecessary refresh, and save power consumption.

[0056]

In the D-RAM refresh control device of the present invention, the wait state is detected during the memory read cycle of the CPU, and the hidden refresh is performed during the read cycle, so that the CPU cycle is interrupted. D-RAM can be refreshed without sacrificing the efficiency of the CPU.
Moreover, the above-described functions can be realized with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a timing chart of each signal in the embodiment of FIG.

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing a circuit configuration example of access control of a conventional D-RAM.

FIG. 7 is a timing chart of each signal of the circuit shown in FIG.

8 is a timing chart of each signal of the circuit shown in FIG.

[Explanation of symbols]

 1 CPU unit 2 Memory unit 3 D-RAM refresh controller 4 NAND gate 5 AND gate 6,7 Timer 8 Counter 9 D-flip-flop circuit

Claims (4)

[Claims] 1. A detection means for detecting a wait state during a read cycle of a CPU for a D-RAM,
A RAS signal that makes the RAS signal supplied from the D-RAM controller controlled by the CPU to the D-RAM non-active for a predetermined period during the wait state of the CPU detected by the detecting means. A D-RAM refresh control device provided with a control means. 2. A timer for outputting a signal for adding refresh when the detecting means starts a time counting operation after detecting the wait state of the CPU and measures a predetermined time. The described D-RAM refresh controller. 3. A timer that repeats a time counting operation within a set time, and the number of read cycles of the D-RAM including the wait state detected by the detecting means is counted, and the counted value becomes a predetermined value. When the count value of the counter is discriminated when the preset time of the timer has elapsed and the counter that outputs a signal indicating that when the count value has not reached the predetermined value, the count value of the timer While supplying a signal to the timer to stop the timekeeping operation,
The D-RAM refresh control device according to claim 1, further comprising: a determination unit that outputs a signal for adding refresh. 4. A timer that repeats a time counting operation within a set time, a counter that counts the number of D-RAM read cycles including the wait state detected by the detecting means, and the set time of the timer. When the count value of the counter reaches the predetermined value before the passage of
2. The D-RAM refresh control device according to claim 1, further comprising a prohibition unit that prohibits refreshing within a set time of the timer from this point.