JPH10302460A - Microcontroller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a hard perform an access by releasing the self-refresh state of a DRAM with the autonomy of the hard in a microcontroller controlling the self-refresh state of the DRAM while transmitting strobe signals based on the data written in a register. SOLUTION: This microcontroller makes the DRAM be in a self-refresh state when the data written in a register 44 are, for example, 'H'. In the case an access with respect to the DRAM becomes necessary, a decoder 41 detects the necessity to generate an access request signal acsREQ being 'H'. When the signal acsREQ becomes 'H', and AND gate 45 makes holding information of the register 44 an 'L' forcibly. As a result, strobe signals RAS, CAS are changed to release the self-refresh state of the DRAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynami
The present invention relates to a microcontroller provided with a DRAM controller for controlling c Random Access Memory.

[0002]

2. Description of the Related Art Conventionally, as a technique in this field, for example, there is a technique described in the following literature. Literature; Edited by Hitachi Microcomputer Systems, Inc. “SH760
4 Hardware Manual, 1st Edition (Heisei 6-9), published by Hitachi, Ltd., P / 160-161. The above document describes a method for controlling self-refresh performed by a DRAM. , Conventional DRAM
FIG. 2 is a configuration block diagram illustrating an example of a microcontroller including a controller.

This microcontroller has a CPU (Ce
ntral Processor Unit) 1 and clock controller 2
, R0M (Read Only Memory) 3, a DRAM controller 4, and a bus controller 5, which are connected to each other by an address bus B1 and a data bus B2. The CPU 1 reads and executes a program on the ROM 3. Clock controller 2
Supplies a clock CK to the CPU 1, the ROM 3, the DRAM controller 4, and the bus controller 5, and has a function of stopping supply of the clock CK in order to reduce power consumption in accordance with an instruction from the CPU 1. doing. The DRAM controller 4 supplies an external bus B to the DRAM directly connected to the microcontroller.
3 and a function to access via
It has a function to periodically refresh the AM. Further, the DRAM controller 4 has a function of receiving the signal write from the CPU 1 and putting the DRAM into a self-refresh state. The bus controller 5
It controls the data bus B2 and the external bus B3 connecting them.

FIG. 3 shows a DRAM controller 4 shown in FIG.
FIG. 2 is a configuration block diagram showing a main part of FIG. The DRAM controller 4 includes an address decoder (decoder) 4a connected to the address bus B1, and a two-input selector 4b. A strobe signal control circuit 4c is connected to the output side of the address decoder 4a, and a self-refresh strobe signal control register 4d composed of a delay flip-flop (DFF) is connected to the output side of the selector 4b.
Is connected. The output terminal of the register 4d is connected to the strobe signal control circuit 4c, and the selector 4b
Are connected in a feedback manner to one of the input terminals. Selector 4b
Is configured to use the signal write from the CPU 1 as a selection signal, select the data DT _4d fed back from the register 4d or the data DT ₁ given from the CPU ₁ , and output the selected data to the register 4d. The strobe signal control circuit 4c stores the data DT _4d and the address decoder 4
a strobe signals RAS and CAS corresponding to the output signal
Is output. Next, the operation of the conventional microcontroller will be described.

When accessing the DRAM, C
PUl transfers the address corresponding to the DRAM to the address bus B.
Output to 1. The address decoder 4a in the DRAM controller 4 decodes and monitors the address.
As a result of decoding the address, if it is determined that it is necessary to access the DRAM, the address decoder 4a sends an access request acsREQ to the strobe signal control circuit 4c. Upon receiving the access request acsREQ, the strobe signal control circuit 4c activates the strobe signal RAS first (sets it to an asserted state) so that the DRAM can access, and then sets the strobe signal CAS to the asserted state. Thereby, access is instructed to the DRAM.
At this time, the bus controller 5 sets the address bus B
The address for the DRAM on 1 is divided into two and output via the external bus B3. The access to the DRAM is executed in this manner.

When the DRAM is put into a self-refresh state in which the DRAM is self-refreshed, the DRAM controller 4 uses the strobe signals RAS and CAS to output the DR.
Instruct AM. In this case, CPUL with indicating "1" in the signal write, for example, the data DT ₁ "H"
Is shown. When the signal write is "1", the selector 4b gives the register 4d select the data DT _1. The register 4d takes in "H" data in synchronization with the clock CK. That is, "H" data is written to the register 4d. The register 4d holds the written data,
The signal is given to the strobe signal control circuit 4c. The strobe signal control circuit 4c asserts the strobe signals RAS and CAS and outputs the signal to the DRAM so that the DRAM performs self-refresh. That is, the strobe signal CAS
Is asserted first, and the strobe signal RAS is asserted. Conversely, when returning the DRAM from the self-refresh state to the normal operation state, the CPU 1
And the data DT ₁ "L" from is performed by writing the data of "L" for the self-refresh state release to the register 4d.

On the other hand, the procedure for the microcontroller to stop the clock and shift to the power consumption reduction mode is to first set the instruction of the CPU 1 (set the signal write to "1" and set the data DT1 to "H"). That), D
"H" data is written into the register 4d so that the DRAM enters the self-refresh state with respect to the RAM controller 4, and the strobe signals RAS and CAS are asserted so that the DRAM performs the self-refresh. Thereafter, the supply of the clock CK to the clock controller 2 is stopped according to a command from the CPU 1, and the transition to the power consumption reduction mode is completed. The procedure in which the microcontroller resumes the supply of the clock CK and shifts from the power consumption reduction mode to the normal operation mode is performed after the clock controller 2 resumes the supply of the clock CK due to the occurrence of an interrupt or the like and then issues a command (signal write Is set to "1" and the data DT1 is set to "L".
Is written in the register 4d to release the self-refresh operation mode, and the strobe signal is released.

[0008]

However, the conventional microcontroller has the following problems (1) to (3). (1) When the operation mode of the microcontroller is not the power consumption reduction mode but the normal mode,
If an attempt is made to access the DRAM while the RAM is performing self-refresh, writing of data to the DRAM and reading of data from the DRAM are not performed correctly, and subsequent operation of the microcontroller is not guaranteed. . To prevent this, DRAM
Before accessing the DRAM, an instruction for returning the DRAM from the self-refresh state to the normal state is always executed.
It needed to access RAM. (2) When the microcontroller shifts to the power consumption reduction mode and puts the DRAM in a self-refresh state, the DRA is
Strobe signal R such that M performs self-refresh
If only the command to shift to the power consumption reduction mode is issued without issuing an instruction from CPU 1 for generating AS and CAS, the DRAM does not perform self-refreshing, and
Will be destroyed. In order to prevent this, it is necessary to generate strobe signals RAS and CAS such that the DRAM enters a self-refresh state before the clock CK is stopped.

(3) When the microcontroller is returned from the power consumption reduction mode to the normal operation mode to bring the DRAM into the normal state, that is, the clock controller 2 restarts the supply of the clock CK by an external interrupt or the like,
When shifting from the power consumption reduction mode to the normal operation mode, it is necessary to return the self-refresh state of the DRAM to the normal operation state. At this time, if the data "L" for canceling the self-refresh is not written in the register 4d so that the DRAM enters the normal operation state with respect to the DRAM controller 4 in accordance with the instruction of the CPU 1, the DRAM does not perform the self-refresh. Remains in a state. Therefore, subsequent DRAM access is not performed correctly. In order to prevent this, if the supply of the clock CK is always restarted by the program, the DRAM
Had to be returned to the normal operating state. The above (1)-
As in (3), the conventional microcontroller has a problem that the load on the program is large and the program is complicated.

[0010]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a connected DRAM.
Has a first terminal for outputting a first strobe signal, a second terminal for outputting a second strobe signal, and an address terminal for transferring an address.
And activating the second strobe signal at a predetermined timing and transferring an address to the DRAM,
Function to execute the access, and D based on the program
In a microcontroller having a function of activating the first and second strobe signals at a timing different from the case of performing access to the RAM and causing the DRAM to perform self-refresh, the following register, decoder, state A setting circuit, a strobe signal control circuit, and an address transfer unit are provided. The register holds the first state or the second state set by the program. The decoder is connected to the address bus and has a function of generating an access request when an address for the DRAM is detected on the address bus. The state setting circuit is connected to the decoder, and forcibly sets the state held by the register to the second state when the decoder generates an access request.

The strobe signal control circuit is connected to the register and the decoder, and activates the first and second strobe signals so that the DRAM performs a self-refresh when the first state is input from the register, and Is changed from the first state to the second state, the first and second strobe signals are changed to change the DR state.
When the self-refresh in the AM is canceled and an access request is input from the decoder while the second state is being input from the register, the first and second strobe signals are activated so that the DRAM accesses. Has a function. The address transfer means transfers the address on the address bus to the DRAM via the address terminal when the strobe signal control means activates the first and second strobe signals to access the DRAM. Has become. According to a second aspect, a microcontroller includes a clock control circuit, a register, a mode setting circuit, a decoder, a strobe signal control circuit, and address transfer means.

The register, decoder, strobe signal control circuit and address transfer means are the same as in the first invention. The clock control circuit has a function of supplying a clock to an internal circuit of the microcontroller and setting a normal operation mode, and a function of stopping supply of the clock and setting a power consumption reduction mode in the internal circuit. When the supply of the clock is stopped, a clock supply stop signal is output. The mode setting circuit forcibly sets the state held by the register to the first state when the clock supply stop signal is output from the clock control circuit. The third invention is the second invention
The mode setting circuit of the invention of the present invention has a configuration in which the clock control circuit stops outputting the clock supply stop signal when the DRAM starts self-refreshing by outputting the clock supply stop signal by the clock control circuit. I have. According to a fourth aspect, the state setting circuit according to the first aspect is provided in the microcontroller according to the second or third aspect.

According to the first invention, since the microcontroller is configured as described above, when accessing the DRAM, the occurrence of an address for the DRAM is detected by the decoder, and an access request is generated. For example, even when the DRAM is in the self-refresh state, the state setting circuit receiving this access request can
The holding state of the register is forcibly set to the second state. When the register enters the second state, the self-refresh state is released. Then the correct DRAM
Is accessed.

According to the second aspect, the clock control circuit outputs the clock supply stop signal when stopping the clock. The register is forced to hold the first state by the mode setting circuit that has received the clock stop signal. When the register holds the first state, the strobe signal control circuit outputs the first and second strobe signals so that the DRAM enters a self-refresh state. According to the third aspect, the clock supply stop signal in the clock control circuit stops when the DRAM starts self-refreshing as a result of generating the clock supply stop signal. Therefore, the holding state of the register is not forced, and the register holds the second state when, for example, the supply of the clock is restarted. That is, the self-refresh state is released. Therefore, the above problem can be solved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 4 is a block diagram showing a configuration of a microcontroller according to a first embodiment of the present invention. This microcontroller includes a CPU 10 for executing a program, a clock controller 20 as a clock control circuit, an R0M30 storing the program, and a DRAM controller 4.
0 and a bus controller 50 as an address transfer means, which are connected to each other by an address bus B1 and also to each other by a data bus B2. CP which is the internal circuit of the microcontroller
The U10, the ROM 30, the DRAM controller 40, and the bus controller 50 include a clock controller 20.
Are connected to receive a clock CK. The clock controller 20 has a function of stopping supply of the clock CK in response to an instruction from the CPU 10 to reduce power consumption, for example. The DRAM controller 40 has a DRAM connected directly to this microcontroller.
In order to access the RAM 60 via the external bus B3, the first strobe signal RAS and the second strobe signal CAS are output from the first terminal T1 and the second terminal T2, respectively. Strobe signal RA
It has a function of self-refreshing the DRAM 60 using S and CAS. Bus controller 50
Controls the data bus B2 and the external bus B3 connecting them. The external bus B3 has an address terminal T3
Is connected to the DRAM 60 via the.

FIG. 1 is a diagram showing a main part of a DRAM controller in a microcontroller according to a first embodiment of the present invention, and shows a DRAM controller 40 in FIG. The DRAM controller 40 includes an address decoder (decoder) 41 connected to the address bus B1.
And a two-input selector 42. On the output side of the address decoder 41, a strobe signal control circuit 43
The self-refresh strobe signal control register 44 composed of a delay flip-flop (DFF) is connected to the output side of the selector 42.
The output terminal of the register 44 is connected to the strobe signal control circuit 4
3 and a 2-input A which is a state setting circuit.
It is connected to one input terminal of the ND gate 45. A
The ND gate 45 is newly provided instead of the conventional microcontroller. A signal obtained by inverting the output signal of the address decoder 41 is input to the other input terminal of the AND gate 45. ing. AND
An output terminal of the gate 45 is connected to one side of the selector 42 by feedback. The other input terminal of the selector 42 has C
The data DT10 given from the PU ₁₀ is input. The selector 42 is configured to receive a signal write from the CPU 10 as a selection signal.

On the output side of the strobe signal control circuit 43,
Terminals T1 and T2 are provided, and two strobe signals RAS and CAS for accessing the DRAM 60 are output from the terminals T1 and T2. DRA is determined by the state of strobe signals RAS and CAS.
M60 is set to an accessible normal state or a self-refresh state for performing a self-refresh. Next, the operation of the microcontroller will be described. DRAM
When accessing the CPU 60, the CPU 10
The address AD corresponding to the AM 60 is output to the address bus B1. An address decoder 41 in the DRAM controller 40 decodes and monitors the address AD. When the address decoder 41 determines that it is necessary to access the DRAM 60 as a result of decoding the address AD, the address decoder 41 outputs an access request acsSREQ to the strobe signal control circuit 43. In response to the access request acsREQ, the strobe signal control circuit 43 outputs the strobe signal RAS
Is first set to the “L” level of the assertion, and then the strobe signal CAS is set to “L”. Thereby, DR
Access is instructed to AM 60. At this time, the bus controller 50 divides the address for the DRAM 60 into two parts and divides the address into the DRAM 60 via the external bus B3.
Give to 0. In the DRAM 60, the strobe signal RA
Access is performed based on S, CAS and address.

The microcontroller brings the DRAM 60 into a normal operation state in which it can be accessed or into a self-refresh state depending on how strobe signals RAS and CAS are applied. FIG. 5 is a time chart showing an operation example of the microcontroller shown in FIG. 4. Referring to FIG. 5, the DRAM 60 is set from the normal operation state to the self-refresh state, and the self-refresh state is released to release the DRAM 60. The operation in the case where the user performs the access will be described. When the microcontroller is operating in normal mode instead of power saving mode, DRA
It is assumed that the register 44 in the M controller 40 holds the second state “L”. When the DRAM 60 is set to the self-refresh state, as shown in FIG.
PU10 outputs the address AD ₄₄ addressed register 44 to the address bus B1. At the same time, the signal writ of "1"
e and the data DT ₁₀ of “H” are given to the selector 42, and the selector 42 selects the data DT ₁₀ and
Give to 4. Therefore, the register 44 holds and outputs the first state “H”. Strobe signal control circuit 4
3 sets the strobe signal CAS to "L" for assertion first based on "H" given from the register 44,
Subsequently, the strobe signal RAS is set to an asserted “L”. Thereby, DRAM 60 is set to a self-refresh state.

When the DRAM 60 is in the self-refresh state, the CPU 10 operates at the address A corresponding to the DRAM 60.
And outputs a D ₆₀ to the address bus B1, the address decoder 41 in the DRAM controller 40, an address AD
Detecting that ₆₀ has arrived, it is determined that access to DRAM ₆₀ is necessary. Then, the address decoder 41 generates an access request acsREQ of “H” level. When the access request acsREQ occurs, the output signal of the AND gate 45 becomes "L", and the holding state of the register 44 is forcibly changed from "H" to "L". Register 4
4 becomes “L”, the strobe signal control circuit 43 returns the levels of the strobe signals RAS and CAS to “H”, cancels the self-refresh state of the DRAM 60, and temporarily returns to the normal operation state. Subsequently, the strobe signal control circuit 43 first sets the strobe signal RAS to an asserted “L” level and sets the strobe signal CAS to “L”. Thereby, DRAM
Access is instructed to the DRAM 60, and the DRAM 60 is accessed.

As described above, in the first embodiment,
An AND gate 45 for setting the information held in the register 44 to “L” when an access request acsREQ is generated is provided. It is possible to shift to the normal operation state without writing and holding “L”. Therefore, correct access is possible without releasing the self-refresh state by an instruction from the CPU 10. Therefore, for example, in a program for accessing the DRAM 60 in a self-refresh state, an effect is obtained that runaway and stop of the microcontroller caused by a bug can be prevented.

Second Embodiment FIG. 6 is a block diagram showing the configuration of a microcontroller according to a second embodiment of the present invention. This microcontroller includes a CPU 70 for executing a program, a clock controller 80 as a clock control circuit, an R0M 90 storing the program, and a DRAM controller 1.
00 and a bus controller 120, which are connected to each other by an address bus B1 and a data bus B2 in the same manner as in the first embodiment. CPU 70, ROM 90, DR which are internal circuits of the microcontroller
AM controller 100 and bus controller 120
Is supplied with a clock CK from the clock controller 80. Clock controller 80
Has a function of stopping the supply of the clock CK in order to reduce power consumption in response to an instruction from the CPU 10. The clock controller 80 differs from the first embodiment in that when the supply of the clock CK is stopped,
The asserted clock supply stop signal stopREQ is supplied to the RAM controller 100, and the asserted clock stop acknowledge signal stopACK, which is a response signal resulting from the application of the clock supply stop signal stopREQ, is input from the DRAM controller 100. Connected. When the clock stop acknowledge signal stopACK is input, the output of the asserted clock supply stop signal stopREQ is stopped.

The DRAM controller 100 includes a DRAM 13 directly connected to the outside of the microcontroller.
0 to output the first and second strobe signals RAS and CAS in order to access the DRAM 130 via the external bus B3. Is set to a self-refresh state. The bus controller 120 controls the data bus B1 and the external bus B3 connecting them. Strobe signal RA
S and CAS are connected from the first and second terminals T1 and T2 to DR.
The connection is provided to the AM 130. External bus B
3 transfers the address to the DRAM 130, and the external bus B3 is connected to the DRA via the address terminal T3.
M130. FIG. 7 shows the DRAM in FIG.
FIG. 3 is a diagram illustrating a main part of the controller 100. The DRAM controller 100 includes an address decoder (decoder) 101 connected to the address bus B1, a two-input selector 102, a strobe signal control circuit 103 connected to the output side of the address decoder 101, and a delay flip-flop (DFF). ) And a self-refresh strobe signal control register 104. Further, the DRAM controller 100 includes an AND gate 105 functioning in the same manner as in the first embodiment and a mode setting circuit 110 newly provided for the first embodiment.
Are provided.

Unlike the first embodiment, the strobe signal circuit 103 receives the clock supply stop signal stopREQ and outputs a clock stop acceptance signal stopACK which is a response signal to the clock supply stop signal stopREQ. I have. The mode setting circuit 110 includes an inverted signal of the clock supply stop signal stopREQ and a clock stop acceptance signal stop.
ACK as input, a clock supply stop signal stopREQ and a clock stop acknowledge signal stopACK
And an AND gate 112 which receives the inverted signal of the AND gate 112 as an input. The output terminal of the NAND gate is connected to the selector 10
Two-input AN with one input terminal connected to two output terminals
It is connected to the other input terminal of D gate 113. A
The output terminal of the ND gate 112 is a two-input OR gate 11 that inputs the output signal of the register 104 to one input terminal.
4 is connected to the other input terminal. AND gate 11
3 is connected to the input terminal of the register 104. The output terminal of the OR gate 114 is connected to one input terminal of the two-input AND gate 105.

The other input terminal of the AND gate 105 is a connection to which an access request acsREQ output from the decoder 101 is input, and the output terminal of the AND gate 105 is connected to one input terminal of the selector 102. .
Data DT ₇₀ from the CPU ₇₀ is input to the other input terminal of the selector 102. Also,
The selector 102 has a command signal wr from the CPU 70.
ite is input as a selection signal. The strobe signal control circuit 103 includes two strobe signals RAS and C for accessing the DRAM 130.
It has a function of outputting an AS and a function of outputting an asserted clock stop acknowledge signal stopACK. Depending on the state of strobe signals RAS and CAS, DR
AM 130 is set to a normal operation state or a self-refresh state. Next, the operation of the microcontroller will be described. The microcontroller shown in FIG. 6 operates in the normal mode by generating the clock CK in the clock controller 80, and in the case where the clock supply from the clock controller 80 is stopped by an instruction from the CPU 70 to set the power consumption reduction mode. There is.

In the normal operation mode, the CPU 70,
Clock controller 80 and bus controller 120
And a decoder 101 in the DRAM controller 100,
The selector 102, the strobe signal control circuit 103, the register 104, and the AND gate 105 constitute the CPU 10, the clock controller 20, the bus controller 50, the decoder 41, the selector 42, the strobe signal control circuit 43, the register 44, and the AND of the first embodiment. Gate 4
The operation is the same as in the case of FIG. Therefore, the operation of setting the DRAM 130 to the self-refresh state and the operation of releasing the self-refresh state to return to the normal operation state,
The operation of accessing the AM 130 is performed in the same manner as in FIG. FIG. 8 is a time chart showing the transition to the power consumption reduction mode and its release in the microcontroller of FIG.

When the microcontroller shifts to the power consumption reduction mode, the DRAM 130 is set to a self-refresh state. When the microcontroller is in the normal mode before setting the self-refresh state, the register 104 in the DRAM controller 100
Holds “L” as shown in FIG. Immediately before the microcontroller shifts to the power saving mode, the clock controller 80 controls the clock supply stop signal stopRE.
Q is set to “H” level. Thereby, the AND gate 1
12 also becomes “H”, the output of the OR gate 114 becomes “H”, and the output of the AND gate 105 becomes “H”. At this time, the output of the NAND gate 111 is also “H”,
“H” is forcibly written to the register 104. The register 104 outputs “H” to the strobe signal control circuit 103.
The signal of is output. The strobe signal control circuit 103
Just like the DRAM 120 performs self-refresh,
The level of the strobe signal CAS is set to "L" for assertion, and the strobe signal RAS is set to "L". Thereafter, the strobe signal control circuit 103 asserts the clock stop acknowledge signal stopACK to make it "H". “H”
Is given to the clock controller 80, and the clock controller 80 sets the level of the clock supply stop signal stopREQ to "L" and stops the supply of the clock CK. Thus, the microcontroller completes the transition to the power consumption reduction mode. When the transition to the power consumption reduction mode is performed, the NAND1
The output signal becomes "L".

When the microcontroller releases the power consumption reduction mode and shifts to the normal mode, the
130 is set to the normal operation state. For example, when the clock controller 80 resumes the supply of the clock CK due to an external interrupt, the output signal of the NAND gate 111 is “L” and the holding state of the register 104 is “L” because the clock stop request signal stopREQ is “L”. L ”. In response, the strobe signal control circuit 103
Changes the clock stop acknowledge signal stopACK from “H” to “L”.
To the strobe signal R for self-refresh.
AS and CAS are negated to “H” and the DRAM 130
Is released from the self-refresh state. With this operation, the mode shifts from the power consumption reduction mode to the normal operation mode.

As described above, in the second embodiment,
When the power consumption reduction mode is set, the clock supply stop signal stopREQ asserted by the clock controller 80 is set.
And the clock supply stop signal
Input stopREQ to change the holding state of register 104 to “H”.
Mode setting circuit 110 is provided, so that when the microcontroller shifts to the power saving mode, the DRA
When M130 is in the self-refresh state,
It is not necessary to write “H” to the register 104 by the instruction of U70, and the strobe signals RAS and CAS can be generated so that the DRAM controller 100 automatically brings the DRAM 130 into the self-refresh state. That is, it is possible to shift the DRAM 130 to the self-refresh state without the instruction of the CPU 70 based on the program. In addition, since the clock controller 80 outputs the asserted clock supply stop signal stopREQ until the asserted clock stop acknowledge signal stopACK is input, the microcontroller returns from the power consumption reduction mode to the normal operation mode. When the clock CK is restarted, the DRAM 130 can be immediately shifted to the normal operation state without executing the instruction of the CPU 70 for setting the DRAM 130 to the normal operation state and writing “L” to the register 104. It is possible. That is, when the microcontroller shifts to the power consumption reduction mode, the DRAM 1
30 goes into a self-refresh state, and the DRAM 130 can be brought into the normal state at the same time as the transition to the normal operation.

The present invention is not limited to the above embodiment, but can be variously modified. For example, the following modifications can be considered. (I) In the first embodiment, the clock controller 2
0, the microcontroller capable of setting the power consumption reduction mode is described. However, even when the power consumption reduction mode is not set, the AND gate 45
By providing such a state setting circuit, the same effect as in the first embodiment can be obtained. (Ii) In the second embodiment, the AND of the first embodiment is used.
Although the AND gate 105 having the same function as the gate 45 is provided, even when the AND gate 105 is not used, when the transition to the power consumption reduction mode and the release thereof are performed, the same as in the second embodiment. The effect is obtained.

[0030]

As described above in detail, according to the first aspect, the register for holding the first state or the second state, the decoder for generating the access request, and the holding state of the register are forcibly set. Since the microcontroller is provided with a state setting circuit for setting to the second state, a strobe signal control circuit, and an address transfer means, when an address to the DRAM is generated, the state of the register is held based on an access request. Is forcibly set to the second state. Therefore, for example, in a program for accessing a DRAM performing self-refresh,
An instruction to write the second state to the register to generate the first and second strobe signals for releasing the self-refresh of the DRAM becomes unnecessary. According to the second invention, a clock control circuit for setting a power consumption reduction mode, a register, a mode setting circuit for forcibly setting the holding state of the register to the first state, a decoder, and a strobe signal control circuit And the address transfer means are provided in the microcontroller, so that the first and second strobe signals for causing the DRAM to perform a self-refresh before shifting to the power consumption reduction mode are written into the register. However, it becomes unnecessary.

According to the third aspect of the present invention, the mode setting circuit according to the second aspect of the present invention is used to control the clock control circuit when the clock control circuit outputs a clock supply stop signal and the DRAM starts self-refreshing. Since the circuit is configured to stop outputting the clock supply stop signal, the first and second strobe signals for releasing the self-refresh of the DRAM when returning the microcontroller from the power consumption reduction mode to the normal operation mode are provided. Instructions to write to registers to generate them are not needed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a main part of a DRAM controller in a microcontroller according to a first embodiment of the present invention.

FIG. 2 is a configuration block diagram showing an example of a microcontroller having a conventional DRAM controller 4 built therein.

FIG. 3 is a configuration block diagram illustrating a main part of a DRAM controller in FIG. 2;

FIG. 4 is a configuration block diagram of a microcontroller according to the first embodiment of the present invention.

FIG. 5 is a time chart illustrating an operation example of the microcontroller of FIG. 4;

FIG. 6 is a configuration block diagram of a microcontroller showing a second embodiment of the present invention.

FIG. 7 is a diagram showing a main part of the DRAM controller 100 in FIG. 6;

FIG. 8 is a time chart showing a transition to a power consumption reduction mode in the microcontroller of FIG. 6 and its release.

[Explanation of symbols]

10, 70 CPU 20, 80 Clock controller 30, 90 RAM 40, 100 DRAM controller 41, 101 Decoder 42, 102 Selector 43, 103 Strobe signal control circuit 44, 104 Register 45, 105 AND gate (state setting circuit) 50, 120 Bus controller 60, 130 DRAM 110 mode setting circuit acsREQ access request AD address stopREQ clock supply stop signal stopACK clock stop acceptance signal CK clock RAS, CAS first and second strobe signals

Claims (4)

[Claims] A first terminal for outputting a first strobe signal to a connected DRAM; a second terminal for outputting a second strobe signal; and an address terminal for transferring an address, based on a program. Activating the first and second strobe signals at a predetermined timing, and
A function of transferring an address to an AM to execute access to the DRAM, and activating the first and second strobe signals at a different timing from the case of executing the access to the DRAM based on the program. The DRA
A microcontroller having a function of causing M to perform a self-refresh operation, comprising: a register for holding a first state or a second state set by the program; and a register connected to an address bus;
A decoder for generating an access request when an address for AM is detected; and a decoder connected to the decoder and forcibly setting the state held by the register to the second state when the decoder generates the access request. A state setting circuit, which is connected to the register and the decoder, and when the first state is being input from the register, the DR
The AM activates the first and second strobe signals so as to perform self-refresh, and when the holding state of the register changes from the first state to the second state, the first and second strobe signals are activated. The DRAM
, The self-refresh is canceled, and the access request is input from the decoder while the second state is being input from the register, so that the first and second strobes are accessed by the DRAM. A strobe signal control circuit for activating a signal; and when the strobe signal control means activates the first and second strobe signals to access the DRAM, the address on the address bus is changed to the address terminal. And an address transfer means for transferring the data to the DRAM via the microcontroller. 2. A semiconductor device comprising: a first terminal for outputting a first strobe signal to a connected DRAM; a second terminal for outputting a second strobe signal; and an address terminal for transferring an address, based on a program. Activating the first and second strobe signals at a predetermined timing, and
A function of transferring an address to the AM to execute access to the DRAM;
A microcontroller having a function of activating the first and second strobe signals at a different timing from the case where the access is executed and causing the DRAM to perform self-refresh. A clock for supplying a clock to the internal circuit, setting a normal operation mode, stopping the supply of the clock, setting a power consumption reduction mode in the internal circuit, and outputting a clock supply stop signal when stopping the supply of the clock. A control circuit; a register for receiving and holding the first state or the second state set by the program in synchronization with the clock; and a register for outputting the clock supply stop signal from the clock control circuit. Forcibly set the state held by the register to the first state A mode setting circuit that is connected to the address bus, the DR on the address bus
A decoder for generating an access request when an address for the AM is detected; and a DRAM connected to the register and the decoder when a first state is input from the register.
Sends a strobe signal for setting a self-refresh state for performing a self-refresh, and changes the first and second strobe signals when the holding state of the register changes from the first state to the second state. Then, the self-refresh in the DRAM is released, and when an access request signal is input from the decoder in a state where the second state is input from the register, the first and second signals are accessed so that the DRAM accesses. A strobe signal control circuit for activating the first and second strobe signals, and an address on the address bus when the strobe signal control means activates the first and second strobe signals to access the DRAM. Address transfer means for transferring the data to the DRAM via the address terminal. Microcontroller. 3. The mode setting circuit, when the clock control circuit outputs the clock supply stop signal and the DRAM starts self-refreshing, the clock control circuit outputs the clock supply stop signal. 3. The microcontroller according to claim 2, wherein the output is stopped. 4. A state setting circuit connected to the decoder, wherein a state setting circuit for forcibly setting a state held by the register to the second state when the decoder generates the access request is provided. The microcontroller according to claim 2.