JPH02159170A - Coding device - Google Patents

Abstract

PURPOSE:To perform a coding process at a high speed by using a means which controls the process action of a deciding/computing circuit and that of a table retrieving circuit independently of each other an in accordance with the state of a corresponding bus and the process state of its own circuit and at the same time setting a temporary memory circuit before the table retrieving circuit to store the output information on the deciding/computing circuit. CONSTITUTION:A temporary memory circuit 10 stores temporarily the coding mode information outputted from a deciding/computing circuit 3 and the run length information (both information called as the mode information hereafter). A sequence control circuit 13 performs the start control, etc., of the circuit 3 based on a prescribed process sequence and in accordance with the states of a picture bus 1 and the circuit 3. The circuit 13 also controls the start of a table retrieving circuit 4 in response to the states of a system bus 5 and the circuit 4. The state control circuits 11 and 12 perform the state control, etc., of the process action of the started circuits 3 and 4 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an encoding device for encoding image data into an MH (Modified Huffman) code, an MR (Modified Read) code, or the like.

2. Description of the Related Art Conventionally, this type of encoding device has generally had a configuration as shown in FIG. 1 is an image bus, 2 is an interface circuit that controls the input of image data from image bus 1, and 3 is an interface circuit that detects changing points in the image data input from image bus 1, performs encoding mode determination and gin length calculation, and 4 is a table search circuit that performs a table search based on the encoding mode information and run length information to create a code, aligns the words of the code data, and outputs the code data; 5; 6 is a system bus; 6 is an interface circuit that controls the output of code data output from the table search circuit 4 to the system bus 5;
7 is a control circuit that controls each part according to a predetermined processing sequence.

Image data is input one word at a time from the image bus 1 through the interface circuit 2 to the judgment/calculation circuit 3, where detection of change points, coding mode judgment, and further run length calculation processing are performed as necessary. When this encoding mode determination/run length calculation processing is completed, table search processing is executed by the table search circuit 4, and code data is output. This code data is output to the system bus 5 via the interface circuit 6. When the output of this encoded data is completed, the next image data is input and the same processing is executed.

Problems to be Solved by the Invention However, with this configuration, the encoding processing time is long;
Another problem is that the encoding processing time varies greatly depending on the bus status.

That is, the encoding mode determination/run length calculation process and the table search process are executed serially. Moreover,
When the table search circuit 4 goes into an output waiting state because the system bus is busy, the judgment/calculation circuit 3 also goes into a waiting state. On the other hand, if the image bus is busy and the system is waiting for input of image data, not only the judgment/calculation circuit 3 but also the table search circuit 4 will be in a waiting state.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an encoding device that is capable of high-speed encoding processing and that has small fluctuations in encoding processing time due to bus input/output wait. do.

In addition, Japanese Patent Application Laid-open No. 61-263370 describes a circuit unit that detects a change point in image data, determines a mode, and calculates a run length, a circuit unit that converts a mode determination result into an 8-bit intermediate code, and a circuit unit that performs change point detection of image data, mode determination, and run length calculation, and a circuit unit that converts the mode determination result into an 8-bit intermediate code. It consists of a FIFO memory that stores run-length information, and a ROM that obtains target code data from the intermediate code and run-length information output from the FIFO memory, and performs encoding mode determination, run-length calculation processing, and encoded data. An encoding device with increased independence from generation processing is shown.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention independently performs the processing operations of the judgment/arithmetic circuit and the table search circuit depending on the state of the corresponding bus and the processing state of its own circuit. The table retrieval circuit has a temporary storage circuit for the output information of the determination/arithmetic circuit in front of the table search circuit.

Operation As described above, the determination/arithmetic circuit and the table search circuit are each independently controlled according to the state of the corresponding bus and the state of its own circuit.

In addition, since the configuration has a temporary storage circuit for encoding mode information and run length information between the judgment/arithmetic circuit and the table search circuit, the table search circuit is in an output waiting state due to the system bus busy. To,
Even when the determination calculation circuit executes encoding mode determination and run length calculation processing for the next image data, the output information is stored in the temporary storage circuit. Next, during the period when the judgment/calculation circuit is in the input waiting state due to the image bus busy, it is possible to have the table search circuit perform a table search using the encoding mode information and run length information stored in the temporary storage circuit. It is.

Therefore, the encoding mode determination/run length calculation process and the table search process can be executed in parallel, and the encoding process time can be shortened by parallelizing the time of each process. Fluctuations can be reduced.

Embodiment FIG. 1 is a schematic diagram of an encoding apparatus according to an embodiment of the present invention, and the same reference numerals as those in FIG. 3 indicate the same parts.

10 is a temporary storage circuit (hereinafter, image information is collectively referred to as mode information) for temporarily storing encoding mode information and run length information (hereinafter, image information is collectively referred to as mode information) output from the determination/arithmetic circuit 3;
register). The mode information output from the determination/arithmetic circuit 3 is input to the table search circuit 4 via this temporary storage circuit IO.

11 is a state control circuit that manages the processing operation state of the judgment/arithmetic circuit 3, and 12 is a state control circuit that manages the processing operation state of the table search circuit 4.

13 is a sequence control circuit for controlling the entire processing sequence. The states of the image bus 1 and the system bus 5 are shown to the sequence control circuit 13 by the respective interface circuits 2 and 6, and the operating states of the judgment/calculation circuit 3 and the table search circuit 4 are shown to the sequence control circuit 13 by the respective state control circuits 11 and 12. Shown in circuit 13.

The sequence control circuit 13 performs activation control of the judgment/calculation circuit 3 according to the state of the image bus 1 and the state of the judgment/calculation circuit 3 according to a predetermined processing sequence, and also controls the start-up of the judgment/calculation circuit 3 according to the state of the system bus 5 and the table search circuit. 4, startup control of the table search circuit 4, etc. is performed. The state management of the processing operations of the judgment/arithmetic circuit 3 and the table search circuit 4 after they are activated is carried out by the respective state control circuits 11.
It is done by 12. Also, the state control circuit 11. 1
Data input/output requests issued from 2.2 are sent to the interface circuit 2.2 via the sequence control circuit 13. 6 gradients are transmitted.

FIG. 2 is a timing diagram of the processing of this encoding device. *AENBL is a start signal for encoding mode determination and run length calculation processing sent from the sequence control circuit 13 to the state control circuit 11, and ACMP is a start signal for encoding mode determination and run length calculation processing sent from the state control circuit 11 to the sequence control circuit 13. The run length calculation processing completion signal, this ARDY, is an input ready signal for image data from the image bus 1 sent from the interface circuit 2 to the sequence control circuit 13,
MOD is mode information (encoding mode information and run length information) stored in the temporary storage circuit 10. Monkey B
ENBL is connected to the state control circuit 1 by the sequence control circuit 13.
Start signal for table search processing sent to 2, signal BCM
P is a table search processing completion signal sent from the state control circuit 12 to the sequence control circuit 13, and BRDY is an output ready signal for code data to the system bus 5, sent from the interface circuit 6 to the sequence control circuit 13. . However, the middle mark in front of the signal name indicates that it is an active low signal.

The operation of this encoding device will be explained with reference to this timing diagram.

When the user instructs the start of the encoding process, the sequence control circuit 13 first turns on AENBL and starts the encoding mode determination/run length calculation process (point a in FIG. 2).

The state control circuit 11 requests the sequence control circuit 13 to input image data, but here the umbrella ARDY is on and image data can be input from the image bus 1. Therefore, image data is input from the image bus 1 to the determination/calculation circuit 3 via the interface circuit 2, and under the control of the state control circuit 11, the encoding mode is determined by detecting a change point and run length calculation is executed as necessary. be done.

When this encoding mode determination/run length calculation processing is completed, the state control circuit 11 turns on the main ACMP (point b).

The sequence control circuit 13 turns on this AENBL again,
Start encoding mode determination/run length calculation processing (
point C). At this time, the output information (previous processing result) of the determination/arithmetic circuit 3 is stored in the temporary storage circuit 10. *ARD
Since Y is on, image data is input as before, and execution of encoding mode determination and run length calculation processing begins for the data.

After turning on *BENBL, the sequence control circuit 13 turns on *BENBL and starts table search processing (d
point). Under the control of the state control circuit 12, the table search circuit 4 retrieves the output information (mode information M) of the temporary storage circuit 10.
OD) is taken in and a table search is performed using this to create a corresponding code, and its words are aligned.

The word-aligned code data is output to the interface circuit 6, but here the rate BRDY is off and the system bus 5 is in a state where it cannot output code data, so the table search circuit 4 is in a waiting state. *BCMP is not turned on (points d-e in Figure 3). During such a waiting period due to the system bus being busy, the processing of the determination/arithmetic circuit 3 is being executed.

This encoding mode determination/run length calculation process ends at point e in FIG. 3, and is notified to the sequence control circuit 13 by turning on *ACPM.

The sequence control circuit 13 turns on IAENBL and restarts the encoding mode determination/run length calculation process (point f). At this time, the mode information that is the immediately previous processing result is stored in the temporary storage circuit IO.

Although the previous mode information stored in the temporary storage circuit IO is destroyed, there is no problem because the search process for this mode information has been completed. Furthermore, since the umbrella ARDY is on, the next image data is input, and encoding mode determination and run length calculation processing are executed.

Now, when IBRDY is turned on (point e), the output code data of the table search circuit 4 is output to the system bus 5,
The table search circuit 4 is released from the waiting state and the processing ends, and the state control circuit 12 turns on *BCMP (point g).

The sequence control circuit 13 turns on *BENBL (h
point). Under the control of the state control circuit 12, the table search circuit 4 takes in mode information from the temporary storage circuit 10 and executes table search processing.

Incidentally, although IAENBL is turned on at one point in FIG. 3, at this time *ARDY is turned off and input of image data is impossible, so the judgment/calculation circuit 3 enters a waiting state.

This wait state is canceled at point j when *ARDY turns on.

Here, between points d and 0 and points 1 and j in Figure 3, one of the processes is in a waiting state because one of the buses is busy.
The other process is executed. Furthermore, in other periods, both processes are executed in parallel. Therefore, compared to conventional devices, the encoding processing time is significantly shortened due to the time overlap between each processing, and the fluctuations in the encoding processing time due to bus busyness are also significantly reduced.

Note that it is also possible to separate the run length calculation circuit from the determination/calculation circuit 3 and have it directly controlled by the 7-case control circuit 13.

Effects of the Invention As is clear from the above description, the present invention controls the processing operations of the judgment/arithmetic circuit and the table search circuit independently, depending on the state of the corresponding bus and the processing state of its own circuit. and a temporary storage circuit for the output information of the determination/arithmetic circuit in front of the table search circuit to execute encoding mode determination/run length calculation processing and table search processing in parallel; In addition, by executing one process while the other process is in a waiting state due to bus busyness, it is possible to shorten encoding processing time and reduce fluctuations in processing time due to bus busyness. This has the effect that it is possible to

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an encoding device according to an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the processing operation of the same device.
FIG. 3 is a schematic configuration diagram of a conventional encoding device. 1... Image lotus, 2... Interface circuit, 3°
゛. Judgment/arithmetic circuit, 4...Table search circuit, 5...
System bus, 6...interface circuit, lO...
・Temporary memory circuit, 11.12...State control circuit, 13
...Sequence control circuit.

Claims (1)

[Claims] A determination/calculation circuit that detects a change point from image data, performs encoding mode determination and run length calculation, and outputs encoding mode information and run length information;
a temporary memory circuit that temporarily stores output information of the arithmetic circuit; a table search circuit that outputs code data by performing a table search based on the output information of the temporary memory circuit; an interface circuit that controls input of image data of the table search circuit; an interface circuit that controls output of output code data of the table search circuit to a system bus; and a state of the image bus indicated by the interface circuit of the image bus and the determination. - Control of the processing operation of the judgment/arithmetic circuit according to the operating state of the arithmetic circuit, and control of the table search circuit according to the state of the system bus indicated by the interface circuit of the system bus and the state of the table search circuit. 1. An encoding device comprising means for independently controlling processing operations.