JPH0736821A - Dma transfer controller - Google Patents

Abstract

PURPOSE:To provide a DMA transfer controller capable of quickly resetting the control of a bus when a DMA transfer request is stopped on the way of data packing/unpacking transfer, and at the time of restarting DMA transfer, surely and continuously transferring remaining data. CONSTITUTION:This DMA transfer controller has a DMA internal data V register 104 having capacity for holding data displaced by an input aligner in each channel, a valid bit register 124 for updating and storing the holding state of data held in each channel in each bus cycle, a means for releasing bus control in a succeeding bus cycle when a DMA transfer request is stopped, and a means for restarting the transfer of data held due to interruption at the time of generating a DMA transer restart request for an interrupted channel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device, and more particularly to a direct memory access transfer (hereinafter referred to as a DMA transfer).

[0002]

2. Description of the Related Art Since the processing transfer rate of an I / O device is not improved while the performance of a CPU is improved, a DMA transfer method that specializes in data transfer has a function of balancing the difference in the data transfer processing speed. There is a data pack / unpack method.

FIG. 3 shows the data pack method and FIG. 4 shows the data unpack method.

In the data pack method, the DMA transfer control device operates from a transfer source device (source side) having a narrow data bus width to a transfer destination device (destination side) having a wide data bus width.
It has the purpose of shortening the exclusive time of the bus control right of the DMA transfer control device when data is transferred to.

FIG. 3 shows an I having a data bus width of 8 bits.
FIG. 6 is a diagram showing an example of transferring data from an / O device to a memory device having a data bus width of 32 bits. When the DMA transfer control device receives a transfer request from the I / O side, it becomes a bus master and outputs a "read to I / O device (at the source side)" signal of the bus control signal in the first bus cycle. Data is output from the I / O device on the source side, and the 8-bit data is taken into a 32-bit register inside the DMA transfer control device. In the subsequent bus cycle, the same bus cycle is driven, and this is repeated four times until the data of 32 bits which is the data bus width on the destination side is fetched. Then, finally, the DMA control device, as a bus master, outputs a bus control signal "write to memory (at the destination side)" signal and outputs the data taken in by the DMA transfer device.
The procedure of writing 32-bit transfer data in the memory is performed. After that, the process is repeated until the preset count number becomes zero. In particular, in the case of this transfer, when the number of remaining transfer bytes is 3 bytes or less, the data in the DMA is forcibly written to the destination side after the read bus cycle for the remaining count occurs, and it is effective. Data is indicated in byte units by a byte enable signal or the like.

In the data unpacking method, the DMA transfer device operates from a transfer source device (source side) having a wide data bus width to a transfer destination device (destination side) having a narrow data bus width.
It has the purpose of shortening the exclusive time of the bus control right of the DMA transfer control device when data is transferred to.

FIG. 4 shows a memory device having a data bus width of 32 bits and an I / O having a data bus width of 16 bits.
It is a figure which shows the example which transfers data to O apparatus. When the DMA receives a transfer request from the I / O side, it becomes a bus master, and in the first bus cycle, outputs a bus control signal "read to memory device (which is the source side)" signal,
Data is output from the memory device on the source side, and the 32-bit data is fetched into the 32-bit register inside the DMA transfer control device. In the subsequent bus cycle, unlike the data pack method, the bus width on the destination side is narrower, so the bus control signal "write to I / O device (on the destination side)" is adjusted in 16-bit units according to the endian direction. Output signal, DM
A Transfer control device outputs the data captured and I / O
The procedure of writing 16-bit transfer data to the device is performed, and thereafter, the process is repeated until the preset count number becomes zero. Especially, in the case of this transfer, the number of remaining transfer bytes is 3
When the number of bytes is less than, after the last read bus cycle occurs,
The data inside the DMA is forcibly written twice to the destination side, and valid data is indicated in byte units by a byte enable signal.

Next, the pack / unpack control of the conventional DMA transfer control device will be described.

FIG. 2 is a diagram showing an embodiment of a conventional DMA transfer device.

In this conventional example, a count register 1 capable of 4-channel DMA transfer and accessible by the CPU
08 and the mode register 114 specify the transfer byte number and transfer mode of a single channel to be transferred by the selected channel information signal 118. That is, D
Before performing the MA transfer, the CPU sets the transfer mode in the mode register 114 and the transfer byte number in the count register 108 according to the channel to be used.

DMA transfer request input terminal 1 from the I / O device
When a DMA transfer request is input to the DMA transfer request processing unit 116 via 17, the DMA transfer request processing unit 116
Whether or not there is a mask for each channel, priority determination according to the transfer request status of other channels, and the like are performed, and the presence or absence of DMA transfer to the DMA transfer control unit 204, the count number check of the transfer request channel, and the priority check result selection. The channel information signal 118 thus generated is output.

The DMA transfer control unit 204 is a sequencer,
Synchronized to the next clock according to the current status, the status of the DMA internal register valid bit 21 indicating the validity of each byte of the DMA internal register 201 fetched, the transfer mode 112, and the input information indicated by the selected channel information signal 118. Then, the state transition is performed.

The internal register valid bit controller 122 is
The validity of data for each byte of the DMA internal register 201 (the data read inside the DMA but not yet written to outside is valid) is held on the valid bit register 202 by a 4-bit signal. , Updated every time a data pack / unpack bus cycle runs.

For example, in the data pack method of FIG. 3, the value of the valid bit register 202 is' 000 before the start of transfer.
Although it is 0 ', it is assumed that the LSB corresponds to the least significant byte, and the bus cycle of (1) causes'0001' and (2).
Is updated to "0011" by the bus cycle of 1, and the use status of the DMA internal register 201 during transfer is shown. In the case of the transfer mode of FIG. 3, the DMA transfer control unit 204
Shifts to the write cycle when the valid bit register 202 becomes '1111'. Also in the data unpacking method of FIG. 4, the write cycle is similarly repeated until the valid bit register 202 becomes “1111” and then becomes “0000”.

When there is a DMA transfer request, if it is the pack / unpack method, 32 input from the data input terminal 101 connected to the data bus of the system.
The bit data is stored in the mode register 114 before the DMA transfer.
Input aligner 1 according to the transfer mode preset in
At 02, the data is rearranged in byte units. As a result, for example, as shown in (1) to (4) of the data pack method of FIG. 3, it becomes possible to write data to the DMA internal 32-bit register 201 only by the LSB side 8-bit bus of the I / O device.

When data is rearranged in the input aligner 102, a DMA internal 32-bit register control signal is sent from the input data internal data bus 103 to the DMA internal register 201 which is a single 32-bit data register for packing / unpacking. Writing / reading is performed by 203.

The data output from the DMA internal register is connected to the output aligner 106 through the output data internal data bus 105. The output aligner 106 rearranges the output data according to the internal register valid bit 121 and the output aligner control signal 132 output in the transfer mode 112, and outputs the data from the data output terminal 107.

When the transfer end detection unit 111 detects that the number of transfer bytes set in the count register 108 has been decremented and has become 0, the fact is output to the DMA transfer control unit 204, and at the final transfer cycle, TC Activate signal 125.

In the DMA transfer control device described above, the DM
When there is no DMA transfer request during the DMA transfer using the A internal register, the data processing method of the DMA internal register is as follows.

At the time of data pack transfer, when the DMA transfer request is exhausted, the effective bit register 202 is sent to the DMA transfer control unit 204 from the selected channel information signal 118.
Until it becomes '0000', the transition is repeated one or more write cycles depending on the transfer mode 112. At this time,
Only when the data fetched into the DMA internal register 201 is not from the memory device but from the I / O device,
Since the data from the I / O device may be lost even if the read cycle is driven again, be sure to DM
At this time, the data in the A internal register 201 may be forcibly written to the outside, and the data from the memory device may be discarded.

FIG. 5 shows an I having an 8-bit data bus.
Read data from the I / O device and DM during pack transfer
A timing chart shows a case where the A transfer request is lost and the data in the DMA internal register 201 is written to the memory having a 32-bit data bus.

The DMA transfer is (1) to (4) and is a series of transfer cycles in which data is fetched from the source side into the DMA internal register 201 and then the DMA transfer is performed to the destination side.

Ti, Ta, Tb are bus states defined by the DMA transfer control device when the DMA becomes a bus master. In the DMA transfer device of this example, one bus cycle is completed in at least two clocks. The Ti state is a state in which the DMA transfer device is not the bus master, and the CPU or another bus master holds the bus use right.
The Ta state outputs the BCYST (-) signal,
In the Tb state, the DA (-) signal is activated in the state where the address of the bus cycle and other bus control signals are started to be output, and the data can be latched to the outside at the rising edge. Bus control signal BCYST
The (-) signal is negative logic and defines the first one clock of the bus cycle, the DA (-) signal is negative logic and defines the next state of the Ta state, and the MRQ (-) signal is negative logic and is the bus cycle. Is a memory access, and R
The W (-) signal has a negative logic and defines that the bus cycle is a write cycle. Further, the BE (3-0) (-) signal is output for each bus cycle in order to notify a valid byte of the data output to the data bus.
When the DMARQ signal sampled at the falling edge of the clock every Ta cycle becomes active and the DMA transfer request is recognized, the DMA transfer is started. DM
During the A transfer, the DMAAK signal is activated to notify the transfer source or transfer destination device.

Source side I having an 8-bit data bus
In the transfer mode in which DMA transfer is performed from the I / O device to the memory device on the destination side having a 32-bit data bus, T during the pack transfer for reading data from the I / O device
If the DMARQ signal, which is a DMA transfer request, is LOW at the falling edge of the a-state clock, the DMA transfer control unit 204 makes a state transition for the next bus cycle according to the selected channel information 118. As for the cycle, it drives a cycle for reading data from the I / O device.

In FIG. 5, the DMA internal register 201
After driving the DMA transfer cycle for performing the DMA transfer of the 3-byte data in the memory to the destination side (memory in FIG. 5) to surely transfer and transfer the untransferred data in the DMA internal register 201, Open.

Alternatively, as in Japanese Patent Laid-Open No. 3-157748 (reference), when the number of transfer bytes is unknown in the case of serial reception, the residual data in the DMA internal register can be detected and the end of transfer can be detected. There is also a method of performing DMA transfer of the residual data by software or hardware at the time. But this is only possible with data packs.

In the data unpack transfer, when the DMA transfer request is exhausted, the DM is transferred in the same manner as in the data pack transfer.
The transition to the write cycle is repeated until there is no more data in the A internal register 201. In FIG. 6, data is read from an I / O device having a 32-bit data bus, a DMA transfer request disappears during unpack transfer, and
A timing chart shows how data in the internal register 201 is written to a memory having a 16-bit data bus.

If the DMARQ signal is inactive at the falling edge of the Ta state clock in the bus cycle (1) for reading data from the I / O device, the data from the I / O device can be reliably transferred by DMA. The DMA transfer control unit 204 forcibly drives the DMA transfer cycle to the destination side (memory in FIG. 6) and then releases the bus.

In FIG. 6, an additional 2 bus cycles are forcibly driven from the bus scythe in which the DMARQ signal becomes inactive, but extremely 8 bits from the I / O device having a data bus width of 32 bits. Even when recognizing that the DMA transfer request has disappeared in the data read bus cycle from the I / O device during the data unpack transfer to the memory having the data bus width of 4 bytes, the DMA transfer to the memory requires 4 bus cycles. There is also a possibility to do.

[0030]

DISCLOSURE OF THE INVENTION Conventional DMA described above
The transfer control device uses a DMA internal data register which plays a role of balancing the difference in the data transfer rates of the source side and the destination side when the data transfer with different bus widths on the source side and the destination side is performed by the DMA transfer. Since the data pack method and the data unpack transfer are performed, there is a disadvantage that the DMA occupies the bus until all the data in the DMA internal data register is DMA transferred to the outside even if the DMA transfer request is lost.

When the number of transfer bytes in the DMA transfer is unknown, the data is held in the internal data register during the data pack and data unpack transfer and is externally DMA-transferred.
If the DMA transfer request is lost without being transferred,
In some cases, a fatal accident of losing transfer data occurred.

During DMA transfer of data pack transfer or data unpack transfer of a certain channel,
When there is a DMA transfer request for another high priority channel, again, until all the data in the DMA internal data register that has been used until that time is DMA transferred to the outside,
There is also a problem that the DMA transfer channel is not switched, the bus occupation rate of the DMA transfer device increases, and the throughput of the entire system decreases, and further, the reliability of the system increases due to the loss of transfer data. It became clear that there was a drawback that caused the decrease.

An object of the present invention is to improve the response of control right switching at the time of data pack transfer or data unpack transfer, and to surely transfer the data to be transferred, thereby improving the system performance. Is provided.

[0034]

A DMA transfer control device of the present invention has a plurality of channels, is capable of assembling intra-channel data, means for rearranging input data before assembling, channel information and Data having means for storing the channel mode, a register for holding data in the channel, a register for displaying information indicating whether the data held in the register has been transferred or not, and means for finally arranging output data In a DMA transfer control device that controls direct memory access transfer that can perform pack transfer and data unpack transfer, a register that latches the data rearranged before assembly as transfer data for each channel, and an intra-channel data transfer for each channel When the register indicating the transfer status and the stop of the transfer request of the DMA transfer are detected,
Means for directly interrupting the DMA transfer, means for detecting that untransferred data remains in the register for latching the transfer data, and restarting the DMA transfer for the untransferred data detected by the detection means. It has a control means for forcibly performing a DMA transfer for each channel according to an instruction.

Further, the present invention also includes means for detecting that the untransferred data remains, which is means for detecting from a register indicating a transfer state.

[0036]

It has a plurality of internal registers that can latch all the data in the channel.
Since the holding state of the latched data of each byte in the internal register is detected, even if the transfer request is stopped in the middle of the transfer cycle, the transfer cycle following the transfer result up to the said cycle is restarted and transferred. Can be completed.

[0037]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the DMA transfer control device of the present invention.

This DMA transfer control device uses the conventional DMA
The DMA internal register 104 of the control device has a plurality of areas having a capacity of 32 bits, and holds data for each channel in each area. Further, the valid bit register 202 has an area corresponding to the number of areas of the DMA internal register 104 and displays the effectiveness of each byte data. Further, it has a sweep register 115, and C
The untransferred data is detected for each channel by the DMA transfer restart instruction issued via the PU, and the OR gate 119 is detected.
The data transfer of the corresponding channel is started by the output information signal of.

Further, this DMA transfer control device is capable of 4-channel DMA transfer, and the count register 108 and the mode register 114 accessible by the CPU specify the transfer byte number and mode of a single channel by the selected channel signal 118. There is.

The DMA transfer mode register 114 has a transfer direction (I / O device to memory or memory to I).
/ O device) and a method of accepting a DMA transfer request and setting the bus width on the source side and the destination side. In particular, in the method of accepting a DMA transfer, a DMA transfer request pulse is latched by an RS flip-flop. There are a method (block transfer) and a method of performing DMA transfer (demand transfer) as long as there is a DMA transfer request.

Below, as long as there is a DMA transfer request, the DMA
The demand transfer for continuing the transfer will be described.

Before performing the DMA transfer, the mode register 114 and the number of transfer bytes for the channel to be used are set in the count register 108 by the CPU. When a DMA transfer request is input to the DMA transfer request input terminal 117 from the I / O device, the DMA transfer request processing unit 116 masks the DMA transfer request of each channel.
A single transfer channel is selected in accordance with the presence / absence of a signal in 7 and a fixed priority order in which MSB is channel 0 and LSB is channel 3, and the selected transfer channel information signal 118 is output.

The DMA internal data sweep-out register 115, like the other DMA internal registers, allows only writing from the CPU on a channel-by-channel basis, and the writing operation from the CPU to this register causes the 2-input logical sum 119. Output information signal 129 can drive a DMA transfer for transferring the contents of the DNA internal data register to the outside.

The DMA transfer control unit 110 is a sequencer, and the status of the DMA internal register valid bit 121 indicating the validity of each byte of the DMA internal register 104 input for the current status, the transfer mode 112, and the selected channel information 129. The state transition is performed in synchronization with the next clock according to the input information.

The DMA internal register 104 has a 32-bit register for each channel, and only the register corresponding to the DMA transfer channel is used by the selected channel signal 129 during the DMA transfer. Therefore, as in the conventional example of FIG. 2, there is a possibility that a DMA transfer during operation is interrupted midway and a transfer of another channel may occur, so that the entire contents of the DMA internal register 201 are lost during the data pack. It is not necessary to make a DMA transfer.

Further, since the DMA controller can release the bus while holding the data in the middle of packing in the DMA internal register, the bus occupation rate of the DMA transfer device can be further reduced.

The internal register valid bit controller 122
The validity of data is indicated by a 4-bit signal for each byte of the DMA internal register 104, and is updated every time a data pack / unpack bus cycle runs. For example, in the data pack method of FIG. 3, the value of the valid bit register 124 is "0000" before the transfer is started, but it is assumed that the LSB corresponds to the least significant byte and "0" by the bus cycle of (1).
DMA being updated to “0011” by the bus cycle of 001 ”and (2) and during the transfer of the selected channel.
The usage status of the internal register 104 is shown.

The effective bit register 124 has a 4-bit register for each channel, and uses only the register corresponding to the DMA transfer channel by the selected channel signal 129 during the DMA transfer.

Further, the effective bit register 124 is DM
It can be said that the current state of the DMA transfer is shown during the A transfer. That is, if the destination side has a data bus with a bus width of 32 bits, the DMA control unit 110 drives the read cycle for obtaining data on the source side until the value of the valid bit register 124 becomes “1111”. DMA with a 16-bit data bus width
As the lower byte of the internal register 104 is used in order, the value of the valid bit register 124 is "001."
It is sufficient to drive the read cycle until it becomes 1 ".

Therefore, in addition to the above DMA data register 104, the effective bit register 12 is provided for each channel.
By having 4, it becomes possible to restart the data pack / unpack halfway when the DMA transfer request is input again and the DMA transfer is restarted even if the transfer is interrupted midway.

The status register 126, which is read only from the CPU, is provided for each channel to ensure data transfer when the above DMA transfer is in the middle of data pack / unpack transfer using the DMA internal data register 104. The DMA internal data register 104 has a bit indicating that transfer data still remains. This can be realized by a logical sum of 4 bits for each channel for the value in the valid bit register 124. If the value is 1, the data to be transferred remains, and if the value is 0, the data to be transferred. You can see that there is no.

Therefore, the DMA for the channel which is 1 among the bits indicated by the status register 126
If you access the internal data sweep register 115,
Transfer data in the middle of packing / unpacking can be DMA-transferred to the outside. This is a pack / unpack DM
This means that even if the DMA transfer cycle is interrupted during the transfer of A and the transfer data remains in the DMA internal register of the transfer channel as it is, it can be transferred to the outside by software.

FIG. 7 is a timing chart of pack transfer of data by the DMA transfer control device of the present invention, and FIG. 8 is a timing chart of its unpack transfer.

This pack transfer is a pack transfer from an I / O device having a data bus of 8 bits on the source side to a memory device having a data bus of 32 bits on the destination side, and unpack transfer is data transfer of 32 bits on the source side. This is an unpack transfer from an I / O device having a bus to a memory device having a 16-bit data bus on the destination side.

The sequence from the input of the DMA transfer request to the start of the DMA transfer is that the values of the DMA internal data register 104 and the valid bit register 124 are always selected as the DMA transfer channel during the transfer by the selected channel signal 129. , The same as the conventional sequence. In other words, when the DMA transfer request is recognized, when the transfer request is approved according to the priority order or the mask status, the HLRQ (-) signal requesting the CPU or the bus arbiter to release the bus is activated. When the release of the bus is approved by the previous bus master, the DMA transfer bus cycle is started after waiting for the input of the HLDAK (-) signal. During the DMA bus cycle, the DMAAK signal is activated in order to notify the source side that the DMA transfer request has been approved.

During a DMA transfer bus cycle, a read signal is output to the source side in the Ta state, and data is sampled at the last Tb state and the next rising edge of the clock even if the bus cycle is extended due to wait, and the data is input. Input to the aligner 102. The input aligner 102 is compatible with data pack transfer, and has 32 byte units as shown in FIG.
It has a relocation type of bit data. The byte transfer changing type control of the input aligner 102 is performed by the DMA transfer control unit 110.

Depending on the transfer mode, the arrangement of data in bytes is changed, and the data is transferred via the input data bus 103.
After latching in the internal data register 104 corresponding to each channel, when the DMA transfer control unit 110 makes a transition to a write cycle according to the value of the valid bit register 124, data is loaded on the output internal data bus 105.

Also in the output aligner 106, the arrangement of bytes is changed according to the transfer mode, and the data is output to the outside. The output aligner 106 corresponds to the data unpack transfer and has a type of arrangement change of 32-bit data in byte units as shown in FIG.

What is remarkably different from the conventional example of this embodiment is that D
It is time for the MA transfer controller to stop the DMA transfer and release the bus.

In the timing chart shown in FIG. 7, each D is read while data is being read from the pack transfer I / O device.
The sampling is performed at the falling edge of the Ta cycle of the MA cycle, and if the DMARQ signal is inactive, the DMA transfer control device releases the bus in the DMA bus cycle. Data pack DMA
Even during the transfer, the internal data register 104 and the valid bit register 124 can hold the progress, and the transfer can be interrupted. This means that when the DMARQ signal is sampled, if there is no DMA request, the DMA transfer can be immediately interrupted, the bus can be released, and when the DMA transfer request for the channel is generated again, the transfer can be continued. means. If another high priority DMA transfer request is issued during a DMA transfer of a certain channel, the bus is released while holding the progress, and the DMA transfer service of the higher priority channel is started earlier than before. It means that you can do it.

In FIG. 8, sampling is performed at the falling edge of the Ta cycle clock of each DMA cycle during the reading of data from the unpacked I / O device (or in the data writing cycle after reading the data). If the DMARQ signal is inactive, the DMA transfer controller releases the bus in the DMA bus cycle.

Even during the DMA transfer of the data unpack, the internal data register 104 and the valid bit register 124 can hold the progress, and the transfer can be interrupted. This means that when the DMARQ signal is sampled, if there is no DMA transfer request, the DMA transfer can be immediately interrupted, the bus can be released, and when the DMA transfer request for the channel is generated again, the transfer can be continued. means. Further, even if another high priority DMA transfer request is made during the DMA transfer of a certain channel, the bus is released while keeping the progress of the request, so that the DMA transfer service of the higher priority channel can be performed faster than before. Means you can start.

In the pack / unpack transfer of data, the TC signal is output from the transfer end detection unit 111 at the end of the transfer, so that the transfer end of the channel that has been transferred up to now can be externalized.

[0065]

As described above, according to the present invention, a DMA having a capacity capable of holding intra-channel data for each channel.
It has an internal data register and a valid bit register that holds the transfer status of the data for each channel held in these registers, and D during the data pack / unpack transfer
When the MA transfer request disappears or a high-priority DMA transfer request occurs, the transfer status of the data that has been transferred is held and the bus is immediately released. Since the DMA transfer can be restarted by this, the switching of the bus control right becomes extremely fast, the interrupt can be promptly dealt with, and the interrupted DM can be performed.
There is an effect that the A transfer is surely restarted and there is no fear of data disappearance.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a DMA transfer control device of the present invention.

FIG. 2 is a block diagram of an embodiment of a conventional DMA transfer control device.

FIG. 3 is a conceptual diagram of a data pack method, including (a) to (d).
Shows a state in which 1 byte is read in, and (e) shows a state in which 4 bytes are packed and written in the memory.

FIG. 4 is a conceptual diagram of a data unpacking method, in which (a) reads 32-bit data from a memory (b),
(C) is a diagram showing a state in which 2 bytes are written in the 16-bit wide I / O.

5 is a timing chart of data pack transfer by the DMA transfer control device shown in FIG.

6 is a timing chart of data unpack transfer by the DMA transfer control device shown in FIG.

7 is a timing chart of data pack transfer by the DMA transfer control device shown in FIG.

8 is a timing chart of data unpack transfer by the DMA transfer control device shown in FIG.

FIG. 9 is a diagram showing a type of byte-aligned data alignment of the input aligner 101 shown in FIGS. 1 and 2, where (a) is a fourth byte arranged in 4 bytes, and (b) is a third and a fourth. FIG. 6 is a diagram showing a type in which bytes are repeatedly arranged in series, and 4 bytes are arranged in an input order.

10 is a type of byte-aligned data alignment of the output aligner 106 shown in FIGS. 1 and 2, where (a) is arranged in byte order in input order, and (b) is the first to third bytes in input order. And, the third byte is arranged at the fourth position, (c) repeats the first and second data of the input 4-byte data and arranges them in series, and (d) shows the first to third data. It is a figure which shows the type which arrange | positions the bytes until it is input order, and arrange | positions the 1st byte 4th.

[Explanation of symbols]

 101 data input terminal 102 input aligner 103 internal data bus for input data 104 DMA internal data register 105 internal data bus for output data 106 output aligner 107 data output terminal 108 count register 109 input aligner control signal 110 DMA transfer control unit 111 transfer end detection Part 112 Transfer mode signal 113 Transfer end detection signal 114 Mode register 115 DMA internal data sweep register 116 DMA transfer request processing part 117 DMARQ signal input terminal 118 Selected channel information signal 119 2 input OR gate 120 DMA internal data register control signal 121 DMA internal Register valid bit 122 DMA internal register valid bit 123 Transfer selection internal valid bit 124 Valid bit register 125 TC signal 126 Status Register 127 Mask Register 128 DMAAK Signal Output Terminal 129 Select Channel Signal 130 Bus Transfer Control Signal Terminal 131 Bus Control Signal 132 Output Aligner Control Signal 201 DMA Internal Register 202 Effective Bit Register 203 DMA Internal Data Register Control Signal 204 DMA Transfer Control Section

Claims (2)

[Claims] 1. A plurality of channels, capable of assembling intra-channel data, means for rearranging input data before assembling, means for storing channel information and channel mode, and holding intra-channel data Register to
Controls a direct memory access transfer capable of data pack transfer and data unpack transfer having a register for displaying information indicating whether the data held in the register has been transferred or not and a means for finally arranging output data. D
In the MA transfer control device, a register for latching the data rearranged before assembly as transfer data for each channel, and a stop of a DMA transfer transfer request are detected, the DM transfer is immediately performed.
A means for interrupting transfer, a register for indicating the transfer state of in-channel data for each channel, a means for detecting that untransferred data remains in the register for latching the transfer data, and a detection means for detecting the untransferred data The untransferred data that has been transferred
A DMA transfer control device comprising control means for forcibly performing DMA transfer for each channel in response to a transfer restart instruction. 2. The DMA transfer control device according to claim 1, wherein the means for detecting that the untransferred data remains is means for detecting from a register indicating a transfer state.