JPH05197609A - Store buffer managing system - Google Patents

Abstract

PURPOSE:To reduce the number of performing accesses with a main storage device and to effectively utilize a store buffer with limited capacity by merging the store data of a preceding store instruction and the store data of a following store instruction and registering them on the store buffer as one store instruction later. CONSTITUTION:When the store request information of the preceding store instruction is registered on a waiting register R4 (4) and the store request information of the following store instruction is registered on a waiting register R3 (3) at the same time, at the next time point T, the store data of the preceding store instruction are transmitted from an arithmetic part and written at the word position of a store buffer 6 shown by a WA pointer 9. At such a time, the preceding store request in the R4 (4) is also written in the same word position as the store data buffer 6 in a store request buffer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a store buffer management system which is used in a computer system and performs high speed processing of store instructions.

[0002]

2. Description of the Related Art In conventional store instruction processing in an information processing apparatus, the processing is performed as separate store instructions without judging whether two consecutive store instructions are store instructions for the same address in the main memory. ing.

[0003]

Therefore, in the information processing apparatus of the conventional example, since the same address of the main storage device is separately processed, it takes twice as much time to access the main storage device. There is.

The present invention solves such a problem, and provides a store buffer management system capable of reducing the number of accesses to the main storage device and effectively utilizing a store buffer having a limited capacity. With the goal.

[0005]

To achieve this object, the store buffer management system of the present invention comprises a store buffer, an arithmetic unit for supporting the execution of instructions requiring store instruction processing, and a main memory. In the store buffer management method according to the pipeline processing information processing device provided,
When the preceding store instruction and the subsequent store instruction are store instructions for the same main memory address, the store request information and store data information are registered in the store buffer as one store instruction. When the store request information about the store request is sent from the instruction control unit to the store control unit, the store data information paired with the store request information is sent from the operation control unit to the store control unit after several T cycles, and the store request and the store Waiting means for waiting the store request information by the multi-stage register by utilizing the shift of the transmission timing of the data to the store control unit, and the store request information of the preceding store instruction is registered in the final stage register of the multi-stage register, At the same time, the register next to the register one stage before the final stage A) When the instruction is registered, the store request information of the two-stage register is compared, and when they match, it is determined that the preceding store instruction and the subsequent store instruction are the store instructions for the same main memory address. However, when the store instruction is for the same main memory address, the store request information and the store data information of the preceding store instruction are simultaneously stored at the timing when the store data information of the preceding store instruction is sent from the arithmetic control section to the store control section. When writing is performed at the word position pointed by the write instruction pointer, and the store data information of the subsequent store instruction is sent from the arithmetic control unit to the store control unit, the mask information indicating the validity of the byte-unit store data is valid. The part of the store data is stored in the store It is characterized in that to register overwriting the same word position fa.

Further, the queuing means and the judging means store the store request information in a two-stage register and the store request information of the preceding store instruction is registered in the second stage register of the two-stage register. When the subsequent store instruction is registered in the one-stage register, the store request information of the two-stage register is compared, and if they match, it is determined that the preceding store instruction and the subsequent store instruction are stores for the same main memory address. Means, an instruction means for issuing a dedicated write instruction for registering the store request in the store request buffer, and an instruction means for instructing an exclusive write instruction for registering the store data in the store data buffer. In addition to the above-mentioned configuration, the data is sent from the arithmetic control unit to the store control unit. If the store data of the preceding store instruction is registered in the register and the store data of the subsequent store instruction is sent from the arithmetic control unit to the store control unit, both store data are stored in the register. The mask information indicating the validity of the byte-by-byte store data of the subsequent store instruction is valid. The store data is merged with the store data output signal of the preceding store instruction held in the register and indicated by the store data write instruction pointer. It is characterized in that it is registered as one command at the word position to be stored.

In addition to the above configuration, holding means for holding the store request information by a two-stage register, and the store request information of the preceding store instruction is registered in the second stage register of the two-stage register, and the first stage When the subsequent store instruction is registered in the register of, the store request information of the two-stage register is compared, and when they match, the preceding store instruction and the subsequent store instruction are determined to be the stores for the same main memory address. , Instruction means for issuing a dedicated write instruction for registering the store request in the store request buffer, instruction means for issuing a dedicated write instruction for registering the store data in the store data buffer, and store data sent from the arithmetic control section to the store control section It is equipped with a reception means to receive When the store data of the subsequent store instruction is sent from the arithmetic control unit to the store control unit while the store data of is stored, both store data have mask information indicating the validity of the byte-unit store data of the subsequent store instruction. It is characterized in that the valid store data is merged with the store data of the preceding store instruction held in the register to register it as one instruction at the word position indicated by the store data write instruction pointer.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the store buffer management system of the present invention will be described below with reference to the drawings.

First, the first embodiment will be described. The first embodiment corresponds to claim 1.

FIG. 1 shows the configuration of the first embodiment.

In FIG. 1, the store request information sent from the instruction control unit is written into the store buffer at the same timing as the pair of store data sent from the arithmetic unit after several T cycles, R1, R2, R3, R4 ( 1,
Waiting is performed by the multi-stage registers shown in 2, 3, 4). The storage data information is transmitted to the store request buffer 5 and the store data buffer 6 4T cycles later than the store request information, and the four wait registers R1 to R4 (1 to 4) are provided. It is set.

In FIG. 1, the store request information of the preceding store instruction is registered in R4 (4), and at the same time, R3 (3) is registered.
When the store request information of the subsequent store instruction is registered in (3), the store data of the preceding store instruction is sent from the arithmetic unit at the next T and written in the word position of the store data buffer 6 indicated by the WA pointer 9. At this time, the preceding store request of R4 (4) is also written to the same word position as the store data buffer 6 of the store request buffer 5.

Further, when R3 = R4 is detected at this time, the WA pointer 9 which counts + (plus) 1 is usually controlled so as not to count up after instructing writing to the store request buffer 5 and the store data buffer 6. The store data of the subsequent store instruction is controlled so as to instruct the write to the same address as the preceding store instruction. The detection of R3 = R4 detects that the preceding store instruction and the subsequent store instruction are store instructions for the same address in the main memory. Further, at the next T, when the store data of the subsequent store instruction is sent from the operation unit, the store data write control unit 8 shown in FIG. 1 shows the validity of the byte unit data sent from the operation unit together with the store data. Control is performed so that only valid bytes of store data are selected according to the store mask information and written into the store data buffer 6.

With this control, the store data buffer 6 has already been stored.
Only valid store data of the store data of the succeeding store instruction can be overwritten on the store data of the preceding store instruction written in. Further, the store data of the preceding store instruction and the store data of the subsequent store instruction are merged when registering the store buffer, and can be registered as one store instruction.

Next, a second embodiment will be described. This second
This embodiment corresponds to claim 2.

FIG. 2 shows a second embodiment.

In the second embodiment, the write instruction pointer to the store request buffer 5 and the write instruction pointer to the store data buffer are the same pointers as the WA pointer 9 in the first embodiment, whereas the second embodiment performs the write operation. Pointer pointer SWA11, write pointer pointer D
Writing is possible separately from WA12.

By having a pointer exclusively for registering the store request buffer and for registering the store data buffer, the multi-stage register holding means of R1 to R4 (1 to 4) shown in FIG. There can only be two stages for detecting a match.

In FIG. 2, when the store request of the R2 (2) preceding store instruction is registered in the store request buffer 5 and at the same time the store request of the subsequent store instruction is registered in R1 (1), R1 = at the next T. The detection of R4 is performed by the comparator 7. When R1 = R2, the preceding store instruction and the subsequent store instruction are judged to be the store instructions for the same address in the main memory device, and the write instruction pointer SWA11 and the write instruction pointer DW of the store request buffer 5 and the store data buffer 6 are stored.
The +1 count of A12 is controlled to wait until the store data of the subsequent store instruction is registered in the store data buffer 6.

When the store data of the preceding store instruction is registered in the store data buffer 6 and then the store data of the succeeding store instruction is transmitted from the arithmetic unit, it is effective by the store mask information transmitted from the arithmetic unit at the same time. The store data write control unit 8 controls so that only the store data of a certain byte is written to the store data buffer. Therefore, at the same word position in the store data buffer, the store data of the preceding store instruction and the store data of the subsequent store instruction are merged and registered as the store data of one store instruction.

Further, a third embodiment will be described. This third embodiment corresponds to claim 3.

FIG. 3 shows a third embodiment.

In the third embodiment, since the store data sent from the arithmetic unit in the first embodiment is directly registered in the store data buffer 6, the store data of the preceding store instruction and the store data of the succeeding store instruction are stored. The merge is executed in the store data buffer 6, whereas the store data sent from the arithmetic unit is the one-stage register WDR.
In the next T, the store WDR13 output store data is merged with the store data sent from the arithmetic unit at this timing by the selector WDX14, and the store data of one instruction is generated and then registered in the store data buffer.

In FIG. 3, when the store request of the preceding store instruction is registered in R4 (4) and the store request of the succeeding store instruction is registered in R3 (3) at the same time, the preceding store instruction is made by the comparator 7 at the next T. And the subsequent store request is matched. If a match is detected, it is determined that the preceding store instruction and the subsequent store instruction are store instructions for the same address in the main memory, and W
The A pointer 9 is controlled so as to suppress the +1 count.

At this timing, the register WDR1
3 stores the store data of the preceding store instruction. When the store data of the subsequent store instruction is sent from the arithmetic unit, the register WD is selected by the selector WDX14.
From the store data of the preceding store instruction and the store data of the succeeding store instruction which are output signals from R13, the valid byte data of the store mask information sent from the operation unit at the same time as the store data of the succeeding store instruction is the data of the succeeding store instruction. The selection control unit controls so that the store data is selected and invalid byte data is selected as the store data of the preceding store instruction. Therefore, the output signal of the selector WDX 14 is written in the word position indicated by the WA pointer 9 of the store data buffer 6 as the store data of one store instruction in which the store data of the preceding store instruction and the store data of the subsequent store instruction are merged.

Next, a fourth embodiment will be described. This 4th
This embodiment corresponds to claim 4.

FIG. 4 shows this fourth embodiment.

The fourth embodiment is the same as the second embodiment and the third embodiment.
The examples are combined.

The registration of the store request in the store request buffer 5 is performed by the dedicated write instruction pointer SW.
A12 and register DWA13. R1 to R4 (1 to 4) shown in FIG. 1 because they have separate pointers
The multi-stage wait register of 2 need only have two stages of registers for coincident transmission of the preceding store instruction and the subsequent store instruction. In the embodiment of FIG. 1, the store data of the preceding store instruction and the store data of the subsequent store instruction sent from the arithmetic unit were merged in the store data buffer 6, but by using the register WDR13 and the selector WDX14, The data buffer 6 can be controlled at the registration timing.

In FIG. 4, when the store request of the preceding store instruction is registered in R2 (2) and at the same time the store request of the subsequent store instruction is registered in R1 (1), the comparator 7 causes R1 (1) and R2 ( The match of 2) is detected. If a match is detected, it is determined that the preceding store instruction and the subsequent store instruction are store instructions for the same address in the main memory, and the store request buffer 5
Is controlled so that the +1 count of the write instruction pointer SWA11 and the store data buffer write instruction pointer DWA12 is suppressed.

When the store data of the preceding store instruction is sent from the arithmetic unit, it is held in the register WDR13. When the store data of the succeeding store instruction is sent from the arithmetic unit, it is valid by the store data of the preceding store instruction from the register WDR13 and the store mask information sent from the arithmetic unit at the same time as the store data of the subsequent store instruction in the selector WDX14. The selection control unit 15 selects the store data of the subsequent store instruction as the store data of a certain byte unit, and selects the store data of the preceding store instruction for the store data of the byte unit in which the store mask information of the subsequent store instruction is invalid. Control.

Therefore, the store data output from the selector WDX 14 is registered as the store data of one instruction obtained by merging the store data of the preceding store instruction and the subsequent store instruction with respect to the word position indicated by the DWA pointer 12 of the store data buffer. .

As is apparent from the above description, in the store buffer management method of the present invention, when the pointer has consecutive store instructions for the same main memory address, the store instruction of the preceding store instruction is registered when the store buffer is registered. After merging the store data and the store data of the subsequent store instruction, it is registered in the store buffer as one store instruction, so that it is possible to reduce the number of accesses to the main memory and to save the limited capacity. This has the effect of effectively utilizing the store buffer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in a first embodiment of a store buffer management system of the present invention.

FIG. 2 is a block diagram showing a configuration in a second exemplary embodiment.

FIG. 3 is a block diagram showing a configuration in a third exemplary embodiment.

FIG. 4 is a block diagram showing a configuration in a fourth exemplary embodiment.

[Explanation of symbols]

 5 Store Request Buffer 6 Store Data Buffer 7 Comparator 8 Store Data Write Control Section 9 WA Pointer 11, 12 Write Instruction Pointer DWA 13 Register WDR 14 WDX Selector 15 Selection Control Section

Claims (4)

[Claims] 1. A store buffer management method according to a pipeline processing information processing apparatus comprising a store buffer, an arithmetic unit that supports execution of instructions requiring store instruction processing, and a main memory, and a preceding store instruction and a succeeding store instruction. If the store instructions for the same main memory address are the store instruction information, the store request information and the store data information in the store buffer are registered as one store instruction. When transmitted from the control unit to the store control unit, the store data information paired with the store request information is transmitted from the arithmetic control unit to the store control unit after several T cycles, and the store control unit for the store request and the store data. Store request information Waiting means for waiting by a multi-stage register, and store request information of the preceding store instruction is registered in the final stage register of the multi-stage register, and at the same time, a subsequent store instruction is registered in the register one stage before the final stage. And comparing the store request information of the two-stage registers and judging that the preceding store instruction and the succeeding store instruction are store instructions for the same main memory address when they match, for the same main memory address When the store instruction is a store instruction, the store request information and the store data information of the preceding store instruction are simultaneously indicated by the store buffer write instruction pointer at the timing when the store data information of the preceding store instruction is sent from the arithmetic control section to the store control section. Write to word position, and then follow When the store data information of the tor instruction is sent from the arithmetic control unit to the store control unit, the store data of the portion where the mask information indicating the validity of the byte-unit store data is valid is stored in which the preceding store instruction is registered. Store buffer management method characterized by overwriting and registering at the same word position in the buffer. 2. The queuing means and the judging means are holding means for holding the store request information by a two-stage register, and store request information of the preceding store instruction is registered in a second-stage register of the two-stage register, When the subsequent store instruction is registered in the register of the first stage, the store request information of the registers of the two stages are compared, and when they match, it is determined that the preceding store instruction and the subsequent store instruction are stores for the same main memory address. Determination means, an instruction means for issuing a dedicated write instruction for registering the store request in the store request buffer, and an instruction means for issuing a dedicated write instruction for registering the store data in the store data buffer. The store buffer management method according to claim 1. 3. In addition to the configuration according to claim 1, there is provided a receiving means for receiving the store data sent from the arithmetic control section to the store control section by a one-stage register, and the store data of the preceding store instruction is registered in the register. When the store data of the subsequent store instruction is sent from the arithmetic control unit to the store control unit in the above state, the mask data indicating the validity of the byte-unit store data of the subsequent store instruction A store buffer management system characterized by merging with a store data output signal of a preceding store instruction held in the register and registering as one instruction at a word position indicated by a store data write instruction pointer. 4. In addition to the configuration according to claim 1, holding means for holding store request information by a two-stage register, and store request information of a preceding store instruction in a second-stage register of the two-stage register. When the subsequent store instruction is registered in the register of the first stage, the store request information of the registers of the two stages is compared, and when they match, the preceding store instruction and the subsequent store instruction are stores for the same main memory address. Determining means, an instruction means for issuing a dedicated write instruction for registering a store request in the store request buffer, an instruction means for issuing a dedicated write instruction for registering store data in the store data buffer, and an operation control section to a store control section. A register for receiving the store data sent to the general register, When the store data of the subsequent store instruction is sent from the arithmetic control unit to the store control unit while the store data of the preceding store instruction is registered in, the validity of the byte-unit store data of the subsequent store instruction A store characterized by registering as one instruction at the word position indicated by the store data write instruction pointer by merging the store data of which the mask information shown is valid with the store data of the preceding store instruction held in the register. Buffer management method.