JPH11353242A - Memory control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up access by minimizing the delay of data return due to an ECC(error check and correction) process. SOLUTION: Data read out of a memory 12 are transferred to a queue 14 before an error is detected. Namely, enqueuing and error detection are performed simultaneously in parallel. When no error is found in next timing, the data are taken out of the queue 14 in a next cycle and sent back to an access request source. Therefore, when there is no error, the data are sent back to the access request source in the next cycle of the data detection. If an error of the data is detected, the data which are already enquenced are made ineffective and error-corrected data are enqueued again. At the exit of the queue 14, a sending-back output driver 13 with an output enabling function is provided and wrong data taken out of the queue are made ineffective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory control system for speeding up memory access including ECC (Error Check and Collect) processing.

[0002]

2. Description of the Related Art When data is read by accessing a memory, ECC processing is performed for error detection and correction of the read data. For example, in the ECC process, one-bit error correction and two-bit error detection are performed using the redundant bits of the read data. On the output side of the memory, a number of logic circuits are arranged for this processing. When data is read from the memory, a one-bit error is detected and corrected in the next one cycle of the system clock, and a two-bit error is detected in the next one cycle.
If it is determined that there is no error in the read data, the data is transferred to a queue for storing return data. That is, the read data is enqueued if there is no error, invalidated if there is an error, and reread from the memory.

[0003]

However, the above-mentioned prior art has the following problems to be solved. When performing the above-described ECC processing, the return of the read data is waited until the processing such as error detection and correction is completed. Therefore, even if there is no error in the read data, there is a problem that returning the read data to the device that has requested the memory access is delayed. In order to solve this problem, a technique for controlling the timing of returning read data in accordance with the presence or absence of an error to increase the speed has been introduced (Japanese Patent Application Laid-Open No. Hei 7-146825). However, this type of system is as simple as possible in its circuit configuration,
It is also desirable that the operation be simple.

[0004]

The present invention employs the following structure to solve the above problems. <Structure 1> An ECC circuit for detecting and correcting an error in data read from a memory by access, a queue for storing data before error detection read from the memory, and data extracted from an exit of the queue. When the ECC circuit detects an error in the data, the corresponding output data stored in the queue is invalidated. A memory control system, comprising: a control circuit that controls a return output driver to invalidate data extracted from an exit of a queue.

<Configuration 2> In the system described in Configuration 1, when the corresponding data stored in the queue is invalidated, the ECC circuit newly stores the data corrected by the ECC circuit in the queue. A memory control system characterized by the above-mentioned.

<Configuration 3> In the system described in Configuration 1, the control circuit stores the data in the queue so that the data is stored in the queue until the error detection of the data by the ECC circuit is completed. A memory control system characterized by setting a wait cycle to adjust the time.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, data read from a memory is transferred to a queue before error detection. That is, enqueue and error detection are performed simultaneously in parallel.
Enqueue means transferring data to a queue. If the queue is empty, the enqueued data is stored at the head of the queue. If the queue is not empty,
Enqueued data is ordered so that it is retrieved next to data already stored.

If there is no error at the next timing, data is taken out of the queue in the next cycle and returned to the access request source. Therefore, if there is no error in the data, the data is returned to the access request source in the next cycle of the error detection. If an error is detected in the data, the already enqueued data is invalidated, and the error-corrected data is re-enqueued. If the corresponding data is at the head of the queue, the data is returned to the access request source in time for invalidation processing. Therefore, a return output driver with output enable is provided at the exit of the queue.
This invalidates the data retrieved from the queue.

Further, the data processed immediately before may remain in the queue. If the data just processed remains, the timing for extracting the data from the queue is 1
Cycle delay. In this case, the data in the queue can be freely invalidated. Therefore, in the following description, when data read from a memory is enqueued, description will be made in consideration of a case where the data comes to the head of the queue and a case where data processed immediately before remains in the queue. . Hereinafter, embodiments of the present invention will be described using specific examples.

FIG. 1 is a block diagram showing a specific example of a memory control system according to the present invention. The system shown is configured such that a memory access request device 11 accesses a memory 12 via a memory control circuit 10. The memory control circuit 10 includes a return output driver 13 with an output enable, a data return queue 14, a control circuit 15, and an ECC circuit 16.

The memory access request device 11 includes, for example, a CPU (Central Processing Unit), a DMAC (Direct Memory Access Controller), and the like. This device 1
1 accesses the memory 12 by supplying a control signal such as an access address and a read enable signal. The memory 12 includes a storage device such as a semiconductor memory, an optical disk, and a magnetic disk.

The ECC circuit 16 is not different from the known one. Detects data errors by referring to the redundant bits,
If there is a one-bit error, the process of correcting it is executed in one cycle of the system clock. In the next one cycle, a 2-bit error is detected. Therefore, this EC
The C circuit 16 completes processing of one data in two cycles of the system clock. If no error is detected in the first cycle, the process of detecting a 2-bit error is omitted.

The queue 14 temporarily stores data read from the memory 12. The queue is composed of, for example, a first-in first-out ring buffer or the like. Note that a flag indicating the validity is added to each data stored in the queue. Therefore, the data for which an error has been detected by the ECC circuit 16 is invalidated by switching this flag by the control circuit 15. Invalidated data is not removed from the queue.

When the ECC circuit 16 detects an error, the control circuit 15 invalidates the corresponding data in the queue 14 in the next cycle. However, if the corresponding data is at the head of the queue, the data is taken out of the queue before the invalidation processing. When there is no error in the data, the return output driver 13 with the output enable extracts the data at the head of the queue and returns it to the access request source. On the other hand, if there is a possibility that data will be extracted without performing the invalidation processing, the output is disabled and the extracted data is invalidated.

As described above, the control circuit 15 is a circuit for invalidating the data in the queue 14 by the error detection output of the ECC circuit 16 and outputting a signal for switching the operation of the return output driver 13. Can be realized by a simple logic gate.

<Operation> The operation of the memory control system shown in FIG. 1 will be described below in order of each operation pattern. (1) First Pattern (No Error, Queue Is Empty) FIG. 2 shows an operation timing chart of the first pattern. The horizontal axis of this figure represents time, (a) is a system clock, (b) is data read from the memory 12,
(C) shows the operation of the queue, (d) shows the operation of the ECC circuit 16, (e) shows the return data, (f) shows the strobe for transferring the return data, and (g) shows the operation of the output driver 13 for return. The first cycle is S1, and the second cycle is S1.
The second and third cycles are indicated in the figure as S3.

[First Cycle] The data read from the memory 12 is stored (enqueued) in the queue 14. At this time, the queue 14 is empty, and data is stored at the head of the queue 14. The ECC circuit detects that there is no error in the data read from the memory 12. [Second cycle] The output driver for return 13
The corresponding data stored at the head of No. 4 is extracted and returned to the access request source. This is the pattern that returns data the fastest.

(2) Second pattern (no error, queue is not empty) FIG. 3 shows an operation timing chart of the second pattern. The description format of the figure is exactly the same as that of FIG. [First cycle] Data read from the memory 12 is stored (enqueued) in the queue 14. Since the data read and processed last time is stored at the head of the queue 14, the data read this time is stored next. The ECC circuit detects that there is no error in the current data read from the memory 12.

[Second cycle] Return output driver 13
Retrieves the previously read data stored at the head of the queue 14 and returns it to the access request source. [Third Cycle] Subsequently, the return output driver 13 takes out the data from which no error has occurred this time from the queue 14 and returns it to the access request source.

(3) Third pattern (1 bit error present, queue is empty) FIG. 4 shows an operation timing chart of the third pattern. The description format of the figure is exactly the same as that of FIG. [First cycle] Data read from the memory 12 is stored (enqueued) in the queue 14. At this time, the queue 14 is empty, and data is stored at the head of the queue 14. The ECC circuit detects an error in the data read from the memory 12 and corrects a one-bit error.

[Second cycle] Return output driver 13
Invalidates the corresponding data stored at the head of the queue 14 and prohibits return to the access request source. ECC
The circuit stores the corrected data at the head of the queue 14. [Third cycle] The return output driver 13 sends the queue 1
The corresponding data stored at the head of No. 4 is extracted and returned to the access request source.

(4) Fourth pattern (1 bit error present, queue is not empty) FIG. 5 shows an operation timing chart of the fourth pattern. The description format of the figure is exactly the same as that of FIG. [First cycle] Data read from the memory 12 is stored (enqueued) in the queue 14. Since the data read and processed last time is stored at the head of the queue 14, the data read this time is stored next. The ECC circuit detects an error in the data read from the memory 12 and corrects a one-bit error.

[Second cycle] Return output driver 13
Retrieves the previously read data stored at the head of the queue 14 and returns it to the access request source. The control circuit 15 invalidates the error-detected data stored in the queue 14. The ECC circuit is queue 1
The corrected data is stored at the beginning of the fourth data. [Third cycle] Subsequently, the return output driver 13 takes out the corrected data from the queue 14 and returns it to the access request source.

(5) Fifth pattern (2-bit error detection, queue is empty) FIG. 6 shows an operation timing chart of the fifth pattern. The description format of the figure is exactly the same as that of FIG. [First cycle] Data read from the memory 12 is stored (enqueued) in the queue 14. At this time, the queue 14 is empty, and data is stored at the head of the queue 14. The ECC circuit detects an error in the data read from the memory 12 and corrects a one-bit error.

[Second cycle] Return output driver 13
Invalidates the corresponding data stored at the head of the queue 14 and prohibits return to the access request source. ECC
The circuit 16 stores the corrected data at the head of the queue 14. The ECC circuit 16 detects a 2-bit error. [Third cycle] The return output driver 13 sends the queue 1
The corresponding data stored at the top of No. 4 is invalidated, and return to the access request source is prohibited. The ECC circuit 16
Perform post-processing after detecting a 2-bit error.

(6) Sixth pattern (2-bit error detection, queue is not empty) FIG. 7 shows an operation timing chart of the sixth pattern. The description format of the figure is exactly the same as that of FIG. [First cycle] Data read from the memory 12 is stored (enqueued) in the queue 14. Since the data read and processed last time is stored at the head of the queue 14, the data read this time is stored next. The ECC circuit detects an error in the data read from the memory 12 and corrects a one-bit error.

[Second cycle] Return output driver 13
Retrieves the previously read data stored at the head of the queue 14 and returns it to the access request source. The control circuit 15 invalidates the error-detected data stored in the queue 14. The ECC circuit is queue 1
The corrected data is stored at the beginning of the fourth data. ECC circuit 16
Detects a 2-bit error. [Third cycle] The return output driver 13 sends the queue 1
The corresponding data stored at the top of No. 4 is invalidated, and return to the access request source is prohibited. The ECC circuit 16
Perform post-processing after detecting a 2-bit error.

[0028]

As described above, since the enqueue and the error detection are simultaneously performed on the data read from the memory at the same time, if there is no error at the next timing, the data is taken out from the queue and accessed in the next cycle. Can be returned to the requester. Therefore, if there is no error in the data, the speed of returning the data to the access request source is increased.
If an error is detected in the data, the already enqueued data is invalidated, and the error-corrected data is re-enqueued. If a return output driver is provided, data retrieved from the queue can be invalidated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a specific example of a memory control system according to the present invention.

FIG. 2 is an operation timing chart of a first pattern.

FIG. 3 is an operation timing chart of a second pattern.

FIG. 4 is an operation timing chart of a third pattern.

FIG. 5 is an operation timing chart of a fourth pattern.

FIG. 6 is an operation timing chart of a fifth pattern.

FIG. 7 is an operation timing chart of a sixth pattern.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 memory control circuit 11 memory access request device 12 memory 13 return output driver 14 queue 15 control circuit 16 ECC circuit

Claims (3)

[Claims] 1. An ECC circuit for detecting and correcting an error of data read from a memory by access, a queue for storing data before error detection read from the memory, and a queue extracted from an exit of the queue. A return output driver with an output enable for returning data to an access request source, and when the ECC circuit detects an error in the data, invalidates the corresponding data stored in the queue, or A control circuit for controlling the output driver for return to invalidate data extracted from the exit of the queue. 2. The system according to claim 1, wherein when the corresponding data stored in the queue is invalidated, the ECC circuit newly stores the data corrected by the ECC circuit in the queue. Characteristic memory control system. 3. The system according to claim 1, wherein the control circuit determines a data storage timing in the queue so that the data is held in the queue until the error detection of the data by the ECC circuit ends. A memory control system for setting a weight cycle to be adjusted.