JPH04255056A - Dma controller - Google Patents

Abstract

PURPOSE:To execute sure data transfer free from overrun even in a high operation frequency state by switching a transfer mode to single transfer with slow speed at the fixed number of bytes before the interruption of transfer. CONSTITUTION:A current count register block (CCR block) 11 in a count register block 1 calculates the number of remaining bytes not to be transferred to a memory (not shown). The remaining transfer byte number data 201 calculated by the block 11 are inputted to a control register block 2. Data for turning a low active DMARQ signal into an inactive state in each fixed number of bytes and interrupting transfer are stored in a transfer unit specifying register in a mask circuit 12 built in the block 2. At the time of transferring a demand or a block, the low active DMARQ is turned to the inactive state. Namely the transfer mode is switched to the single transfer before the end of transfer of each transfer unit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller.

0002

2. Description of the Related Art Conventionally used DMA controllers perform DMA transfer with three types of transfer modes in order to transfer data between an I/O device and memory or between memories at high speed.

These three methods are: single transfer, in which the bus is released every time a DMA transfer is completed; The mode register selects which mode to transfer between demand transfer, which continues DMA transfer until the end of the count register countdown, or block transfer, which continues DMA transfer until the end of the count register or an external transfer end signal is input. . Among these, demand transfer and block transfer have almost the same speed, and both are about twice the transfer speed of single transfer.

[0004] Here, an example of the timing of single transfer and demand transfer will be explained using FIGS. 5 and 6.

(1) Single transfer As shown in FIG. 5, a low active DMARQ signal (hereinafter referred to as DM
ARQ signal) is sampled, and if it is “L”, T
Move to H state. In TH state, HLDRQ
At the rising edge of the clock, the signal is set to "L" to request the CPU to occupy the bus. Next, HL from CPU
The DACK signal is sampled at the rising edge of the TH state clock, and the TH state is repeated until it becomes "L". When the HLDACK signal becomes "L", it moves to the T1 state. In the T1 state, address and bus control signals are output, and the BCYST signal is set to “L”. The state then becomes the T2 state. At the rising edge of the next clock after the T2 state, if the READYI signal is "H", a wait state is inserted. When the READY signal becomes active, the state transitions to T1.

(2) Demand transfer As shown in FIG. 6, at the rising edge of the clock in the T1 state, DM
The ARQ signal is sampled and a DMA cycle starts when it is "L". At the rise of T2 state, DMA
When the RQ signal is "L", the READYI signal is sampled at the next rising edge of the clock, and if it is "L", it moves to the T1 state and continues the DMA transfer cycle. DMARQ signal is “H”, TC, EO
If P and BERR are "L", the T1 state ends.

[0007]

[Problems to be Solved by the Invention] As shown in FIG. 7, when performing high-speed transfer using demand transfer or block transfer,
As the frequency increases, the speed increases and data transfer may overrun.

[0008] Let us take an example of demand transfer. For example, when transferring to a hard disk, D is sent every 256 bytes.
The MARQ signal becomes inactive and data transfer is interrupted. However, as the frequency increases, DMARQ
If the signal becomes L but shifts to the T2 state,
Since the DMARQ signal is still active at the rising edge of T2 when sampling is performed, the DMA controller determines that the transfer will continue, and ends up executing the transfer one more time.

An object of the present invention is to provide a DMA controller that can perform reliable data transfer without the risk of overrun even at high operating frequencies.

0010

[Means for Solving the Problems] The present invention provides a D
In the MA controller, a transfer unit specification register,
and conversion means for switching to single transfer before the end of transfer of the transfer unit in continuous transfer mode.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. Current count register block 11 (hereinafter referred to as CCR) is a part of count register block 1.
block) calculates the number of remaining bytes that have not yet been transferred to memory. This CCR block 1
The remaining transfer byte count data 201 calculated in step 1 is input to the control register block 2.

FIG. 2 is a schematic diagram of the inside of the control register block 2. As shown in FIG. The transfer unit designation register 102 stores data indicating every byte at which the DMARQ signal becomes inactive and the transfer is interrupted. The upper bit mask circuit 103 outputs the output 201 (
24 bits) (for example, if the transfer unit byte number is 256 bytes, bits 8 and above, and if the transfer unit number is 64 bytes, bits 6 and above) are masked to "0".

Comparison circuit 104 includes mode register A10.
The port width bit 207 and bus width bit 208 are taken in from 1. At the time of memory-to-memory transfer, that is, input signal M
When M is active, bus width bit, memory/IO
At the time of transfer (input signal from other block M M205
is inactive), the comparison circuit 104 selects the smaller bit of the bus width and port width, which determines the number of transfer bytes transferred in one bus cycle. The lower bit mask circuit 105 masks the bits up to which the transfer byte number is set (lower 3 bits for 4-bit transfer, lower 2 bits for 2-byte transfer) with "0". While this masked output 202 is all "0", that is, for two bus cycles after the transfer of the specified unit is completed and before the transfer is interrupted, the all-0 detection circuit 14 outputs the strobe signal 203.
Output.

Transfer mode conversion circuit 14 takes in transfer mode information stored in mode register 110. In the case of demand transfer or block transfer, the mode selection circuit 111 outputs the strobe signal 206, and only while the strobe signal 203 from the all-0 detection circuit 13 is output, that is, during the last two bus cycles before the transfer is interrupted. Output 204 specifies the mode for other blocks to perform a single transfer.

Next, another embodiment of the present invention will be described in detail with reference to FIG. FIG. 2 is a diagram of information in mode register A of this embodiment. Bit 5, which was originally undefined, is set as transfer mode conversion bit 209, which has information on whether or not to perform transfer mode conversion.If it is "0", no transfer mode conversion is performed;
If it is "1", it is assumed that transfer mode conversion has occurred.

FIG. 4 is a block diagram of this embodiment. The difference between this embodiment and the first embodiment is that the mode register A11
There is only output 209 from bit 5 of 0 and selector 16. Mode register A1 indicates whether or not to perform transfer mode conversion.
Specify with bit 5 209 of 10. Bit 5 is “0”
”, the input from the selector 16 to the transfer mode conversion circuit 15 is always “0” and no transfer mode conversion is performed.

[0017]

[Effects of the Invention] During demand transfer or block transfer, when DMARQ becomes inactive, that is, a certain number of bytes before the transfer is interrupted, the transfer mode is switched to a slow single transfer, thereby preventing overflow even at high operating frequencies. Data can be transferred reliably without the risk of running.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the invention.

FIG. 2 is a schematic diagram within the control register block in FIG. 1;

FIG. 3 is a schematic diagram of information in mode register A of a second embodiment of the invention.

FIG. 4 is a block diagram of a second embodiment.

FIG. 5 is a timing diagram during single transfer.

FIG. 6 is a timing diagram during demand transfer.

FIG. 7 is a timing diagram when an overrun occurs in demand transfer.

[Explanation of symbols] 1 Count register block 2 Control register block 3 Other blocks 11 in the DMA controller
Current count register block 12
Mask circuit 13 All 0 detection circuit 14 Transfer mode conversion circuit 15 Other blocks 16 in the control register
Selector 101 Mode register A 102 Transfer unit specification register 103 Upper bit mask circuit 104 Comparison circuit 105 Lower bit mask circuit 110 Mode register 111 Mode selection circuit 201 Remaining transfer byte number data 202
Remaining transfer byte count data after masking 203, 206
Strobe signal 204 Transfer mode specification data 205 Input signal M M 207 Port width data 208 Bus width data

Claims (1)

[Claims] 1. A DMA controller that specifies a single transfer mode and a continuous transfer mode by a register, comprising a transfer unit specification register and a conversion means for switching to single transfer before the end of transfer of the transfer unit in the continuous transfer mode. A DMA controller characterized by: