CN112802518A - Data writing method, system-on-chip and computer readable storage medium - Google Patents

Data writing method, system-on-chip and computer readable storage medium Download PDF

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CN112802518A
CN112802518A CN202110321248.8A CN202110321248A CN112802518A CN 112802518 A CN112802518 A CN 112802518A CN 202110321248 A CN202110321248 A CN 202110321248A CN 112802518 A CN112802518 A CN 112802518A
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data unit
data
block
address information
instruction address
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CN112802518B (en
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龙帆
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A data writing method, a system-on-chip and a computer readable storage medium, the method comprising: determining at least one data unit of data to be written and instruction address information corresponding to the data unit according to a single-frame written data volume of a PSRAM (programmable random access memory), wherein the single-frame written data volume is the data volume written in the low-level time of a chip selection signal corresponding to the PSRAM; generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list, the block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used for indicating a next block to be sent of the block when the block linked list is transmitted; and sending the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list through a DMA controller. High-speed writing to the PSRAM can be realized.

Description

Data writing method, system-on-chip and computer readable storage medium
Technical Field
The present application relates to the field of chips, and more particularly, to a data writing method, a system-on-chip, and a computer-readable storage medium.
Background
Compared with a Dynamic Random Access Memory (DRAM), a Pseudo Static Random Access Memory (PSRAM) adopts a Self refresh (Self refresh) mechanism, and internal data can be refreshed at regular time without an additional refresh circuit, so that data loss is avoided.
When a microcontroller (Micro control unit, MCU) or a System On Chip (SOC) type main control chip accesses a PSRAM, since a self-refresh mechanism of the PSRAM limits the longest pull-down time of a chip select signal cs (chip select), the data throughput of the PSRAM accessed each time is limited, so that the MCU/SOC cannot access the PSRAM with a single as large as possible payload as access to a flash memory device, thereby greatly limiting the access efficiency to the PSRAM.
Disclosure of Invention
The embodiment of the application provides a data writing method, a System On Chip (SOC) chip and a computer readable storage medium, and under the condition that an IP controller is not adopted, the access efficiency of a PSRAM is effectively improved.
In a first aspect, a method for writing data is provided, which includes: determining at least one data unit of data to be written into a Pseudo Static Random Access Memory (PSRAM) and instruction address information corresponding to the data unit according to a single-frame written data volume of the PSRAM, wherein the single-frame written data volume is the data volume written in the low-level time of a chip selection signal corresponding to the PSRAM; generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list, the block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used for indicating a next block to be sent of the block when the block linked list is transmitted; and accessing a DMA controller through a direct memory, and sending the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list.
According to the embodiment of the application, a DMA controller with hardware circuit support is introduced in the process of writing the PSRAM by software, a software layer divides data to be sent at one time through a software instruction and determines the data to be sent into at least one data unit and instruction address information corresponding to the data unit, the instruction address information corresponding to the data unit and the data unit generate at least one block, each block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, the at least one block orderly forms a block linked list through the pointer information, and the data is sent to the PSRAM through the DMA controller in the form of the block linked list, so that the time of the software instruction indication consumed by the software layer for dividing, configuring and sending the data for multiple times is saved, the access efficiency of the PSRAM is effectively improved, and high-speed writing of the PSRAM is realized.
It should be understood that if the instruction address information corresponding to the data unit and the data unit respectively generate different blocks for transmission, in the block linked list, the block to be sent next to the block including the instruction address information corresponding to the data unit is the block including the data unit.
In one possible implementation, the block further includes: configuration information for instructing the DMA controller to transfer instructions required for the block.
In the embodiment of the present application, each block has corresponding configuration information, that is, the configuration information of each block may be different, and the DMA controller can transmit the blocks through different configurations, thereby improving flexibility and freedom of accessing the PSRAM.
In one possible embodiment, the instruction includes at least one of a transfer direction instruction, a transfer channel instruction, a transfer speed instruction, and a transfer data width instruction for the DMA controller to transfer the block.
In the embodiment of the application, the DMA controller can transmit data with different data sizes, different transmission directions and different transmission paths at different transmission speeds by configuring the plurality of transmission instructions required for transmitting each block through the configuration information, thereby further improving the flexibility of data transmission.
In a possible implementation manner, the generating at least one block according to the instruction address information corresponding to the data unit and the data unit includes: and generating a block according to the instruction address information corresponding to the data unit and the data unit, wherein the block comprises the configuration information, the pointer information, the instruction address information corresponding to the data unit and the data unit.
It should be understood that the software layer may store the data into the cache space matching the data format of the block in the memory after processing the data into the block, that is, a new cache space matching the instruction address information corresponding to the data unit and the data unit may be created in the memory, and the instruction address information corresponding to the data unit and the data unit may be stored before data transmission.
In a possible implementation, the generating at least one block according to the instruction address information corresponding to the data unit and the data unit includes: and generating a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, wherein the first block comprises the configuration information of the first block, the pointer information of the first block and the instruction address information corresponding to the data unit, and the second block comprises the configuration information of the second block, the pointer information of the second block and the data unit.
The method and the device have the advantages that the instruction address information and the data units corresponding to the data units are respectively configured into the first block and the second block, so that the blocks with special data width do not need to be stored into the additionally opened new cache space in the process of sending data to the PSRAM by the DMA controller, the blocks can be directly written into the existing cache space of the MCU/SOC, the memory and software instructions for carrying data from the new cache space are saved, and the access efficiency to the PSRAM is further improved.
In one possible embodiment, the method further comprises: and determining instruction address information corresponding to the data unit and the data volume of the data unit sent by the DMA controller, and pulling up the chip select signal when the data volume is equal to a preset data volume, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
According to the embodiment of the application, the chip selection signal cannot be pulled up when the transmitted data volume does not reach the threshold value by controlling the chip selection signal, the situation that the chip selection signal is accidentally pulled up before data transmission is finished is avoided, normal transmission of data is guaranteed, and the stability of an access program is improved.
In a possible implementation manner, the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
In the embodiment of the application, the instruction address information corresponding to the data unit and the front selection signal sent by the data unit are controlled not to be pulled up, so that data can be normally transmitted. Under the condition that the instruction address information and the data units corresponding to the data units are respectively configured into the first block and the second block, the chip selection signal can be ensured to be pulled up after the second block is sent, on one hand, the problem that the first block and the second block cannot be continuously sent and the instruction address information and the data units corresponding to the data units cannot be continuously written and finally data writing errors are caused because the chip selection signal is pulled up after the first block is sent is avoided in the block sending process, on the other hand, the pulling-down time of the chip selection signal is utilized to the maximum extent, the data transmission efficiency is improved, and therefore the access efficiency to the PSRAM is improved.
In one possible implementation, the sending, by the DMA controller, the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list includes: and writing the instruction address information corresponding to the data unit and the data unit into a cache through the DMA controller, and sending the instruction address information corresponding to the data unit and the data unit to the PSRAM through the cache.
According to the embodiment of the application, the cache is arranged between the DMA controller and the PSRAM, the data transmission speed can be controlled, the phenomenon that the data transmission speed is too high to cause package sticking is avoided, namely the block is not sent to the completion time when the next block to be sent enters the cache, after the block is sent to the completion time, a chip selection signal is not pulled up to cause circuit abnormity, normal data transmission is further ensured, and the stability of a program when the PSRAM is accessed and the reliability of the program running in a complex environment are improved.
In one possible embodiment, the method further comprises: and controlling a first writing speed not to be larger than the sending speed of the cache, and controlling a second writing speed not to be larger than the sending speed, wherein the first writing speed is the speed of writing the instruction address information corresponding to the data unit into the cache by the DMA controller, the second writing speed is the speed of writing the data unit into the cache by the DMA controller, and the sending speed is the speed of sending the instruction address information corresponding to the data unit and the data unit to the PSRAM by the cache.
It should be understood that the first speed and the second speed may be equal, that is, when the instruction address information corresponding to the data unit and the data unit generate one block, the first speed and the second speed are equal and both are less than the sending speed, and the instruction address information corresponding to the data unit and the data unit are sent to the cache in sequence. When the instruction address information corresponding to the data unit and the data unit respectively generate the first block and the second block, the first speed and the second speed are both smaller than the sending speed, and the instruction address information corresponding to the data unit and the data unit are sent to the cache sequentially at the first speed and the second speed respectively.
According to the embodiment of the application, the speed of writing the block into the cache is controlled not to be larger than the sending speed of sending the information and/or data in the block out of the cache, so that the filling speed of the block in the cache can be controlled, and the phenomenon of packet sticking caused by the excessively high writing speed is effectively avoided. For example, when the instruction address information corresponding to the data unit in the first block is not sent out from the cache, the second block is already written into the cache, and the sticky packet will cause the chip select signal to be unable to be normally released after the information in the first block is sent out, thereby causing the circuit to work abnormally. By controlling the write-in speed not to be greater than the sending speed, the next block to be sent can be ensured to enter the cache after the block transmission is finished, the chip selection signal can be pulled high after the block transmission is finished, the data package sticking is effectively avoided, and the efficiency of accessing the PSRAM is further improved.
In one possible embodiment, the method further comprises: determining instruction address information corresponding to the data unit and data volume of the data unit sent by the DMA controller; controlling a first writing speed to be not more than a sending speed of the cache, and controlling a second writing speed to be not more than the sending speed, wherein the first writing speed is a speed for the DMA controller to write instruction address information corresponding to the data unit into the cache, the second writing speed is a speed for the DMA controller to write the data unit into the cache, and the sending speed is a speed for the instruction address information corresponding to the data unit and the data unit to be sent to the PSRAM by the cache; and when the data volume sent at the sending speed is equal to a preset data volume, pulling up the chip selection signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
According to the embodiment of the application, the normal pull-up of the chip selection signal is ensured by controlling the filling speed of the block in the cache and controlling the pull-up condition of the chip selection signal, the stability of a program when the PSRAM is accessed in a complex environment can be further improved, and the access program is ensured to safely and efficiently run in the complex environment.
In one possible embodiment, the method further comprises: after the DMA controller sends the instruction address information corresponding to the data unit and the data unit, write-back information sent by the DMA controller is received, wherein the write-back information is used for indicating that the instruction address information corresponding to the data unit and the data unit are sent completely, and the write-back information comprises the instruction address information corresponding to the data unit and the state information and/or the position information of the data unit.
In the embodiment of the application, the write-back operation is executed after the block is written in and before the next block to be sent is written in by the DMA controller by receiving the write-back information sent by the DMA controller, the software layer can consume some software instructions by receiving the write-back information sent by the DMA controller, the time interval between the block and the next block to be sent in the process of transmitting the block linked list is increased, the phenomenon of data package sticking is avoided, and the safety and the stability of accessing the PSRAM are further improved.
In a second aspect, a system on chip SOC chip is provided, including:
the processor is used for determining at least one data unit of data to be written into the PSRAM and instruction address information corresponding to the data unit according to a single-frame written data volume of the PSRAM, wherein the single-frame written data volume is the data volume written in the low-level time of a chip selection signal corresponding to the PSRAM; generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list, the block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used for indicating a next block to be sent of the block when the block linked list is transmitted;
and the DMA controller is used for sending the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list.
In one possible implementation, the block further includes: configuration information for instructing the DMA controller to transfer instructions required for the block.
In one possible embodiment, the instruction includes at least one of a transfer direction instruction, a transfer channel instruction, a transfer speed instruction, and a transfer data width instruction for the DMA controller to transfer the block.
In one possible implementation, the processor is configured to: and generating a block according to the instruction address information corresponding to the data unit and the data unit, wherein the block comprises the configuration information, the pointer information, the instruction address information corresponding to the data unit and the data unit.
In one possible implementation, the processor is configured to: and generating a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, wherein the first block comprises the configuration information of the first block, the pointer information of the first block and the instruction address information corresponding to the data unit, and the second block comprises the configuration information of the second block, the pointer information of the second block and the data unit.
In one possible implementation, the processor is further configured to: and determining instruction address information corresponding to the data unit and the data volume of the data unit sent by the DMA controller, and pulling up the chip select signal when the data volume is equal to a preset data volume, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
In a possible implementation manner, the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
In one possible implementation, the chip further includes:
caching;
the DMA controller is used for writing the instruction address information corresponding to the data unit and the data unit into the cache, and the cache is used for sending the instruction address information corresponding to the data unit and the data unit written by the DMA controller to the PSRAM.
In one possible implementation, the processor is further configured to: and controlling a first writing speed not to be larger than the sending speed of the cache, and controlling a second writing speed not to be larger than the sending speed, wherein the first writing speed is the speed of writing the instruction address information corresponding to the data unit into the cache by the DMA controller, the second writing speed is the speed of writing the data unit into the cache by the DMA controller, and the sending speed is the speed of sending the instruction address information corresponding to the data unit and the data unit to the PSRAM by the cache.
In one possible implementation, the chip further includes: caching; the processor is further configured to: determining instruction address information corresponding to the data unit and data volume of the data unit sent by the DMA controller; controlling a first writing speed to be not more than a sending speed of the cache, and controlling a second writing speed to be not more than the sending speed, wherein the first writing speed is a speed for the DMA controller to write instruction address information corresponding to the data unit into the cache, the second writing speed is a speed for the DMA controller to write the data unit into the cache, and the sending speed is a speed for the instruction address information corresponding to the data unit and the data unit to be sent to the PSRAM by the cache; and when the data volume sent at the sending speed is equal to a preset data volume, maintaining the high level state of the chip selection signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
In one possible implementation, the processor is further configured to: after the DMA controller sends the instruction address information corresponding to the data unit and the data unit, write-back information sent by the DMA controller is received, wherein the write-back information is used for indicating that the instruction address information corresponding to the data unit and the data unit are sent completely, and the write-back information comprises the instruction address information corresponding to the data unit and the state information and/or the position information of the data unit.
In a third aspect, a computer-readable storage medium is provided, in which computer-executable instructions are stored, and when executed by a processor, the computer-executable instructions are configured to implement the method for data writing according to any one of the possible implementation manners of the first aspect.
In summary, in the scheme of the embodiment of the present application, the data to be sent is determined as the block linked list based on the processor, and is sent to the PSRAM through the DMA controller, which greatly saves the time and software instructions for software layer to repeatedly process and configure the data to be sent, improves the write efficiency of the PSRAM device, and enables the PSRAM device to reach the IP controller level.
Drawings
Fig. 1 is a schematic diagram of a main control chip and an external device according to an embodiment of the present disclosure.
Fig. 2 is a diagram illustrating a PSRAM access timing sequence according to an embodiment of the present application.
FIG. 3 is a flow chart of a software write controller writing data according to an embodiment of the present application.
FIG. 4 is a timing diagram of a software write controller writing data according to an embodiment of the present application.
FIG. 5 is a logic diagram of a software write controller writing data according to an embodiment of the present application.
Fig. 6 is a flowchart of a method for writing data according to an embodiment of the present application.
FIG. 7 is a timing frame diagram according to an embodiment of the present application.
Fig. 8 is a schematic diagram of a block chain table according to an embodiment of the present application.
Fig. 9 is a schematic diagram of another block linked list according to an embodiment of the present application.
Fig. 10 is a schematic diagram of another block chain table according to an embodiment of the present application.
FIG. 11 is a diagram illustrating a relationship between a block and a chip select signal according to an embodiment of the present disclosure.
FIG. 12 is a schematic diagram of a FIFO according to an embodiment of the present application.
Fig. 13 is a schematic diagram of an SOC chip according to an embodiment of the present application.
Fig. 14 is a schematic diagram of another SOC chip according to an embodiment of the present application.
FIG. 15 is a schematic diagram of a software write controller according to an embodiment of the present application.
FIG. 16 is a logic diagram of a software controller writing data according to an embodiment of the present application.
Detailed Description
The technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the following description, numerous specific details are set forth, such as examples of specific types of processor core system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present application. In other instances, well known components or methods, such as specific or alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific algorithm code expressions, specific power down and gating techniques/logic, and other specific operational details of computer systems have not been described in detail in order to avoid unnecessarily obscuring the present application.
With the development of computer System architecture, System components such as a Central Processing Unit (CPU), a memory controller, and an input/output (I/O) hub are no longer externally interconnected in a discrete form, but are integrated on a master chip such as a Microcontroller (MCU) and a System On Chip (SOC), and the MCU/SOC is connected to a peripheral device for access through a serial interface or a parallel interface.
Fig. 1 is a schematic diagram of a main control chip and an external device according to an embodiment of the present disclosure. The main control chip 100 is composed of a software layer 101 and a hardware layer 102, and the software layer 101 can control each hardware of the hardware layer 102 to implement different functions through software instructions, for example, the main control chip can be controlled by a processor to perform various read and write operations. The software layer 101 includes various controllers, logic circuits, and the like for implementing different functions, and the hardware layer 102 includes at least one Microprocessor (MPU) or Digital Signal Processor (DSP), a memory, a hardware circuit, an interface management module for managing different physical interfaces, a converter for converting a Digital signal and an analog signal, an oscillator for providing a Clock signal (CLK), and the like, where the memory may be one or more Read-only memories (ROMs), Random Access Memories (RAMs), flash memories, and the like. The MCU/SOC and other main control chips can realize multifunctional integration through synchronous design of a software layer and a hardware layer. In addition, because the memory space of the memory is limited, the main control chip 100 may be externally connected to a plurality of memory devices 103, 104 and the like through serial/parallel interfaces of the hardware layer, and these external memory devices may be Static Random Access Memories (SRAMs), Dynamic Random Access Memories (DRAMs), Pseudo Static Random Access Memories (PSRAMs) and the like.
The PSRAM is a memory which adopts DRAM process technology to realize the function effect similar to that of SRAM and has the advantages of simple interface, large storage capacity and the like. In the current intelligent wearable market, the PSRAM has become an ideal choice for expanding the RAM storage space and resource data caching of the MCU/SOC, and is one of the common external devices of the MCU/SOC.
The traditional PSRAM is controlled by adopting a parallel interface, and a main control chip such as an MCU/SOC (micro control unit/system on chip) and the like needs to consume more pin resources when accessing the PSRAM, so that Serial PSRAMs supporting single-wire Serial Peripheral Interfaces (SPI) and four-wire Serial peripheral interfaces (QSPI) are provided by some PSRAM manufacturers in recent years, and the application prospect of the PSRAM is further expanded.
The PSRAM adopts a self-refresh mechanism, and unlike DRAM equipment which needs an additional refresh circuit to control a memory unit to refresh data regularly, the PSRAM can refresh the data regularly, so that the data loss is avoided. This also results in that the longest pull-down time of the chip select signal CS (chip select) in the access cycle of the MCU/SOC accessing the PSRAM cannot exceed the self-refresh time of the PSRAM, and exceeding the longest pull-down time of the CS signal without releasing the CS signal causes the PSRAM self-refresh circuit to operate abnormally, thereby resulting in error of the access data. Therefore, when the MCU/SOC accesses the PSRAM, the MCU/SOC cannot access the PSRAM as much as a direct access flash memory by adopting the largest effective load once, but is limited by the longest pull-down time of the CS signal, and data transmission is completed through multiple accesses, so that the access efficiency of the MCU/SOC to the PSRAM is greatly limited.
When the main control chip such as MCU/SOC writes data into the external storage equipment such as PSRAM, etc., the hardware layer is controlled by the write controller of the software layer. Fig. 2 is a schematic diagram of an access timing sequence of a PSRAM supporting an SPI and QSPI interface according to an embodiment of the present application. A write access cycle of the MCU/SOC to the PSRAM starts from the CS signal being pulled low to the end of the CS signal being pulled high, during which the write controller of the MCU/SOC controls the hardware layer to write data into the PSRAM in a manner of transmitting a timing frame. A sequential frame sent to PSRAM is typically composed of 3 parts: a 1-byte Instruction (Instruction) portion, a 3-byte Address (Address) portion, and a number of bytes of Data (Data) portion. The instruction part of 1 byte and the address part of 3 bytes are necessary overhead when the PSRAM is accessed, the time consumption for writing the time sequence frame into the PSRAM cannot exceed the longest pull-down time of the CS signal, otherwise, the self-refresh mechanism of the PSRAM will cause access errors.
At present, there are two types of write controllers for writing data into the PSRAM by the MCU/SOC: one type is an intellectual property IP write controller which can be directly integrated on an MCU/SOC, and the write controller has a general write controller function and also has a control circuit specially designed for the longest CS signal pull-down time corresponding to the PSRAM, can automatically segment, construct a time sequence frame and send data in the IP write controller, does not waste extra software instructions of a software layer, and only needs to perform related configuration through a register in an MCU/SOC memory exposed by the IP write controller, so that the work efficiency is high, but additional research and development design or purchase authorization is needed, and the cost is high.
The other type is a software writing controller, based on the existing structure and function on the MCU/SOC, through software layer design, the data volume written each time is reduced according to the longest CS signal pull-down time in a software control mode, data is segmented, configured and transmitted for multiple times, an additional IP writing controller is not needed to be added in the MCU/SOC, and data writing on the PSRAM can be achieved based on the existing data writing scheme, for example, the data writing scheme of a flash memory device. Specifically, fig. 3 is a flowchart of writing data by a software write controller according to an embodiment of the present application, where the flowchart is executed by the software write controller of the MCU/SOC:
s301, according to the access sequence of the PSRAM, register configuration is carried out.
Specifically, the access timing of the PSRAM is provided by the manufacturer when the PSRAM is shipped, and the register configuration includes instruction-related, address-related, timing-related, and data-related register configurations.
Illustratively, the register configuration includes at least: setting an access instruction in an instruction register, setting a width of the access instruction in an instruction width register, setting a transmission mode of the access instruction in an instruction mode bit register, setting a width of an access address in an address width register, setting a transmission mode of the access address in an address mode bit register, setting a number of clock signals in a timing (Dummy) number register, setting a transmission mode of data in a data mode register. Wherein the transmission mode has a single line mode or a multi-line mode.
S302, constructing a time sequence frame according to the access time sequence.
Specifically, the time-series frame comprises an instruction, an address, a time sequence and data with a certain length, wherein the data length is calculated by the software layer according to the longest CS signal pull-down time.
And S303, sending the constructed time sequence frame to the PSRAM.
S304, judging whether the data to be sent is sent completely. If yes, go to S305; if not, S301 is executed.
S305, the write operation is ended.
Currently, the longest CS signal pull-down time of PSRAMs produced by PSRAM suppliers in the industry mainstream takes 8 μ s as a standard, a for/while logical connection is adopted between a timing frame and a timing frame, a timing resource occupied by sending the timing frame is an effective write-in time, and a time interval between every time of sending the timing frame is T. FIG. 4 is a timing diagram of a software write controller writing data according to an embodiment of the present application. However, when the amount of data to be written is large, the method for realizing PSRAM write access by the software write controller needs to segment data, construct a timing frame, and send the timing frame through software instructions, and in addition, the consumption of software instructions such as system scheduling is added, and compared with the IP write controller, much time is wasted, so that the time interval T is too long, generally on the order of tens of microseconds, and compared with the effective write time (8 μ s), the proportion of time-series resource waste is too large, and the access rate of the PSRAM is seriously affected.
Illustratively, as shown in fig. 5, the PSRAM write flow is performed using for/while logic, and in the case where the serial interface maximum operating frequency SCLK is 48 MHz and the four-wire mode is adopted, the data payload is 128 bytes. The access flow is operated in the logic controller, the CS signal is pulled down for 6.5-6.8 mus, namely the effective time for transmitting data is 6.5-6.8 mus; the time interval between the time sequence frames is about 70 mus, namely the time for waiting for data to be segmented and constructed into the time sequence frames is 70 mus, the time interval is extremely unstable, when a system is scheduled, the time interval is far larger than 70 mus, the ratio of effective time to invalid time is 6.8 mus to 70 mus, namely 0.097 to 1, and the time sequence resource waste is serious.
In view of this, the present application designs a data writing method based on the existing functions and structures of the MCU/SOC main control chip without additionally providing an IP controller, and is applied to the MCU/SOC chip, so as to reduce the time interval T and enable the access efficiency of the software write controller to the PSRAM to reach the level of the IP write controller.
In the embodiment of the present application, an SOC chip supporting a QSPI interface is taken as an example, and it should be understood that the method described in the embodiment of the present application is also applicable to other MCU/SOC chips supporting SPI and QSPI interfaces.
In the embodiment of the application, pulling up the chip selection signal, namely releasing the chip selection signal, maintains the high level state of the chip selection signal until the chip selection signal is pulled down after the chip selection signal is pulled up, and maintains the low level state of the chip selection signal until the chip selection signal is pulled up after the chip selection signal is pulled down.
Fig. 6 is a flowchart of a data writing method according to an embodiment of the present application.
S601, determining at least one data unit of data to be written into a PSRAM and instruction address information corresponding to the data unit according to single-frame written data quantity of the PSRAM, wherein the single-frame written data quantity is the data quantity written in the low-level time of a chip selection signal corresponding to the PSRAM;
s602, generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list;
s603, sending the instruction address information corresponding to the data unit and the data unit based on the block linked list through the DMA controller.
Before executing S601, the software writing controller determines the writing data amount of a single frame of the PSRAM according to the pulling-down time of the CS signal, the working frequency of the serial interface and the working mode of the serial interface. The maximum working frequency of the serial interface is related to the crystal frequency of hardware, and the working mode of the serial interface is used for determining the data bit number transmitted by each clock signal. The single-frame write data volume is the data volume written in the time of the low level of the chip selection signal corresponding to the PSRAM, namely the maximum data volume which can be written in the time of the PSRAM when the CS signal is pulled down. The time that the CS signal is pulled low is the time that the SOC needs to maintain the low level of the CS signal.
As a possible implementation, the write data amount of a single frame of PSRAM can be determined by the following algorithm:
#define PLAYLOAD(SCLK, MODE_BITS, t_CEM) = (SCLK/1000000u)*(MODE_BITS/8)*t_CEM
the PLAYLOAD is a frame write data amount of the PSRAM, SCLK is a maximum working frequency of the serial interface, MODE _ BITS is a data bit number transmitted by each clock signal in a working MODE of the serial interface, t _ CEM is a CS signal pull-down time, 1000000u is 1000000 μ s, and 1/1000000u is 1 MHz. For example, the QSPI of an SOC has an operating frequency of 48 MHz, a MODE _ BITS of 4 in a 4-line operating MODE is 4, and a typical CS signal pull-down time is 8 μ s, so that theoretically the write data amount of a single frame of the PSRAM is 48 × 8 (4/8) × 192 bytes. It should be appreciated that in practical applications, the actual amount of written data of less than 192 bytes is used in consideration of the amount of secure redundancy of the data.
It should be understood that the above-mentioned code for determining the amount of data written in a single frame of PSRAM is only one of the determination methods, and any of the above-mentioned codes, or a code or a combination of codes capable of determining the amount of data written in a single frame of PSRAM using the longest CS signal pull-down time, the largest operating frequency of the serial interface, and the operating mode of the serial interface may be substituted for the above-mentioned code.
As a possible implementation, the amount of data written in a single frame of PSRAM can also be determined using the following code:
#define CLK_FREQ_1MHz 1000000u
#define PSRAM_SAFE_tCEM_US 8u/*Typical tCEM is 8us*/
#define QSPI_LANES 4u/*Quad mode: 4 lanes*/
#define PSRAM_MAX_PAYLOAD(qclk) ((PSRAM_SAFE_tCEM_US*qclk*QSPI_LANES)/(8u*CLK_FREQ_1MHz))/*qclk unit is MHz */
exemplarily, in S601, as shown in fig. 7, the determining, by the software write controller, at least one data unit to be written in the PSRAM data and the instruction address information corresponding to the data unit according to the single-frame write data amount of the PSRAM includes:
dividing data to be sent with a certain width into n data parts, wherein the data size of each data part is the write data size of a single frame of the PSRAM, and the n data parts are configured into n data units and corresponding instruction address information, wherein the instruction address information comprises instruction information and address information. Keeping the instruction information of the n time sequence frame information to be the same, wherein the data width is 1 byte; and updating the address information of the n time sequence frame information, wherein the data width is 3 bytes. Specifically, the address information includes start address information and buffer address information, and the update address information is address offset and buffer offset for updating n time series frames.
Specifically, in S602, after determining a data unit and instruction address information corresponding to the data unit, the software write controller generates at least one block, where the at least one block forms a block linked list, the block includes pointer information, instruction address information corresponding to the data unit, and/or the data unit, and the pointer information is used to indicate a next block to be sent of the block when the block linked list is transmitted.
Direct Memory Access (DMA) is an interface technology in which an external device directly exchanges data with a system memory without passing through a Central Processing Unit (CPU), a DMA controller directly transmits and receives data through a bus, and a block linked list is one of functions that a DMA controller has in an MCU/SOC device. As shown in fig. 8, data is transmitted in units of blocks in the block chain table, and the arrows indicate the transmission order of information. The pointer information may link the plurality of blocks having a sequential order such that the DMA controller sequentially transmits the plurality of blocks in the linked order. And after the block data is sent, the DMA controller automatically loads the data of the next block to be sent of the block in the block linked list according to the pointer information of the block and sends the data until the pointer information of the linked list is empty.
Optionally, the block includes configuration information, pointer information, instruction address information corresponding to the data unit, and/or the data unit, where the configuration information is used to instruct the DMA controller to transmit an instruction required by the block.
In this embodiment, each block has configuration information, and the DMA controller can transmit the block through different configurations, thereby improving flexibility and freedom of data transmission.
Optionally, the configuration information includes at least one of a transfer direction instruction, a transfer channel instruction, a transfer speed instruction, and a transfer data width instruction for the DMA controller to transfer the block.
In this embodiment, the DMA controller can transmit data of different data sizes, different transmission directions, and different transmission paths at different transmission speeds by configuring a plurality of transmission instructions required for transmitting each block with the configuration information, thereby further improving the flexibility of data transmission of the software writing controller.
Optionally, the configuration information further includes: number of DMAs, bus Burst (Burst) behavior, buffer address, write target address, buffer data width, etc.
In this embodiment, the number of the DMAs and the bus Burst behavior are configured so that the software write controller can select multiple DMA controllers to transmit data according to the situation of data to be sent, determine the number of times of each DMA transmission, configure the buffer address, write target address and buffer data width so that the software write controller can send blocks to different buffer areas, dynamically adjust the data transmission route, and further improve the flexibility of data transmission.
In S603, the software write controller sends, through the DMA controller, the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list.
Compared with the method that the software write controller directly sends the time sequence frames, the software layer configures the data to be sent into blocks, the DMA controller sends the data to be sent in the MCU/SOC memory in a chain mode in the form of the blocks, as the DMA controller sends the blocks according to the block chain table and is based on a hardware circuit, excessive software instructions are not needed, and the time interval for sending each block is far smaller than the time interval T for sending each time sequence frame in the data transmission process.
In the embodiment of the application, a DMA controller with hardware circuit support is introduced in the process of writing the PSRAM by software, the data to be sent is segmented and determined into at least one data unit and instruction address information corresponding to the data unit at one time by the software writing controller based on a processor, generating at least one block by the instruction address information corresponding to the data unit and the data unit, wherein each block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, the at least one block orderly forms a block linked list by the pointer information, the data is sent to the PSRAM in the form of the block linked list through the DMA controller, so that the time of the software writing controller consuming software instruction to divide, configure and send the data for multiple times is saved, the access efficiency of the software writing controller to the PSRAM is effectively improved, and the high-speed writing of the PSRAM is realized.
It should be understood that, if the instruction address information corresponding to the data unit and the data unit respectively generate different blocks for transmission, in the block chain table, the next block to be sent of the block including the instruction address information corresponding to the data unit is the block including the data unit, and the DMA controller sequentially sends the block including the instruction address information corresponding to the data unit and the block including the data unit to the PSRAM.
Optionally, in an embodiment, as shown in fig. 9, the software write controller generates a block according to the instruction address information corresponding to the data unit and the data unit, where the block includes the configuration information, the pointer information, the instruction address information corresponding to the data unit, and the data unit.
In this embodiment, the instruction address information and the data units corresponding to the data units are configured into blocks, so that the DMA controller can transmit the blocks in a block linked list manner, a software layer does not need to consume software instructions to send data, and the working efficiency of the software write controller is improved.
It should be understood that after the software write controller processes the data into blocks, the blocks may be stored in the memory, that is, a new cache space matching the instruction address information corresponding to the data unit and the data unit may be created in the memory, and the instruction address information corresponding to the data unit and the data unit may be stored before data transmission.
Specifically, since 4 bytes of instruction address information is necessary overhead for writing data into the PSRAM, in consideration of the continuity of the address information and the data width, after the block information is configured, a new buffer space is used to store data to be transmitted in the MCU/SOC memory, and the data width of the new buffer space is the sum of the number of bytes of the data unit and the number of bytes of the instruction address information corresponding to the data unit.
Optionally, in an embodiment, as shown in fig. 10, the block list is another schematic diagram of the block list according to the embodiment of the present application. And the software writing controller generates a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, wherein the first block comprises the configuration information of the first block, the instruction address information corresponding to the data unit and the pointer information of the first block, and the second block comprises the configuration information of the second block, the data unit and the pointer information of the second block. That is, when the software writing controller generates a data unit and a block corresponding to the corresponding instruction address information, the software writing controller respectively generates one instruction address information and corresponding data into a first block and a second block.
The instruction address information and the corresponding data are respectively configured into the corresponding first block and the second block, the data can be directly stored into the existing cache space of the MCU/SOC, a new cache space does not need to be opened up for the blocks due to the special data width of the blocks, the memory space and the software instruction for carrying the data from the new cache space are saved, a block linked list can be flexibly constructed, the complexity of the software instruction is reduced, and the working efficiency of the software writing controller is improved.
Fig. 11 is a schematic diagram of a relationship between a block and a chip select signal according to an embodiment of the present application, which illustrates an ideal state of sending data to a PSRAM by using a DMA controller, that is, before command address information corresponding to a data unit and the data unit start to be sent, a CS signal is pulled low, and after the command address information corresponding to the data unit and the data unit are sent, a CS signal is pulled high. That is, the CS signal is pulled low before the first block is transmitted, and the CS signal is pulled high after the second block is transmitted.
In the actual operation process of software, there is a case that other external devices occupy a bus, so that the DMA controller cannot send the instruction address information and the data unit corresponding to the data unit to the cache in time, and particularly when the instruction address information and the data unit corresponding to the data unit are respectively configured as the first block and the second block, a situation that data in the second block to be sent lacks the instruction address information and cannot be written into the PSRAM due to unexpected release of a CS signal after the cache has sent the first block may occur, resulting in data errors.
Optionally, in an embodiment, the method further includes determining instruction address information corresponding to the data unit and a data amount of the data unit sent by the DMA controller, and pulling up the chip select signal when the data amount is equal to a preset data amount, where the preset data amount is a threshold determined according to the instruction address information corresponding to the data unit and the data unit.
In order to ensure that the CS signal is not released and remains at a low level until the block transmission is completed when the DMA controller transmits data to the PSRAM, a counter may be provided at the QSPI interface to count the amount of data flowing from the QSPI. When the data amount corresponding to the counting value of the counter does not reach the preset data amount, the CS signal is not pulled up, the CS signal keeps the low level pull-down state all the time, and data are written into the PSRAM from the MCU/SOC; when the data amount corresponding to the counting value of the counter reaches the preset data amount, the CS signal is pulled up, the low level is not maintained any more, the writing operation in one period is finished, and the counter is reset to start counting again.
According to the embodiment of the application, the chip selection signal cannot be pulled up when the transmitted data volume does not reach the threshold value by controlling the chip selection signal, the situation that the chip selection signal is accidentally pulled up before data transmission is finished is avoided, normal transmission of data is guaranteed, and the running stability of the software writing controller is improved.
Optionally, in an embodiment, the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
Specifically, after data writing is started, every time one beat of data flows from the QSPI to the PSRAM, the value of the counter is increased by 1, when the count value of the counter does not reach a preset count value, the chip selection signal is kept in a low level state all the time, when the count value of the counter is equal to a preset threshold value, the chip selection signal is released and pulled high, the low level is not kept any more, the writing operation in one period is finished, and the counter is reset to start counting again.
Specifically, the preset count value of the counter is obtained by configuring the instruction address information corresponding to the data unit and the data size of the data unit in units of beats, and the data size corresponding to the preset count value is the preset data size. That is, the data amount corresponding to the preset count value of the counter is equal to the instruction address information corresponding to the data unit and the data amount of the data unit. When the bus data width HSIZE is different, the data amount corresponding to the counter beat number is also different. For example: when the bus width is 8 bits (bit), the unit of 1 beat of data is byte; when the bus width is 16bit, the unit of 1 beat of data is half word; when the bus width is 32 bits, the unit of 1 beat of data is a word.
In this embodiment, by setting the counter at the QSPI interface, it can be ensured that the CS signal is not pulled high before the command address information corresponding to the data unit and the data unit are sent, so that the data can be normally transmitted. Under the condition of the first block and the second block, the CS signal can be guaranteed to be pulled up after the second block is sent, on one hand, the problem that the command address information and the data units corresponding to the data units cannot be continuously written into the data units and finally data writing errors are caused due to the fact that the chip select signal is possibly pulled up after the first block is sent in the block sending process is solved, on the other hand, the pulling-down time of the chip select signal is utilized to the maximum extent, the safety and the stability of block transmission are improved, and the working performance of the PSRAM software writing controller is effectively improved.
Optionally, the sending, by the DMA controller, the data unit and the instruction address information corresponding to the data unit to the PSRAM based on the block linked list includes: and writing the instruction address information corresponding to the data unit and the data unit into a cache through the DMA, and sending the instruction address information corresponding to the data unit and the data unit to the PSRAM through the cache.
From the perspective of a hardware layer, when the SOC sends data to the PSRAM through the QSPI interface, after the data to be written is processed into blocks by the software layer, the data is written into a buffer memory, for example, a First Input First Output (FIFO), from the memory of the SOC by the DMA controller, and then sent to the external PSRAM through the QSPI interface by the FIFO, and the data in the FIFO is automatically sent according to the sequence. The FIFO buffer is arranged between the software layer and the external device, and can help to control the transmission speed of data. Fig. 12 is a schematic diagram of a fifo buffer according to an embodiment of the present application, where the data width of the buffer is 32 bits.
In this embodiment, by setting the cache between the DMA controller and the PSRAM, the speed of data transmission can be controlled, and a situation that a packet is stuck due to an excessively high speed is avoided, that is, when the block transmission is not completed, the next block to be transmitted enters the cache, so that a chip select signal is not pulled high after the block transmission is completed, thereby causing a circuit abnormality is avoided. The normal transmission of data can be further ensured by controlling the data transmission speed, and the stability of the software writing controller and the reliability of the software writing controller in running under a complex environment are improved.
Optionally, in an embodiment, the method further includes: and controlling a first writing speed not to be larger than the sending speed of the cache, and controlling a second writing speed not to be larger than the sending speed, wherein the first writing speed is the speed of writing the instruction address information corresponding to the data unit into the cache by the DMA controller, the second writing speed is the speed of writing the data unit into the cache by the DMA controller, and the sending speed is the speed of sending the instruction address information corresponding to the data unit and the data unit to the PSRAM by the cache.
It should be understood that the first speed and the second speed may be equal, that is, when the instruction address information corresponding to the data unit and the data unit generate a block, the first speed and the second speed are equal and both less than the sending speed, and the instruction address information corresponding to the data unit and the data unit are sent to the cache in sequence as a whole. When the instruction address information and the data unit corresponding to the data unit respectively generate a first block and a second block, the first speed and the second speed are both smaller than the sending speed, and the instruction address information and the data unit corresponding to the data unit are sent to the cache sequentially at the first speed and the second speed respectively.
Specifically, taking the FIFO shown in fig. 12 as an example, in the cache, the software write controller controls the write speed of the block to be not greater than the sending speed, wherein the write speed can be adjusted according to the data width of the block and the bus width used by the DMA controller.
In this embodiment, by controlling the speed at which the block is written into the cache to be not greater than the sending speed at which the data and/or command address information in the block is sent out of the cache, the filling speed of the block in the cache can be controlled, and the packet sticking phenomenon caused by an excessively fast writing speed can be effectively avoided. For example, when the instruction address information in the first block has not been issued from the FIFO, the second block has been written into the FIFO, which is the sticky packet. After the instruction address information in the first block is sent completely due to packet sticking, the software layer mistakenly considers that the instruction address information is sent incompletely, and the CS signal cannot be normally released, so that the circuit works abnormally. By controlling the writing speed not to be greater than the sending speed, the next block to be sent can be ensured to enter the cache after the data and/or instruction address information in the block is transmitted, the chip selection signal can be ensured to be pulled high after the block is transmitted, the package sticking is effectively avoided, and the performance of the software writing controller is further improved.
In this embodiment, by configuring the first writing speed and the second writing speed to be equal to the sending speed, it is not only ensured that the next block to be sent enters the cache after the block transmission is completed, but also time sequence waste caused by a slow writing speed can be avoided, and the working efficiency of the PSRAM software write controller is further improved.
In one possible implementation, the PSRAM software write controller may be configured with reference to the appropriate data transfer width and write speed as determined in table 1.
TABLE 1
Figure 469365DEST_PATH_IMAGE001
In table 1, MSIZE is the number of beats of data that the DMA controller writes to the FIFO in a single time in Burst mode, and represents the amount of data that the DMA controller writes to the FIFO in a single time.
Optionally, in an embodiment, the method further includes: determining instruction address information corresponding to the data unit and data volume of the data unit sent by the DMA controller; controlling a first writing speed to be not more than a sending speed of the cache, and controlling a second writing speed to be not more than the sending speed, wherein the first writing speed is a speed for the DMA controller to write instruction address information corresponding to the data unit into the cache, the second writing speed is a speed for the DMA controller to write the data unit into the cache, and the sending speed is a speed for the instruction address information corresponding to the data unit and the data unit to be sent to the PSRAM by the cache; and when the data volume sent at the sending speed is equal to a preset data volume, pulling up the chip selection signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
In this embodiment, the normal pull-up of the chip select signal is ensured by simultaneously controlling the filling speed of the block in the cache and the pull-up condition of the chip select signal, so that the working stability of the software write controller in a complex environment can be further improved, and the software write controller can be ensured to operate safely and efficiently in the complex environment.
Optionally, in an embodiment, after the DMA controller sends the instruction address information corresponding to the data unit and the data unit, write-back information sent by the DMA controller is received, where the write-back information is used to indicate that the instruction address information corresponding to the data unit and the data unit are sent completely, the write-back information includes the instruction address information corresponding to the data unit and writing status information and/or location information of the data unit, the status information is used to inform that the writing of the SOC block is completed, and the location information is used to inform a location where the block is written.
Specifically, after the DMA controller sends the block to the PSRAM, and before the DMA controller sends the next block to be sent, the DMA controller executes a write-back operation, and the software layer receives write-back information sent by the DMA controller.
In the embodiment, as the block chain table has almost no time interval between blocks, in the transmission process, besides avoiding packet sticking by controlling the filling speed of the blocks in the cache, write back can be designed, the software layer consumes some software instructions by receiving the write information sent back by the DMA controller, that is, after the DMA controller sends one block, the time of about several nanoseconds is consumed to execute write back operation, the time interval between the blocks can be properly increased, the packet sticking phenomenon is further avoided, the safety and the stability of the software write controller are improved, and the working performance of the software write controller is optimized.
An embodiment of the present application further provides an SOC chip 1300, as shown in fig. 13, including:
the processor 1301 is configured to determine at least one data unit of data to be written into a pseudo static random access memory PSRAM and instruction address information corresponding to the data unit according to a single-frame write data amount of the PSRAM, where the single-frame write data amount is a data amount written in a low-level time of a chip select signal corresponding to the PSRAM; generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list, the block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used for indicating a next block to be sent of the block when the block linked list is transmitted;
the DMA controller 1302 is configured to send the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list.
Optionally, the block further comprises: configuration information for instructing the DMA controller to transfer instructions required for the block.
Optionally, the instruction includes at least one of a transfer direction instruction, a transfer channel instruction, a transfer speed instruction, and a transfer data width instruction for transferring the block by the DMA controller.
In this embodiment, the software writing controller of the software layer divides data to be written into the PSRAM at one time and determines the data into at least one data unit and instruction address information corresponding to the data unit based on the processor 1301 of the hardware layer, the instruction address information corresponding to the data unit and the data unit generate at least one block, and the at least one block orderly forms a block linked list through pointer information. The data is sent to the PSRAM in the form of the block linked list through the DMA controller with the hardware circuit support, so that the time of the software writing controller consuming software instruction to indicate multiple segmentation, configuration and data sending is saved, the access efficiency of the software writing controller to the PSRAM is effectively improved, and the high-speed writing of the PSRAM is realized.
Optionally, the processor 1301 is further configured to: and generating a block according to the instruction address information corresponding to the data unit and the data unit, wherein the block comprises the configuration information, the pointer information, the instruction address information corresponding to the data unit and the data unit.
Optionally, the processor 1301 is further configured to: and generating a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, wherein the first block comprises the configuration information of the first block, the pointer information of the first block and the instruction address information corresponding to the data unit, and the second block comprises the configuration information of the second block, the pointer information of the second block and the data unit.
Optionally, the processor 1301 is further configured to: and determining instruction address information corresponding to the data unit and the data volume of the data unit sent by the DMA controller, and pulling up the chip select signal when the data volume is larger than a preset data volume, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
Optionally, the preset data size is equal to the instruction address information corresponding to the data unit and the data size of the data unit.
Alternatively, in one embodiment, as shown in fig. 14, the SOC chip 1400 includes:
a processor 1401 for performing the functions performed by the processor;
a DMA controller 1402 for executing the functions executed by the above-described DMA controller; the DMA controller is used for writing the instruction address information corresponding to the data unit and the data unit into the cache;
a buffer 1403, configured to send the instruction address information corresponding to the data unit sent by the DMA controller and the data unit to the PSRAM.
Optionally, the processor 1401 is further configured to: and controlling a first writing speed not to be larger than the sending speed of the cache, and controlling a second writing speed not to be larger than the sending speed, wherein the first writing speed is the speed of writing the instruction address information corresponding to the data unit into the cache by the DMA controller, the second writing speed is the speed of writing the data unit into the cache by the DMA controller, and the sending speed is the speed of sending the instruction address information corresponding to the data unit and the data unit to the PSRAM by the cache.
Optionally, the processor 1401 is further configured to: after the DMA controller sends the data unit and the instruction address information corresponding to the data unit, write-back information sent by the DMA controller is received, wherein the write-back information is used for indicating that the instruction address information corresponding to the data unit and the data unit are sent completely, and the write-back information comprises the instruction address information corresponding to the data unit and the state information and/or the position information of the data unit.
The embodiment of the present application further provides a software writing controller, configured to execute the data writing method according to any embodiment of the present application.
Illustratively, the software writing controller 1500, belonging to a software layer, executes software functions based on hardware functions of the SOC chip, as shown in fig. 15, and includes:
the processing module 1501 is configured to determine at least one data unit of data to be written in a pseudo static random access memory PSRAM and instruction address information corresponding to the data unit according to a single-frame write data size of the PSRAM, where the single-frame write data size is a data size written in a low-level time of a chip select signal corresponding to the PSRAM; generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list, the block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used for indicating a next block to be sent of the block when the block linked list is transmitted;
a write module 1502, configured to access the DMA controller through the direct memory, and send the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list.
Optionally, in an embodiment, the block further includes: configuration information for instructing the DMA controller to transfer instructions required for the block.
Optionally, in an embodiment, the instruction includes at least one of a transfer direction instruction, a transfer channel instruction, a transfer speed instruction, and a transfer data width instruction for the DMA controller to transfer the block.
Optionally, in an embodiment, the processing module 1501 is configured to generate a block according to the instruction address information corresponding to the data unit and the data unit, where the block includes the configuration information, the pointer information, the instruction address information corresponding to the data unit, and the data unit.
Optionally, in an embodiment, the processing module 1501 is configured to generate a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, where the first block includes the configuration information of the first block, the pointer information of the first block, and the instruction address information corresponding to the data unit, and the second block includes the configuration information of the second block, the pointer information of the second block, and the data unit.
Optionally, the processing module 1501 is further configured to: and determining instruction address information corresponding to the data unit and the data volume of the data unit sent by the DMA controller, and pulling up the chip select signal when the data volume is equal to a preset data volume, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
Optionally, the preset data size is equal to the instruction address information corresponding to the data unit and the data size of the data unit.
Optionally, in an embodiment, the writing module 1502 is further configured to: and writing the instruction address information corresponding to the data unit and the data unit into a cache through the DMA, and sending the instruction address information corresponding to the data unit and the data unit to the PSRAM through the cache.
Optionally, the processing module 1501 is further configured to: and controlling a first writing speed not to be larger than the sending speed of the cache, and controlling a second writing speed not to be larger than the sending speed, wherein the first writing speed is the speed of writing the instruction address information corresponding to the data unit into the cache by the DMA controller, the second writing speed is the speed of writing the data unit into the cache by the DMA controller, and the sending speed is the speed of sending the instruction address information corresponding to the data unit and the data unit to the PSRAM by the cache.
Optionally, the writing module 1502 is further configured to: determining instruction address information corresponding to the data unit and data volume of the data unit sent by the DMA controller; controlling a first writing speed to be not more than a sending speed of the cache, and controlling a second writing speed to be not more than the sending speed, wherein the first writing speed is a speed for the DMA controller to write instruction address information corresponding to the data unit into the cache, the second writing speed is a speed for the DMA controller to write the data unit into the cache, and the sending speed is a speed for the instruction address information corresponding to the data unit and the data unit to be sent to the PSRAM by the cache; and when the data volume sent at the sending speed is equal to a preset data volume, maintaining the high level state of the chip selection signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
Optionally, the writing module 1502 is further configured to: after the DMA controller sends the data unit and the instruction address information corresponding to the data unit, write-back information sent by the DMA controller is received, wherein the write-back information is used for indicating that the instruction address information corresponding to the data unit and the data unit are sent completely, and the write-back information comprises the instruction address information corresponding to the data unit and the state information and/or the position information of the data unit.
The embodiment of the present application further provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, the computer-executable instructions are used to implement the data writing method according to any possible implementation manner in the embodiment of the present application.
It should be understood that all or part of the steps for implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; the storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
It should be understood that the software layer and the software writing controller described in the embodiments of the present application can be understood as computer-executable instructions in a computer-readable storage medium for executing the data writing method described in the embodiments of the present application.
Illustratively, as shown in fig. 16, a PSRAM write access procedure is performed by using the write method described in this application, and the command address information corresponding to the data unit and the data unit are respectively configured as the first block and the second block, where the first write speed and the second write speed are not greater than the transmission speed, during transmission, when the data amount transmitted at the transmission speed is equal to a preset data amount, the chip select signal is pulled up, and after the command address information corresponding to the data unit and the data unit are transmitted by the DMA controller, write-back information transmitted by the DMA controller is received.
In the case where the serial interface has a maximum operating frequency SCLK of 48 MHz and four-wire mode is used, the data payload is 128 bytes. The access flow is run in the logic controller, the CS signal pull-down time is 6.5 μ s-6.8 μ s, compared with the logic operation result of the ordinary software write controller shown in fig. 5, the time interval between the sequential frame and the sequential frame is about 180 ns, i.e. the time interval between the blocks in the embodiment of the present application is 180 ns, and the time interval is stable and is not affected by the system scheduling, the ratio of the valid time to the invalid time is 6.8 × 1000:180, i.e. 37.8:1, compared with 0.097:1 when the PSRAM write access flow is executed by using for/while logic, the work efficiency of the software write controller is greatly improved.
Illustratively, in the case that the maximum operating frequency SCLK of the serial interface is 48 MHz and the four-wire mode is adopted, the number of bytes of each clock signal is 4, the data payload is 128 bytes, the software write controller accesses the external device supporting the QSPI interface, and the theoretical limit value of the number of bits carried in unit time (Sec ) is: 48 × 4/8 = 24 × 106 Byte = 24*106/(1024 × 1024) = 22.8 MB, i.e., the theoretical speed is 22.8 MB/Sec.
The PSRAM software write controller according to the embodiment of the present application, when the instruction address information occupies 4 bytes and the data payload is 128 bytes, has the maximum access speed V to the payload1= 22.8 = (128/(4+128)) = 22.1 MB/Sec, and the CS signal pull-down time tCEM = (4+128) (48 × 4/8) = 5.5 μ s.
The maximum access speed V to the payload calculated at a typical time-series frame interval of 15 mus under the same conditions using a common software-written controller for/while logic2 = 22.8*((5.5*128/132)/(5.5+15)) = 5.93 MB/Sec。
Under the same conditions, the writing speed of the software write controller provided by the embodiment of the application reaches 4 times that of the common software write controller.
Illustratively, the PSRAM software write controller provided by the embodiments of the present application is subjected to a write speed test and a stability test.
(1) Write speed test
And (3) testing conditions are as follows: SCLK is 48 MHz, four wire mode, and the data payload is 128 bytes or 64 bytes.
The average write access speed test results for the PSRAM software write controller are shown in table 2:
TABLE 2
Figure 897198DEST_PATH_IMAGE002
Wherein, the RAM is a random access memory in the main control chip. As can be seen from table 2, the PSRAM software write controller provided in the embodiment of the present application greatly increases the write speed, and achieves a working efficiency several times that of a common software write controller.
(2) Stability test
And (3) testing conditions are as follows: the data payload is 128 bytes or 64 bytes, and the number of writes and reads back is 100000 times per turn.
The PSRAM software write controller stability test results are shown in table 3:
TABLE 3
Figure 711570DEST_PATH_IMAGE003
Comparing whether the write value and the read-back value of the PSRAM software write controller provided by the embodiment of the application are equal or not, and testing the stability of the PSRAM software write controller to find that the PSRAM software write controller has excellent stability.
To sum up, the application provides a method for data write-in, which is applied to an SOC/MCU chip externally connected with a PSRAM, can effectively improve the write-in speed of a software write-in controller accessing the PSRAM, realizes high-speed write-in to the PSRAM, can stably and circularly work in a complex environment, and enables the software write-in controller to reach the performance of an IP controller through software layer design and combination of an existing hardware circuit in the SOC/MCU chip without additionally arranging an IP write-in controller in the SOC/MCU chip.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (23)

1. A method of data writing, comprising:
determining at least one data unit of data to be written into a Pseudo Static Random Access Memory (PSRAM) and instruction address information corresponding to the data unit according to a single-frame written data volume of the PSRAM, wherein the single-frame written data volume is the data volume written in the low-level time of a chip selection signal corresponding to the PSRAM;
generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list, the block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used for indicating a next block to be sent of the block when the block linked list is transmitted;
and sending the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list through a DMA controller.
2. The method of claim 1, wherein the block further comprises: configuration information for instructing the DMA controller to transfer instructions required for the block.
3. The method of claim 2, wherein the command comprises at least one of a transfer direction command, a transfer channel command, a transfer speed command, and a transfer data width command for the DMA controller to transfer the block.
4. The method of claim 2, wherein the generating at least one block according to the instruction address information corresponding to the data unit and the data unit comprises:
and generating a block according to the instruction address information corresponding to the data unit and the data unit, wherein the block comprises the configuration information, the pointer information, the instruction address information corresponding to the data unit and the data unit.
5. The method of claim 2, wherein the generating at least one block according to the instruction address information corresponding to the data unit and the data unit comprises:
and generating a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, wherein the first block comprises the configuration information of the first block, the pointer information of the first block and the instruction address information corresponding to the data unit, and the second block comprises the configuration information of the second block, the pointer information of the second block and the data unit.
6. The method according to any one of claims 1 to 5, further comprising:
determining instruction address information corresponding to the data unit and the data volume of the data unit sent by the DMA controller,
and when the data volume is equal to a preset data volume, pulling up the chip select signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
7. The method of claim 6, wherein the predetermined amount of data is equal to the amount of data of the data unit and instruction address information corresponding to the data unit.
8. The method of any of claims 1-5, wherein sending, by the DMA controller, the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list comprises:
and writing the instruction address information corresponding to the data unit and the data unit into a cache through the DMA controller, and sending the instruction address information corresponding to the data unit and the data unit to the PSRAM through the cache.
9. The method of claim 8, further comprising:
and controlling a first writing speed not to be larger than the sending speed of the cache, and controlling a second writing speed not to be larger than the sending speed, wherein the first writing speed is the speed of writing the instruction address information corresponding to the data unit into the cache by the DMA controller, the second writing speed is the speed of writing the data unit into the cache by the DMA controller, and the sending speed is the speed of sending the instruction address information corresponding to the data unit and the data unit to the PSRAM by the cache.
10. The method according to any one of claims 1 to 5, further comprising:
determining instruction address information corresponding to the data unit and data volume of the data unit sent by the DMA controller;
controlling a first writing speed to be not more than a sending speed of the cache, and controlling a second writing speed to be not more than the sending speed, wherein the first writing speed is a speed for the DMA controller to write instruction address information corresponding to the data unit into the cache, the second writing speed is a speed for the DMA controller to write the data unit into the cache, and the sending speed is a speed for the instruction address information corresponding to the data unit and the data unit to be sent to the PSRAM by the cache;
and when the data volume sent at the sending speed is equal to a preset data volume, pulling up the chip selection signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
11. The method according to any one of claims 1 to 5, further comprising:
after the DMA controller sends the instruction address information corresponding to the data unit and the data unit, write-back information sent by the DMA controller is received, wherein the write-back information is used for indicating that the instruction address information corresponding to the data unit and the data unit are sent completely, and the write-back information comprises the instruction address information corresponding to the data unit and the state information and/or the position information of the data unit.
12. A system-on-chip SOC chip, comprising:
the processor is used for determining at least one data unit of data to be written into the PSRAM and instruction address information corresponding to the data unit according to a single-frame written data volume of the PSRAM, wherein the single-frame written data volume is the data volume written in the low-level time of a chip selection signal corresponding to the PSRAM; generating at least one block according to the instruction address information corresponding to the data unit and the data unit, wherein the at least one block forms a block linked list, the block comprises pointer information, the instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used for indicating a next block to be sent of the block when the block linked list is transmitted;
and the DMA controller is used for sending the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block linked list.
13. The chip of claim 12, wherein the block further comprises: configuration information for instructing the DMA controller to transfer instructions required for the block.
14. The chip of claim 13, wherein the command comprises at least one of a transfer direction command, a transfer channel command, a transfer speed command, and a transfer data width command for the DMA controller to transfer the block.
15. The chip of claim 13, wherein the processor is configured to:
and generating a block according to the instruction address information corresponding to the data unit and the data unit, wherein the block comprises the configuration information, the pointer information, the instruction address information corresponding to the data unit and the data unit.
16. The chip of claim 13, wherein the processor is configured to:
and generating a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, wherein the first block comprises the configuration information of the first block, the pointer information of the first block and the instruction address information corresponding to the data unit, and the second block comprises the configuration information of the second block, the pointer information of the second block and the data unit.
17. The chip of any one of claims 12 to 16, wherein the processor is further configured to:
determining instruction address information corresponding to the data unit and the data volume of the data unit sent by the DMA controller,
and when the data volume is equal to a preset data volume, pulling up the chip select signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
18. The chip of claim 17, wherein the predetermined data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
19. The chip according to any one of claims 12 to 16, wherein the chip further comprises:
caching;
the DMA controller is used for writing the instruction address information corresponding to the data unit and the data unit into the cache, and the cache is used for sending the instruction address information corresponding to the data unit and the data unit written by the DMA controller to the PSRAM.
20. The chip of claim 19, wherein the processor is further configured to:
and controlling a first writing speed not to be larger than the sending speed of the cache, and controlling a second writing speed not to be larger than the sending speed, wherein the first writing speed is the speed of writing the instruction address information corresponding to the data unit into the cache by the DMA controller, the second writing speed is the speed of writing the data unit into the cache by the DMA controller, and the sending speed is the speed of sending the instruction address information corresponding to the data unit and the data unit to the PSRAM by the cache.
21. The chip according to any one of claims 12 to 16, wherein the chip further comprises:
caching;
the processor is further configured to:
determining instruction address information corresponding to the data unit and data volume of the data unit sent by the DMA controller;
controlling a first writing speed to be not more than a sending speed of the cache, and controlling a second writing speed to be not more than the sending speed, wherein the first writing speed is a speed for the DMA controller to write instruction address information corresponding to the data unit into the cache, the second writing speed is a speed for the DMA controller to write the data unit into the cache, and the sending speed is a speed for the instruction address information corresponding to the data unit and the data unit to be sent to the PSRAM by the cache;
and when the data volume sent at the sending speed is equal to a preset data volume, pulling up the chip selection signal, wherein the preset data volume is a threshold value determined according to the instruction address information corresponding to the data unit and the data unit.
22. The chip of any one of claims 12 to 16, wherein the processor is further configured to:
after the DMA controller sends the instruction address information corresponding to the data unit and the data unit, write-back information sent by the DMA controller is received, wherein the write-back information is used for indicating that the instruction address information corresponding to the data unit and the data unit are sent completely, and the write-back information comprises the instruction address information corresponding to the data unit and the state information and/or the position information of the data unit.
23. A computer-readable storage medium having stored thereon computer-executable instructions for implementing the method of data writing of any one of claims 1 to 11 when executed by a processor.
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