JP2006164119A - Data processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve performance by reducing access latency at the time of accessing a peripheral module, such as data readout, being connected to a low-speed bus, from a CPU, etc. connected to a high-speed bus. <P>SOLUTION: A data processing unit includes a CPU bus 40 for connecting a CPU 41 and a RAM 42, a peripheral bus 50 for connecting one or more peripheral modules 51, a bus bridge controller 1 connected to the respective buses for signal synchronization processing between the buses, a clock generator 30 for supplying a clock signal to each module, a set section 20 for setting a value indicating timing determined by the signal on the peripheral bus 50 and supplying the set value to the bus bridge controller 1 as a timing signal. When accessing the peripheral module 51 from the CPU 41, the bus bridge controller 1 retains data of the peripheral bus 50 at the timing according to the above timing signal, and transfers the retained data to the CPU bus 40. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data processing apparatus such as a microcomputer, and more particularly to a data processing apparatus that performs a signal synchronization process between buses in a configuration in which buses of different frequencies are connected.

  In general, computer systems often have a hierarchical bus structure. For example, a low-speed second bus (also referred to as a peripheral bus) to which peripheral modules are connected is connected to a high-speed first bus (also referred to as a CPU bus) to which modules such as a CPU and a memory are connected. is there. Since the bus is more susceptible to electrical loads such as wiring capacitance and parasitic capacitance as the frequency increases, the number of modules connected to the high-speed CPU bus is limited. For this reason, the peripheral modules that do not require much speed are connected to a peripheral bus that is slower than the CPU bus, thereby avoiding the influence. Moreover, power consumption can be suppressed by lowering the frequency of the peripheral bus.

For example, the technique described in Patent Document 1 is intended to realize data transfer between buses having different frequencies without using an asynchronous circuit. In addition, the transfer from the low frequency bus to the high frequency bus is not specified.
JP-A-6-342415

  The computer system having the hierarchical bus structure has the advantages of the hierarchical bus structure, but also has a problem caused by the hierarchical bus structure. In transferring signals between buses of different frequencies, synchronization processing is required when transferring bus interface signals such as data and control signals. In a bus bridge control unit that performs signal synchronization processing (also referred to as bridge processing) between buses, the access latency when data is transferred from the low speed side to the high speed side bus becomes long, and the high speed side bus is in the meantime. Will be stalled. As a result, the performance of the high-speed bus is degraded.

  Conventionally, since the frequency difference between the CPU bus and the peripheral bus was not so large, the performance degradation due to the synchronization processing was not so problematic. However, recently, the frequency of the CPU bus has been remarkably improved, whereas the frequency of the peripheral bus cannot be increased compared to the CPU bus. This is because a module designed in the past for short-term development of a connected module is often used, or for realizing the low power consumption. Due to the increasing tendency of the speed difference between the CPU bus and the peripheral bus, the problem of performance degradation due to the synchronization processing cannot be ignored.

  The present invention has been made in view of the problems as described above, and its purpose is to provide a data processing apparatus having a bus bridge control unit that is connected to buses of different frequencies and performs synchronization processing of signals between the buses. An object of the present invention is to provide a technique capable of shortening access latency and improving performance when a module such as a CPU on a high-speed side bus accesses a peripheral module or the like on a low-speed side bus for reading data.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. In order to achieve the above object, a data processing apparatus according to the present invention comprises the following technical means.

  The data processing device according to the present invention has a configuration in which a signal of a low-speed bus is determined in a signal synchronization process between buses in a configuration in which buses having different operating frequencies are connected via a bus bridge control unit that performs a bridge process. A peripheral bus signal determination timing setting unit (abbreviated as a setting unit), which is a circuit part for supplying a signal indicating the above to the bus bridge control unit.

  The data processing apparatus includes, for example, a first bus (CPU bus) on a high speed side to which a processor and a module such as a memory used by the processor are connected, and a second low speed side to which one or more peripheral modules are connected. A bus bridge (peripheral bus), a bus bridge controller connected to the first and second buses for synchronizing signals between the buses, and supplying a clock signal to each module including the bus bridge controller And a value (timing value) indicating the timing at which the signal of the second bus is determined is set, and the set value is supplied to the bus bridge control unit as a timing signal for use in the synchronization processing And a setting unit.

  When the processor accesses the peripheral module, the bus bridge control unit synchronizes the signal between the first and second buses, and the signal of the second bus is synchronized with the timing signal. Is held (captured). The signals on the second bus are in particular data and control signals.

  In particular, when the processor on the first bus accesses data reading to the peripheral module on the second bus, the bus bridge control unit is read from the peripheral module on the second bus. Data is held at a timing according to the timing signal and output to the first bus.

  As a term in the present specification, the “signal” of the second bus includes “data” and “control signal”. “Data” is, for example, read data from a peripheral module. The “control signal” is various control signals other than “data”, and excludes “command” and “address”.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to the present invention, the low-speed bus signal can be held at the optimum timing according to the system configuration in the synchronization processing, and the high-speed bus CPU or the like reads data from the peripheral modules of the low-speed bus. For example, the access latency in the case of performing access for the purpose can be shortened and the performance can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  In the data processing device of each embodiment of the present invention, when the CPU on the CPU bus accesses the peripheral module on the peripheral bus via the bridge processing of the bus bridge control unit, the bus bridge control unit A signal synchronization process between the buses is performed at a timing according to the supplied timing signal. In particular, when the CPU on the CPU bus performs access to read data to the peripheral modules on the peripheral bus, the bus bridge control unit transfers the read data from the peripheral modules on the peripheral bus to the CPU bus side. Data on the peripheral bus is held at a timing according to the timing signal and output to the CPU bus side.

<Prerequisite technology>
FIG. 15 shows a configuration example of a known general data processing apparatus that performs data transfer between buses having different frequencies as a prior art which is a premise of the present invention. First, a data processing apparatus as the prerequisite technology will be described. This data processing apparatus includes a CPU bus 40, a CPU 41, a RAM 42, a peripheral bus 50, a first peripheral module (peripheral module # 1) 51-1 to an Nth peripheral module (peripheral module #N) 51-N, a bus bridge. A control unit 101 and a clock generation unit 30 are included. The CPU bus 40 is a bus that operates at a higher frequency than the peripheral bus 50. In the CPU bus 40 and the peripheral bus 50, a command bus (for example, 4 bits), an address bus (for example, 32 bits), a data bus, and the like are collectively shown as one line.

  A CPU 41 as a processor, a RAM 42 as a main memory and a cache memory used by the CPU 41, and a bus bridge control unit 101 are connected to the CPU bus 40. N (one or more) peripheral modules 51 {51-1, 51-2,..., 51-N} from 1st to Nth and the bus bridge control unit 101 are connected to the peripheral bus 50. The The clock generation unit 30 supplies a clock signal to each module including the bus bridge control unit 101. The peripheral module 51 is a module such as a DMA (direct memory access) controller or a timer.

  The bus bridge control unit 101 performs signal synchronization processing (bridge processing) between the CPU bus 40 and the peripheral bus 50, and replaces the CPU 41 when the CPU 41 accesses the peripheral module 51. Access to the peripheral module 51 is performed.

  Next, FIG. 16 shows an internal configuration example of the conventional bus bridge control unit 101. This configuration example of the bus bridge control unit 101 shows a configuration of a read control unit particularly when the CPU 41 accesses data read to the peripheral module 51, and includes a register 11, an AND circuit unit 14, The peripheral bus command issuance control unit 15, the peripheral bus address issuance control unit 112, and signal lines for inputting / outputting signals between the CPU bus 40 and the peripheral bus 50 are configured.

  The peripheral bus command issuance control unit 15 inputs a CPU bus command 43 from the CPU bus 40, outputs a peripheral bus command 152 to the peripheral bus 50, and outputs a peripheral bus data output period signal (output) to the AND circuit unit 14. 151 (abbreviated as a period signal). The output period signal 151 is a signal indicating the output period of the peripheral bus data 54.

  The CPU bus command 43 is a command such as a read command from the CPU 41 that is input from the CPU bus 40 to the bus bridge control unit 101. The peripheral bus command 152 is a command for reading from the peripheral module 51 and the like output from the bus bridge control unit 101 to the peripheral bus 50. The peripheral bus data 54 is data such as read data from the peripheral module 51 input from the peripheral bus 50 to the bus bridge control unit 101. The CPU bus data 111 is data such as read data from the peripheral module 51 to the CPU 41 output from the bus bridge control unit 101 to the CPU bus 40.

  The peripheral bus address issuance control unit 112 receives the CPU bus address 44 from the CPU bus 40 and outputs the peripheral bus address 1121 to the peripheral bus 50. The CPU bus address 44 is an address such as a data read address for the peripheral module 51 from the CPU 41 that is input from the CPU bus 40 to the bus bridge control unit 101. The peripheral bus address 1121 is an address for reading data from the peripheral module 51 and the like output from the bus bridge control unit 101 to the peripheral bus 50.

  The AND circuit unit 14 receives the clock synchronization signal 32 from the clock generation unit 30, receives the output period signal 151 from the peripheral bus command issue control unit 15, performs a logical product, and outputs peripheral bus data to the register 11. A holding enable signal (abbreviated as an enable signal) 141 is output. The enable signal 141 is a signal for enabling the holding of the peripheral bus data 54 in the register 11.

  The register 11 receives the peripheral bus data 54 from the peripheral bus 50, the CPU bus clock 31 from the clock generation unit 30, and the peripheral bus data 54 when the enable signal 141 input from the AND circuit unit 14 is enabled. The data is held and output to the CPU bus 40 as CPU bus data 111.

  The CPU bus clock 31 is an operation clock in the CPU bus 40. A peripheral bus clock (33) not shown is an operation clock in the peripheral bus 50. The clock synchronization signal 32 is a signal for synchronizing the CPU bus clock 31 and the peripheral bus clock (33).

  FIG. 17 is a time chart showing an example of the operation of the data processing apparatus shown in FIGS. 15 and 16. t0 to t16 indicate units of time corresponding to the cycle of the CPU bus clock 31. In this example, the case where the clock ratio between the CPU bus clock 31 and the peripheral bus clock 33 is 8: 1 is shown. The clock synchronization signal 32 is asserted at timings t7 and t15 corresponding to the rising timing of the peripheral bus clock 33.

  In this example, a peripheral bus command 152 for reading (indicated by “R” in FIG. 17) issued by the peripheral bus command issuance control unit 15 based on the input of the CPU bus command 43 from the CPU bus 40, and the peripheral bus address In this example, the peripheral bus address for reading 1121 (indicated by “A”) issued by the issue control unit 112 is output during the period from t0 to t7. The CPU bus command 43 and the CPU bus address 44 from the CPU 41 are not shown, but are input to the bus bridge control unit 101 before t0. The peripheral bus data 54 (indicated by “D”) corresponding to the peripheral bus command 152 is output during the period from t8 to t15. In this case, the output period signal 151 output from the peripheral bus command issuance control unit 15 is also output during the same period from t8 to t15.

  The AND circuit unit 14 takes an AND logic of the output period signal 151 and the clock synchronization signal 32 and asserts the enable signal 141 at the timing t15 as shown in FIG. The register 11 holds the peripheral bus data 54 at the timing t15 when the enable signal 141 is asserted, and outputs it as CPU bus data 111 (indicated by “D”) at the next timing t16.

  In such a data processing device, in the synchronization processing of the bus bridge control unit 101, the data content of the peripheral bus 50 is determined before the clock synchronization signal 32 is asserted. However, even when the peripheral bus data 54 is determined at a timing much earlier than the clock synchronization signal 32, the peripheral bus data 54 is held using the clock synchronization signal 32. That is, in the case of this example, the peripheral bus data 54 is held with a delay of the period from t8 to t14 from the start of output of the peripheral bus data 54 at t8. Therefore, the transfer of the CPU bus data 111 to the CPU bus 40 is delayed by that time. The CPU bus 40 is stalled until the transfer of the peripheral bus data 54 is completed, and as a result, the performance of the CPU 41 is lowered. The stalled state means that a waiting time occurs after the data content of the peripheral bus 50 is determined and taken in and output to the CPU bus 40.

(Embodiment 1)
FIG. 1 shows a configuration of a data processing apparatus 10 according to the first embodiment of the present invention. The data processing apparatus 10 includes a CPU bus 40, a CPU 41, a RAM 42, a peripheral bus 50, a first peripheral module (peripheral module # 1) 51-1 to an Nth peripheral module (peripheral module #N) 51. -N, bus bridge control unit 1, clock generation unit 30, and peripheral bus signal determination timing setting unit (setting unit) 20. Each unit other than the bus bridge control unit 1 and the setting unit 20 has the same configuration as that of the base technology. Although the setting unit 20 is shown as a configuration provided outside the bus bridge control unit 1, a configuration provided inside the bus bridge control unit 1 is also possible.

  The CPU 41, the RAM 42, and the bus bridge control unit 1 are connected to the CPU bus 40. The first to Nth (one or more) N (one or more) peripheral modules 51 {51-1, 51-2,..., 51-N} and the bus bridge control unit 1 are connected to the peripheral bus 50. The bus bridge control unit 1 connects the CPU bus 40 and the peripheral bus 50, and is also connected to the setting unit 20 and the clock generation unit 30. The clock generation unit 30 is connected to the bus bridge control unit 1, the CPU 41, the RAM 42, and each peripheral module 51, and supplies a clock signal to each.

  The setting unit 20 supplies a signal of a peripheral bus signal determination timing value (timing value) 21 set for the setting unit 20 to the bus bridge control unit 1 as a timing signal. The timing value 21 is a value indicating the timing at which the data and control signals of the peripheral bus 50 are determined in the synchronization process, and indicates the timing at which the bus bridge control unit 1 holds the signal of the peripheral bus 50.

  In the data processing apparatus 10, when the CPU 41 on the CPU bus 40 accesses the peripheral module 51 on the peripheral bus 50, the bus bridge control unit 1 takes in the command output by the CPU 41 to the CPU bus 40, The peripheral module 51 is accessed via the peripheral bus 50. The bus bridge control unit 1 performs processing on the peripheral bus 50 at a timing according to the timing signal supplied from the setting unit 20 in the signal synchronization processing between the buses in the access from the CPU 41 to the peripheral module 51 on the peripheral bus 50 side. Are held (taken in) inside and output to the CPU bus 40 side. In particular, the bus bridge control unit 1 reads data read from the peripheral module 51 in accordance with the read command output on the peripheral bus 50 when accessing the peripheral module 51 for data reading by the read command from the CPU 41. The data is held at the timing according to the timing signal and transferred to the CPU bus 40 side.

  The setting unit 20 includes a timing setting register 25 that is a nonvolatile memory in which the timing value 21 is set and held. This configuration particularly corresponds to a configuration in which the setting unit 20 is set from the outside. The setting value of the timing value 21 is read from and written to the timing setting register 25 from a module such as the CPU 41 provided outside the setting unit 20. For example, the CPU 41 writes the set value of the timing value 21 to the timing setting register 25 via the CPU bus 40 or the control signal line.

  The timing value 21 is determined by the system configuration of the data processing apparatus 10, that is, the operating frequency of the CPU bus 40 and the peripheral bus 50, the configuration of the peripheral module 51, and the like. For example, when the timing value 21 is changed as the system configuration is changed, the data processing apparatus 10 writes the newly determined timing value 21 from the CPU 41 to the timing setting register 25 and updates the setting.

  2A to 2E show a configuration example of the setting unit 20 and setting examples of the timing value 21 stored in the setting unit 20 in each embodiment. (A) corresponds to Embodiment 1, (b) corresponds to Embodiment 2, (c) corresponds to Embodiment 3, (d) corresponds to Embodiment 4, and (e) corresponds to Embodiment 7. .

  FIG. 2A shows an example of the timing value 21 stored in the timing setting register 25 built in the setting unit 20 in the first embodiment. In the first embodiment, the shortest timing at which the signal of the peripheral bus 50 is determined is expressed by the number of clock cycles of the CPU bus 40. In this example, the setting value is “2”, which is the clock of the CPU bus 40 when the shortest timing at which the data and control signals in the peripheral bus 50 are determined starts from the start of signal output of the peripheral bus 50. It represents the third clock in the number of cycles. The set value is “2” obtained by subtracting “1” from the clock cycle number “3” for comparison with the counter value of a counter (counter unit 12 described later) in the bus bridge control unit 1. Is set. As a matter of course, this set value may be a value indicating the timing at which the signal of the peripheral bus 50 is fixed, so a value other than the shortest fixed timing, that is, a value at a later timing may be set. . In the case of this example, the set value shown in FIG. 2A may be “2” or more. The range of the set value is determined by the maximum count value of the counter (counter unit 12) in the bus bridge control unit 1. For example, in the case of a 3-bit counter that can count from “0” to “7”, the settable value is in the range from “0” to “7”.

  FIG. 3 is a diagram showing an example of the configuration of the bus bridge control unit 1 shown in FIG. In this example, the read control unit in the bus bridge control unit 1 is shown. The bus bridge control unit 1 includes a register 11, a counter unit 12, a coincidence detection unit 13, an AND circuit unit 14, a peripheral bus command issuance control unit 15, a peripheral bus address issuance control unit 112, and signals for input / output of each signal Consists of lines and the like.

  The register 11 is a peripheral bus input from the peripheral bus 50 based on the CPU bus clock 31 supplied from the clock generation unit 30 and the peripheral bus data holding enable signal (enable signal) 141 from the AND circuit unit 14. The data 54 is held and output to the CPU bus 40 as CPU bus data 111.

  The counter unit 12 receives the CPU bus clock 31 and the clock synchronization signal 32 supplied from the clock generation unit 30, and counts up when the clock synchronization signal 32 is “Lo”, and clears the counter when the clock synchronization signal 32 is “Hi”. The counter value 121 is output.

  The coincidence detection unit 13 compares the counter value 121 input from the counter unit 12 with the timing value 21 supplied from the setting unit 20, and outputs the result as a coincidence detection value 131.

  The AND circuit unit 14 takes an AND logic of the coincidence detection value 131 input from the coincidence detection unit 13 and the peripheral bus data output period signal (output period signal) 151 input from the peripheral bus command issue control unit 15. The result is output as an enable signal 141.

  The peripheral bus command issuance control unit 15 sends the AND circuit unit 14 to the AND circuit unit 14 based on a CPU bus command 43 input from the CPU bus 40 and a peripheral bus valid data output period signal (not shown) input from the peripheral bus 50. The output period signal 151 is output to the peripheral bus 50 and the peripheral bus command 152 is output.

  The peripheral bus address issue control unit 112 outputs the peripheral bus address 1121 to the peripheral bus 50 based on the CPU bus address 44 in the CPU bus 40.

  In this configuration, when a read command for the peripheral module 51 is issued as a CPU bus command 43 from the CPU 41 to the CPU bus 40, a command for reading data to the peripheral bus 50 through the processing of the bus bridge controller 1. Is output as the peripheral bus command 152. Data read from the peripheral module 51 in accordance with the peripheral bus command 152 is input to the bus bridge controller 1 as peripheral bus data 54. The peripheral bus data 54 is held by the synchronization processing in the bus bridge control unit 1 in accordance with the timing signal from the setting unit 20 and is output as the CPU bus data 111 to the CPU bus 40. The CPU 41 acquires the CPU bus data 111 as read data.

  FIG. 4 shows an example of the counter unit 12 shown in FIG. The configuration of the counter unit 12 is an example corresponding to the case where the frequency ratio between the CPU bus 40 and the peripheral bus 50, that is, the clock ratio between the CPU bus clock 31 and the peripheral bus clock (33) (not shown) is 8: 1. Yes, it is a 3-bit counter that can count from "0" to "7". The counter unit 12 performs counting at the cycle of the CPU bus clock 31 and counts up if the clock synchronization signal 32 (indicated by “S” in FIG. 4) is “Lo” (= 0), and “Hi” (= If 1), clear the counter. The maximum count number of this counter is determined according to the clock ratio used in the data processing apparatus 10. For example, when the clock ratio is used up to 16: 1, it is possible to deal with all the timings by making the configuration of the counter unit 12 a 4-bit counter capable of counting from “0” to “15”.

  FIG. 5 shows an example of a time chart for explaining the operation of the bus bridge controller 1 shown in FIGS. t0 to t16 indicate units of time corresponding to the cycle of the CPU bus clock 31. In this example, the clock ratio between the CPU bus clock 31 and the peripheral bus clock 33 is 8: 1. The clock synchronization signal 32 is asserted at t7 and t15 corresponding to the rising timing of the peripheral bus clock 33. Note that the CPU bus command 43, the CPU bus address 44, and the like are the same as in the base technology and are not shown.

  In this example, the peripheral bus data 54 is determined in the third cycle of the CPU bus clock 31 as the determination timing of the signal of the peripheral bus 50 in the synchronization processing in the bus bridge control unit 1. That is, the peripheral bus data 54 output from a peripheral module 51 on the peripheral bus 50 is an indeterminate value whose data content is not guaranteed in the first and second cycles from t8 when output is started. After the cycle, the content is guaranteed. In this case, the timing after the third cycle can be selected and set as the timing value 21. In this example, the third cycle that is the shortest final timing is set as the timing value 21. In this case, the timing value 21 set by the setting unit 20, that is, the value of the timing signal supplied to the bus bridge control unit 1 is “2”. The counter unit 12 is the 3-bit counter described with reference to FIG. 4, and the counter value 121 is repeatedly counted from “0” to “7” corresponding to the cycle of the CPU bus clock 31.

  In the case of this example, the coincidence detection value 131 detected by the coincidence detection unit 13 is asserted at the timings t2 and t10 when the timing value 21 and the counter value 121 coincide. Here, a peripheral bus command 152 for reading (indicated by “R” in FIG. 5) issued by the peripheral bus command issuance control unit 15 in response to the input of the CPU bus command 43 from the CPU bus 40, and the CPU bus address 44. The peripheral bus address 1121 issued by the peripheral bus address issuance control unit 112 is input during the period from t0 to t7, and the peripheral bus data 54 corresponding to the peripheral bus command 152 for reading is output from the peripheral bus 50. The case where it is output from the peripheral module 51 in the period from t8 to t15 is shown. In this case, the output period signal 151 issued from the peripheral bus command issue control unit 15 is also output during the same period from t8 to t15.

  Subsequently, the AND circuit unit 14 performs an AND logic between the peripheral bus data output period signal 151 and the coincidence detection value 131, and asserts the enable signal 141 at a timing t10. The timing of t10 is the third cycle of the CPU bus clock 31, which is the timing for determining the signal of the peripheral bus 50. The register 11 holds the peripheral bus data 54 at the timing t10 when the enable signal 141 is asserted, and outputs it to the CPU bus 40 as the CPU bus data 111 (indicated by “D” in FIG. 5) at the next timing t11. To do.

  As described above, in the synchronization processing of the bus bridge control unit 1, the peripheral bus data 54 is held in the register 11 and transferred to the CPU bus 40 as the CPU bus data 111 at a timing according to the timing signal from the setting unit 20. . Compared to the configuration shown in FIG. 17, the timing of holding and transferring the peripheral bus data 54 from the peripheral bus 50 to the CPU bus 40 is shortened from t16 to t11, and the peripheral module 51 from the CPU 41 is correspondingly reduced. The efficiency of access to is improved.

  In this example, the synchronization process in the data read access to the peripheral module 51 is shown. However, the present invention is not limited to this, and the control signal input from the peripheral bus 50 to the bus bridge control unit 1 is not limited to this. As in the case of the peripheral bus data 54, the processing can be performed at the determined timing. The control signal input to the bus bridge control unit 1 is, for example, a signal that indicates that data can be written. In this example, a structure in which two buses are connected is described, but the same processing can be performed in a structure in which three or more buses are connected.

(Embodiment 2)
Next, the data processing apparatus 10 of Embodiment 2 is demonstrated. In the second embodiment, the peripheral bus signal which is the shortest time in which the data of the peripheral bus 50 is determined as the set value of the timing value 21 stored in the timing setting register 25 incorporated in the setting unit 20 shown in FIG. This is a form in which a fixed shortest time (abbreviated as the shortest time) 22 is set.

  FIG. 2B shows an example of a configuration in which the shortest time 22 is set as the timing value 21 in the setting unit 20. The shortest time 22 indicates the shortest time in which signals of all peripheral modules 51 among one or more peripheral modules 51 connected to the peripheral bus 50 are determined. That is, the shortest time 22 is determined by the peripheral module 51 having the latest signal determination timing. In this example, the setting value of the shortest time 22 is 15 ns. The setting unit 20 supplies the set value to the bus bridge control unit 1 as a timing signal. As in the first embodiment, a value larger than the shortest time may be set.

  FIG. 6 shows a configuration example of the bus bridge control unit 1 in a configuration in which the shortest time 22 shown in FIG. The contents and operation of this configuration are basically the same as those shown in FIG. The difference is that the timing value 21 in the setting unit 20 is the shortest time 22 and a peripheral bus signal determination timing calculation unit (referred to as a timing calculation unit) 16 is added inside the bus bridge control unit 1.

  Based on the shortest time 22 set and supplied to the setting unit 20, the timing calculation unit 16 determines the shortest timing at which the peripheral bus data 54 is determined according to the frequency of the CPU bus 40 and the number of clock cycles of the CPU bus 40. Is a circuit that outputs to the coincidence detector 13 as a peripheral bus signal determination timing calculation value (referred to as a timing calculation value) 161. The coincidence detection unit 13 receives the counter value 121 and the timing calculation value 161 and detects coincidence. The timing calculation unit 16 may be provided on the setting unit 20 side.

  FIG. 7 shows a configuration example of the timing calculation unit 16 shown in FIG. In this example, the timing calculation unit 16 has three types of frequencies of the CPU bus 40 that can be handled: 200 MHz, 100 MHz, and 50 MHz, and the shortest time 22 is set to 5 ns, 10 ns, and 15 ns for each frequency. The timing calculation value 161 corresponding to the case can be calculated. The timing calculation value 161 is represented by the number of cycles of the CPU bus clock 31. For example, the timing calculation unit 16 may have a configuration in which these timing calculation values 161 are set in advance, or may be a circuit that calculates the timing calculation value 161 by a simple calculation formula.

  In this example, when the frequency of the CPU bus 40 is 200 MHz and the shortest time 22 is 5 ns in the data transfer process at that time, the timing calculation value 161 is calculated as “0”. That is, the signal of the peripheral bus 50 is determined in the first cycle of the CPU bus clock 31. Similarly, the timing calculation value 161 is “1” when the shortest time 22 is 10 ns, and “2” when the shortest time 22 is 15 ns. The timing calculation value 161 is “0” when the frequency of the CPU bus 40 is 100 MHz and the shortest time 22 at that time is 5 ns and 10 ns, and “1” when the frequency is 15 ns. In addition, when the frequency of the CPU bus 50 is 50 MHz and the shortest time is 5 ns, 10 ns, and 15 ns, the timing calculation value 161 is “0”. In the case of using other than the combination of values shown in this example, it can be dealt with by preparing a necessary combination in the timing calculation unit 16 in advance. As described above, in the second embodiment, optimum data transfer processing can be performed according to the frequency of the CPU bus 40 and the shortest time 22.

(Embodiment 3)
Next, the data processing apparatus 10 of Embodiment 3 is demonstrated. In the third embodiment, the peripheral bus signal determination timing for each peripheral module 51 in the plurality of peripheral modules 51 is set as the setting value of the timing value 21 stored in the timing setting register 25 built in the setting unit 20 shown in FIG. This is a form in which values are set.

  FIG. 2C shows an example of a configuration in which the timing value 21 for each peripheral module 51 is set as the timing value 21 in the setting unit 20. The corresponding timing value 21 is set in the form of the number of cycles of the CPU clock 31 as in the first embodiment for the peripheral module name which is the peripheral module identification information. In particular, the timing value 21 may be different for each peripheral module 51. A plurality of timing values 21 corresponding to each peripheral module 51 are supplied from the setting unit 20 to the bus bridge control unit 1. In this example, in the timing setting register 25, the setting of the timing value 21 in the first peripheral module 51-1 is “2”, the setting value in the second peripheral module 51-2 is “1”, and the Nth peripheral module. The set value in 51-N is set as “0”.

  FIG. 8 shows a configuration example of the bus bridge controller 1 in the configuration in which the timing value 21 is set for each peripheral module 51 as shown in FIG. The contents and operation of the configuration are basically the same as those shown in FIG. 3 (Embodiment 1). The difference is that the timing value 21 supplied from the setting unit 20 is prepared as timing values # 1 to #N {21-1,..., 21-N} for each of N peripheral modules 51. The timing selection circuit unit 17 is added to the bus bridge control unit 1. The timing selection circuit unit 17 selects the maximum value, that is, the one having the latest signal determination timing of the peripheral bus 50 from among the plurality of timing values # 1 to #N, and supplies the timing selection value 171 to the coincidence detection unit 13. Output. The coincidence detection unit 13 detects coincidence between the counter value 121 and the timing selection value 171.

  Thereby, in the third embodiment, in the access to the peripheral module 51 via the bus bridge control unit 1, the data transfer process is performed at a timing according to the peripheral module 51 in which the peripheral bus data 54 is determined at the latest timing. Can do. Further, as in the first embodiment, a value larger than the shortest timing may be set as the set value. The timing selection circuit unit 17 may be provided on the setting unit 20 side.

(Embodiment 4)
Next, the data processing apparatus 10 of Embodiment 4 is demonstrated. In the fourth embodiment, as the setting value of the timing value 21 stored in the timing setting register 25 built in the setting unit 20 shown in FIG. It is the form which set time.

  FIG. 2D shows an example of a configuration in which the setting unit 20 is set with the shortest time 22 for each peripheral module 51 as the timing value 21. In the timing setting register 25, the corresponding shortest time 22 is set for the peripheral module name in the same format as in the second embodiment. In particular, the shortest time 22 may be different for each peripheral module 51. From the setting unit 20, a plurality of signals of the shortest time 22 corresponding to the peripheral modules 51 are supplied to the bus bridge control unit 1. In this example, in the timing setting register 25, the shortest time 22 in the first peripheral module 51-1 is “20”, the shortest time 22 in the second peripheral module 51-2 is “15”, and the Nth peripheral module 51 The minimum time 22 of −N is set as “5”.

  The bus bridge control unit 1 according to the fourth embodiment is basically the same as that shown in FIG. 6 (second embodiment) in terms of configuration and operation. The difference is that the supplied signal of the shortest time 22 is prepared as each signal of the shortest time # 1 to #N for each of the N peripheral modules 51, and the shortest time selection circuit unit is provided in the bus bridge control unit 1. Is to be added. The shortest time selection circuit unit selects the maximum value, that is, the signal with the slowest determination timing of the signal of the peripheral bus 50 from the plurality of signals of the shortest time 22, and uses this as the shortest time selection value to the timing calculation unit 16. Output. The timing calculation unit 16 outputs a timing calculation value 161 based on the shortest time selection value as in the case of FIG.

  Thereby, in the fourth embodiment, in the access to the peripheral module 51 via the bus bridge control unit 1, the data transfer processing can be performed in accordance with the peripheral module 51 in which the peripheral bus data 54 is determined at the latest timing. . The shortest time selection circuit unit may be provided on the setting unit 20 side.

(Embodiment 5)
Next, the data processing apparatus 10 of Embodiment 5 is demonstrated. In the fifth embodiment, the peripheral bus signal determination timing for each peripheral module 51 in the plurality of peripheral modules 51 is set as the setting value of the timing value 21 stored in the timing setting register 25 built in the setting unit 20 shown in FIG. In this embodiment, a value is set, and the bus bridge controller 1 selects a timing value according to the peripheral module 51 to be accessed and performs processing.

  The configuration of the bus bridge control unit 1 in the fifth embodiment is basically the same as that shown in FIG. 8 (third embodiment) in terms of configuration and operation. The difference is that a selector for selecting a timing value from a plurality of timing values # 1 to #N {21-1,..., 21-N} is provided instead of the timing selection circuit unit 17, and a peripheral bus command issue control unit 15 selects a timing value 21 corresponding to the data transfer processing at that time based on the access destination determination signal output from the selector 15 and outputs the selection signal as a timing selection value to the coincidence detector 13. It is. The access destination determination signal is a signal including peripheral module identification information, for example. An access destination determination signal can be issued from the CPU bus address 44 or the like input to the peripheral bus address issue control unit 112.

  Thereby, in the fifth embodiment, in the access to the peripheral module 51 via the bus bridge control unit 1, the data transfer process can be performed at the shortest timing according to the peripheral module 51 of the access destination. The same applies when the timing value 21 for each group of the peripheral modules 51 is set.

(Embodiment 6)
Next, the data processing apparatus 10 of Embodiment 6 is demonstrated. In the sixth embodiment, as the set value of the timing value 21 stored in the timing setting register 25 built in the setting unit 20 shown in FIG. In this mode, the time is set, and the bus bridge control unit 1 selects and processes the shortest time according to the peripheral module 51 to be accessed.

  The configuration of the bus bridge control unit 1 in the sixth embodiment is basically the same as that shown in the fifth embodiment in terms of configuration contents and operation. The difference is that a selector for selecting a plurality of signals of the shortest time # 1 to #N is provided, and the shortest time corresponding to the data transfer processing is based on the access destination determination signal output from the peripheral bus address issue control unit 112. The time 22 is selected by the selector, and the selection signal is output to the timing calculation unit 16 as the shortest time selection value.

  As a result, in the sixth embodiment, in the access to the peripheral module 51 via the bus bridge control unit 1, the data transfer process can be performed at the shortest timing according to the peripheral module 51 of the access destination.

(Embodiment 7)
Next, the data processing apparatus 10 of Embodiment 7 is demonstrated. In the seventh embodiment, the frequency ratio (clock ratio) between the CPU bus 40 and the peripheral bus 50 is set as the set value of the timing value 21 stored in the timing setting register 25 built in the setting unit 20 shown in FIG. It is a set form.

  FIG. 2E shows an example of a configuration in which the clock ratio is set as the timing value 21 in the setting unit 20. In the timing setting register 25, a value indicating the clock ratio between the CPU bus clock 31 and the peripheral bus clock 33 is set corresponding to the system configuration of the data processing apparatus 10. In this example, the clock ratio setting is 8: 1. As an actual set value, a value such as “8” representing the ratio may be set. A clock ratio signal corresponding to the set clock ratio is supplied from the setting unit 20 to the bus bridge control unit 1.

  The configuration of the bus bridge control unit 1 according to the seventh embodiment is basically the same as that shown in FIG. 6 (second embodiment) in terms of configuration contents and operation. The difference is that the signal supplied from the setting unit 20 becomes a clock ratio signal, and the timing calculation unit 16 determines the peripheral bus according to the frequency of the CPU bus 40 based on the clock ratio signal supplied from the setting unit 20. The shortest timing at which 50 data are determined is calculated in the form of the number of cycles of the CPU bus clock 31 and is output to the coincidence detection unit 13 as a timing calculation value 161.

  FIG. 9 shows a configuration example of the timing calculation unit 16 in the seventh embodiment. The timing calculation unit 16 can calculate the timing calculation value 161 corresponding to the case where the clock ratio between the CPU bus 40 and the peripheral bus 50 is set to 8: 1 to 1: 1, respectively. In this example, the timing calculation value 161 is “2” when the clock ratio is 8: 1 to 3: 1, “1” when it is 2: 1, and “0” when it is 1: 1. . Further, when the data processing apparatus 10 uses a clock ratio other than such a clock ratio, it can be coped with by preparing a timing value corresponding to the clock ratio used in the timing calculation section 16 in advance.

  As described above, in the seventh embodiment, optimum data transfer processing can be performed according to the state of the clock ratio between the CPU bus 40 and the peripheral bus 50. The timing calculation unit 16 may be provided on the setting unit 20 side. Further, the configuration of the timing calculation unit 16 may be a configuration in which each timing calculation value 161 is set in advance as in the case of FIG. 7 or a circuit that calculates the timing calculation value 161 by a simple calculation formula. Also good.

(Embodiment 8)
Next, the data processing apparatus 10 of Embodiment 8 is demonstrated. In the eighth embodiment, the timing value 21 set in the setting unit 20 shown in FIG. 1 and the timing signal supplied from the setting unit 20 to the bus bridge control unit 1 and the timing value 52 output from each peripheral module 51 are used. This is the form that is originally generated.

  FIG. 10 shows a configuration of the data processing apparatus 10 according to the eighth embodiment. The contents and operation of the configuration are basically the same as those shown in FIG. 1 (Embodiment 1). The difference is that signals of timing values 52 {52-1,..., 52-N} from the first to Nth peripheral modules {51-1,. The setting unit 20 generates and supplies a timing signal to be supplied to the bus bridge control unit 1 based on these timing values 52. Each peripheral module 51 supplies a value indicating the timing at which data to be output from its own module to the peripheral bus 50 is determined to the setting unit 20 as a timing value 52. The contents of the timing value 52 output from each peripheral module 51 are the timing value 21 in the first embodiment, that is, the format represented by the number of clock cycles of the CPU bus 40 or the format represented by the shortest time 22 in the second embodiment. And so on.

  For example, the setting unit 20 supplies the timing value 52 from each peripheral module 51 as it is to the bus bridge control unit 1 as a timing signal. Alternatively, the setting unit 20 stores each timing value 52 in the timing setting register 25 and generates a timing signal to be supplied to the bus bridge control unit 1 based on each stored timing value 52. Further, for example, the peripheral module 51 has an internal register for storing the set value of the timing value 52 in the own module, and outputs the timing value 52 from this register. The bus bridge control unit 1 has the configuration shown in the first to sixth embodiments according to the format of the timing signal, and similarly performs the synchronization process using the timing signal from the setting unit 20.

(Embodiment 9)
Next, the data processing apparatus 10 according to the ninth embodiment will be described. In the ninth embodiment, even when the setting of the timing value 21 set in the setting unit 20 shown in FIG. 1 is dynamically rewritten while the data processing device 10 is operating, the timing in the bus bridge control unit 1 This is a mode in which the data transfer process can be normally executed by applying the value 21 at an appropriate timing.

  FIG. 11 shows a configuration example of the bus bridge controller 1 in the ninth embodiment. The contents and operation of the configuration are basically the same as those shown in FIG. 3 (Embodiment 1). The difference is that the register 110 receives and holds the timing value 21 from the setting unit 20, and the peripheral bus signal determination timing update instruction signal (referred to as an update instruction signal) 34, which is a signal for instructing the data holding timing of the register 110. Is added. The update instruction signal 34 is supplied from the clock generation unit 30 and enables data retention in the register 110. The register 110 receives the timing value 21 and the CPU bus clock 31, holds the timing value 21 in accordance with the update instruction signal 34, and outputs it to the coincidence detection unit 13 as a peripheral bus signal determination timing update signal (referred to as an update signal) 1101. To do. The coincidence detection unit 13 receives the counter value 121 and the update signal 1101 and detects coincidence. Even when the clock ratio is changed while the data processing apparatus 10 is operating, the timing value 21 that is valid in the bus bridge control unit 1 can be updated by the update instruction signal 34, and normal data transfer processing can be performed.

  FIG. 12 shows an example of a time chart for explaining the operation of the bus bridge controller 1 shown in FIG. During operation, one or both of the CPU bus clock 31 and the peripheral bus clock 33 are dynamically changed. In this example, an operation when the clock ratio between the CPU bus clock 31 and the peripheral bus clock 33 is dynamically changed from 8: 1 to 2: 1 is shown. The period from t0 to t7 is a state where the clock ratio is 8: 1, and the clock ratio is changed to 2: 1 by changing the CPU bus clock 31 at the timing of t8. In this case, it is necessary to change the peripheral bus data determination timing with the change of the clock ratio. It is assumed that the setting of the timing value 21 before the change is “2”. It is assumed that the timing value 21 set in the setting unit 20 is rewritten from “2” to “1” at the timing of t1 with the change of the clock ratio. In this case, after that, the update instruction signal 34 is asserted from the clock generation unit 30 at the timing t7 which is the same timing as the clock synchronization signal 32. Then, the register 110 holds the timing value 21 in accordance with the update instruction signal 34 and outputs it to the coincidence detection unit 13 as the update signal 1101. The coincidence detection unit 13 compares the update signal 1101 with the counter value 121 and outputs a coincidence detection value 131. Accordingly, as shown in FIG. 12, when the clock ratio is 8: 1, the timing value 21 before rewriting is not the timing t2 (second cycle) indicated by the timing value 21 immediately after rewriting ("1"). The coincidence detection value 131 is asserted at the timing (second cycle) indicated by (2). The peripheral bus data (indicated by “D1”) 54 is held in the register 11 in accordance with the coincidence detection value 131, and is output as CPU bus data (indicated by “D1”) 111 at the timing t3. On the other hand, in a state where the clock ratio is 2: 1, the coincidence detection value 131 is asserted by the update signal 1101 at the timing (second cycle) t9 indicated by the rewritten timing value 21 (“1”). Then, the peripheral bus data (indicated by “D2”) 54 is held in the register 11 in accordance with the coincidence detection value 131, and is output as CPU bus data (indicated by “D2”) 111 at the timing of t10.

  As described above, in the ninth embodiment, even when the setting of the timing value 21 is dynamically rewritten according to a change in the clock ratio during the operation of the data processing device 10, the bus bridge control unit according to the update instruction signal 34. By updating the timing value applied (reflected) at 1, that is, the update signal 1101, the data transfer process can be executed at an appropriate timing.

(Embodiment 10)
Next, the data processing apparatus 10 according to the tenth embodiment will be described. The tenth embodiment uses the clock synchronization signal 32 to perform data transfer processing even when the setting value of the timing value 21 of the setting unit 20 is in an indefinite state immediately after hardware reset in the configuration shown in FIG. This is a form that can be normally executed.

  FIG. 13 shows a configuration example of the bus bridge controller 1 in the tenth embodiment. The contents and operation of the configuration are basically the same as those shown in FIG. The difference is that based on a peripheral bus signal determination timing setting completion signal (referred to as setting completion signal) 210 supplied from the clock generation unit 30, the coincidence detection value 131 and the clock synchronization signal 32 output from the coincidence detection unit 13 are different. That is, a selector 19 for selecting one of the above is added. A selection signal 191 output from the selector 19 is input to the AND circuit unit 14. The setting completion signal 210 is a signal indicating that the setting of the timing value 21 of the setting unit 20 is correctly completed. In this example, the setting completion signal 210 is output from the clock generation unit 30, but it may be output from another module.

  FIG. 14 shows an example of a time chart for explaining the operation of the bus bridge controller 1 shown in FIG. In this example, since it is immediately after a hardware reset in the data processing apparatus 10, an operation when the timing value 21 in the setting unit 20 is still in an indefinite state is shown. It is assumed that the timing value 21 is indefinite in the period from t0 to t7, and the normal timing value 21 “2” is guaranteed from the timing t8. In this case, the setting completion signal 210 is asserted simultaneously with the supply of the correct timing value 21 from the setting unit 20.

  Assume that an access occurs before the setting completion signal 210 is asserted. For example, the peripheral bus data 54 indicated by “D1” is output in the access for reading data to the peripheral module 51, and the peripheral bus data 54 indicated by “D2” is output in the next similar access. In this case, since the timing value 21 is in an indefinite state in the first access, the peripheral bus data 54 is transferred at the timing t7 using the clock synchronization signal 32 which is a late timing. That is, the selector 19 selects the clock synchronization signal 32 when the setting completion signal 210 is not asserted. On the other hand, in the access after the setting completion signal 210 is asserted, the peripheral bus data 54 is transferred at the timing t10 (third cycle) using the timing value 21 selected by the selector 19. As described above, in the tenth embodiment, even if the setting value of the setting unit 20 is in an indefinite state immediately after the hardware reset in the data processing device 10, the data transfer process is normally performed using the clock synchronization signal 32. It can be carried out.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is applicable to all computer systems such as a microcomputer that performs signal synchronization processing between buses of different frequencies.

It is a figure which shows an example of the whole structure of the data processor in Embodiment 1 of this invention. (A)-(e) is a figure which shows an example of the setting value stored in the timing setting register | resistor of a structure of the setting part in the data processor in each embodiment of this invention, and a setting part. It is a figure which shows the structure of the bus bridge control part in the data processor in Embodiment 1 of this invention. It is a figure which shows the structure of the counter part in the bus bridge control part in the data processor in Embodiment 1 of this invention. It is a time chart which shows an example of the data transfer process centering on the bus bridge control part in the data processor in Embodiment 1 of this invention. It is a figure which shows the structure of the bus bridge control part in the data processor in Embodiment 2 of this invention. It is a figure which shows the structure of the timing calculation part in the bus bridge control part in the data processor in Embodiment 2 of this invention. It is a figure which shows the structure of the bus bridge control part in the data processor in Embodiment 3 of this invention. It is a figure which shows the structure of the timing calculation part in the bus bridge control part in the data processor in Embodiment 7 of this invention. It is a figure which shows an example of the whole structure of the data processor in Embodiment 8 of this invention. It is a figure which shows the structure of the bus bridge control part in the data processor in Embodiment 9 of this invention. It is a time chart which shows an example of the data transfer process centering on the bus bridge control part in the data processor in Embodiment 9 of this invention. It is a figure which shows the structure of the bus bridge control part in the data processor in Embodiment 10 of this invention. It is a time chart which shows an example of the data transfer process centering on the bus bridge control part in the data processor in Embodiment 10 of this invention. It is a figure which shows the whole structure of the bus-bridge control part in the data processor used as the premise technique of this invention. It is a figure which shows the structure of the bus bridge control part in the data processing apparatus used as the premise technique of this invention. It is a time chart which shows an example of the data transfer process centering on the bus bridge control part in the data processing apparatus used as the premise technique of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,101 ... Bus bridge control part, 10 ... Data processing apparatus, 11 ... Register, 12 ... Counter part, 13 ... Match detection part, 14 ... AND circuit part, 15 ... Peripheral bus command issue control part, 16 ... Peripheral bus signal Determining timing calculation unit, 17 ... Timing selection circuit unit, 20 ... Peripheral bus signal determination timing setting unit, 21, 21-1, 21-2, 21-N ... Peripheral bus signal determination timing value, 22 ... Peripheral bus signal determination shortest Time, 25 ... Timing setting register, 30 ... Clock generation unit, 31 ... CPU bus clock, 32 ... Clock synchronization signal, 33 ... Peripheral bus clock, 34 ... Peripheral bus signal determination timing update instruction signal, 40 ... CPU bus, 41 ... CPU, 42 ... RAM, 43 ... CPU bus command, 44 ... CPU bus address, 50 ... peripheral bus, 51, 51-1 51-2, 51-3 ... peripheral module, 52, 52-1, 52-2, 52-3 ... timing value, 54 ... peripheral bus data, 110 ... register, 111 ... CPU bus data, 112 ... peripheral bus address issue Control unit 121... Counter value 131. Match detection value 141. Peripheral bus data retention enable signal 151. Peripheral bus data output period signal 152. Peripheral bus command 161 161 Peripheral bus signal determination timing calculation value 171. Timing selection value, 210... Peripheral bus signal determination timing setting completion signal, 1101... Peripheral bus signal determination timing update signal, 1121.

Claims (19)

A first bus to which a processor and a memory used by the processor are connected;
A second bus connected to one or more peripheral modules and slower than the first bus;
A bus bridge controller connected to the first and second buses and performing a signal synchronization process therebetween;
A data processing device having a clock generator for supplying a clock signal to each module connected to the first and second buses;
A setting unit that sets a value indicating a timing at which the signal of the second bus is determined and supplies a signal of the setting value to the bus bridge control unit;
When the processor accesses the peripheral module, the bus bridge control unit holds the signal of the second bus at the timing according to the signal supplied from the setting unit in the synchronization processing. A data processing apparatus. A first bus to which a processor and a memory used by the processor are connected;
A second bus connected to one or more peripheral modules and slower than the first bus;
A bus bridge controller connected to the first and second buses and performing a signal synchronization process therebetween;
A data processing device having a clock generator for supplying a clock signal to each module connected to the first and second buses;
A setting unit that sets a value indicating a timing at which the signal of the second bus is determined and supplies a signal of the setting value to the bus bridge control unit;
When the processor accesses the peripheral module for data reading, the bus bridge control unit uses the command and address for reading the data based on the command and address input from the first bus. Is output to the second bus, and the data read from the peripheral module is held at a timing according to a signal supplied from the setting unit, and output to the first bus. A data processing device. The data processing apparatus according to claim 2, wherein
The value indicating the timing is represented by the number of clock cycles of the first bus in the output of the signal of the second bus, and is stored in the setting unit. The data processing apparatus according to claim 2, wherein
The value indicating the timing is represented by a time in the output of the signal of the second bus and is stored in the setting unit. The data processing apparatus according to claim 2, wherein
The value indicating the timing is represented by a clock ratio between the first bus and the second bus, and is stored in the setting unit. The data processing apparatus according to claim 2, wherein
The setting unit has a nonvolatile memory,
A data processing apparatus, wherein a value indicating the timing is stored in the nonvolatile memory. The data processing apparatus according to claim 6, wherein
A data processing apparatus, wherein a value indicating the timing is written to or read from the nonvolatile memory of the setting unit by the processor. The data processing apparatus according to claim 2, wherein
The setting unit sets one type of value not depending on the number of the peripheral modules as a value indicating the timing, and supplies a signal of the one type to the bus bridge control unit,
The data processing apparatus according to claim 1, wherein the bus bridge control unit uses the one type of value in common in a synchronization process in access to all the peripheral modules. The data processing apparatus according to claim 2, wherein
The setting unit sets a value for each peripheral module as a value indicating the timing, and supplies a signal having one or more values to the bus bridge control unit.
The bus bridge control unit selects and uses one of the one or more value signals that has the latest timing for determining the signal of the second bus in the synchronization processing for accessing the peripheral module. Characteristic data processing device. The data processing apparatus according to claim 2, wherein
The setting unit sets a value for each peripheral module as a value indicating the timing, and supplies a signal having one or more values to the bus bridge control unit.
The bus bridge control unit selects and uses a signal corresponding to a peripheral module to be accessed from the one or more value signals in a synchronization process in accessing the peripheral module. . The data processing apparatus according to claim 2, wherein
The peripheral module supplies a signal having a value indicating a timing at which the signal of the second bus in the module is determined to the setting unit,
The data processing apparatus, wherein the setting unit generates and supplies a signal to be supplied to the bus bridge control unit from a signal supplied from the peripheral module. The data processing apparatus according to claim 11, wherein
The data processing apparatus according to claim 1, wherein the value of the signal supplied from the peripheral module is represented by the number of clock cycles of the first bus in the output of the signal of the second bus. The data processing apparatus according to claim 11, wherein
The data processing apparatus according to claim 1, wherein the signal supplied from the peripheral module has a value represented by a time in the output of the signal of the second bus. The data processing apparatus according to claim 11, wherein
The setting unit supplies a signal of one type of value to the bus bridge control unit based on a signal supplied from the peripheral module,
The data processing apparatus according to claim 1, wherein the bus bridge control unit uses the one type of value in common in a synchronization process in access to all the peripheral modules. The data processing apparatus according to claim 11, wherein
The setting unit sets a value for each of the peripheral modules as a value indicating the timing based on a signal supplied from the peripheral module, and sends a signal having one or more values to the bus bridge control unit. And supply
The bus bridge control unit selects and uses one of the one or more value signals that has the latest timing for determining the signal of the second bus in the synchronization processing for accessing the peripheral module. Characteristic data processing device. The data processing apparatus according to claim 11, wherein
The setting unit sets a value for each of the peripheral modules as a value indicating the timing based on a signal supplied from the peripheral module, and sends a signal having one or more values to the bus bridge control unit. And supply
The bus bridge control unit selects and uses a signal corresponding to a peripheral module to be accessed from the one or more value signals in a synchronization process in accessing the peripheral module. . The data processing apparatus according to claim 2, wherein
Along with a change in the system configuration, there is means for rewriting the setting of the value indicating the timing set in the setting unit during operation,
The bus bridge control unit updates application of a signal supplied from the setting unit at a timing according to an update instruction signal supplied from the clock generation unit and uses the updated application of the signal supplied from the setting unit. Data processing device. The data processing apparatus according to claim 2, wherein
When the setting value in the setting unit becomes indefinite immediately after resetting,
The bus bridge control unit, in the synchronization process, according to a setting completion signal supplied from the clock generation unit,
In the state where the setting is incomplete, a clock synchronization signal determined during the reset period is used as a signal indicating a timing at which the signal of the second bus is determined;
A data processing apparatus using a signal supplied from the setting unit when the setting is completed. A first bus to which a processor and a memory used by the processor are connected;
A second bus connected to one or more peripheral modules and slower than the first bus;
A bus bridge controller connected to the first and second buses and performing a signal synchronization process therebetween;
A data processing device having a clock generator for supplying a clock signal to each module connected to the first and second buses;
A setting unit that sets a value indicating a timing at which the signal of the second bus is determined and supplies a signal of the setting value to the bus bridge control unit;
The bus bridge control unit inputs a command of the first bus, issues a command to the second bus, and outputs a signal indicating a data output period of the second bus An address issuance control unit that inputs an address of the first bus and issues an address to the second bus, and inputs a clock and a clock synchronization signal of the first bus from the clock generation unit. A counter unit for counting, a coincidence detecting unit for detecting coincidence by inputting a count value of the counter unit and a signal supplied from the setting unit, and an output value of the coincidence detecting unit and a signal indicating the output period are input. And the second bus at a timing at which a signal is asserted from the AND circuit unit by inputting the data of the second bus and the clock of the first bus. of Holds over data, a configuration and a register output to the first bus,
When the processor accesses the peripheral module, the bus bridge control unit holds the signal of the second bus at the timing according to the signal supplied from the setting unit in the synchronization processing. A data processing apparatus.

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