JPH10326248A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compact and high speed DMA controller in which burst length in burst transfer can be selectively switched. SOLUTION: A burst end decoder 52 outputs a burst end signal s5 indicating the end of data transfer with burst length based on a burst length designation signal s10 from a CPU 90. A state machine 10 changes the instruction timing of data transfer to a memory controller 80 and the output timing of an update signal s6 to an incremented 22 of an address counter 20 and a decrementer 32 of a transfer counter 30 based on the burst end signal s5. Also, the update of address relevant information by the incrementer 22 and the update of number of data relevant information by the decrementer 32 is constituted of hard made common based on the burst length designation signal s10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct Memory Access) controller that supports burst transfer.

[0002]

2. Description of the Related Art Conventionally, in DMA, there has been a burst transfer in which a transfer executing means such as a memory controller transfers data in a unit of a plurality of bytes based on an instruction of a DMA controller. In this burst transfer, the DMA controller
For example, by designating a transfer destination address to a transfer execution unit such as a memory controller and instructing the transfer execution, the transfer execution unit reads data having a predetermined data length of, for example, 8 bytes from a predetermined transfer source address. , And to the addresses starting with the transfer destination address specified by the DMA controller. Less than,
The predetermined data length that the transfer execution means transfers at one time is called "burst length".

[0003] In other words, when a series of data transfer of the number of bytes specified by a control means such as a CPU is executed, a DMA transfer is performed.
The controller updates and specifies the transfer destination address in burst length units as described above, and repeatedly instructs execution of transfer. At this time, the DMA controller determines the end of a series of data transfer by updating the number of bytes specified by the control means in units of burst length.

Usually, a DMA controller includes an address counter for updating a transfer destination address in accordance with a burst length, a transfer counter for updating the number of data transferred in units of burst length, and an update timing of the address counter and the transfer counter. And a state machine for instructing the transfer execution means to execute the transfer is provided.

[0005]

Incidentally, some memory devices and I / O ports to be subjected to DMA have different burst lengths when executing burst transfer. Therefore, some DMA controllers have conventionally been able to switch the burst length.

However, such a DMA controller has a configuration including a state machine, an address counter, and a transfer counter corresponding to each burst length selectively designated. For example, 8 bytes and 16
DMA controllers capable of selectively switching between two burst lengths of bytes include state machines,
Two address counters and two transfer counters were prepared. As a result, the DMA controller that can switch the burst length becomes large in size, cannot increase the speed due to the increase in the critical path for the clock signal, and generally has a lower speed than the DMA controller in which the burst length cannot be switched. Had become.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a small-sized and high-speed DMA controller capable of selectively switching a burst length, as compared with a conventional DMA controller. With the goal.

[0008]

Means for Solving the Problems and Effects of the Invention The DMA according to claim 1 has been made to achieve the above object.
The controller instructs transfer execution means for collectively transferring the data of the burst length to transfer the data of the burst length, and outputs the update signal and the state control means for outputting the address-related information of at least one of the transfer source and the transfer destination. When an update signal that is held and output by the state control unit is input, an address holding and update unit that updates address-related information output to the transfer execution unit and an update signal that is output by the state control unit are input. Determining the end of a series of data transfer in accordance with an instruction from the control means based on the data number holding / updating means for updating the number of transferred data and the data number related information updated by the data number holding / updating means; Transfer end determining means for outputting a transfer end signal to the control means. A DMA controller which realizes a series of data transfers by repeatedly instructing the transfer execution means to transfer data of a burst length until it is determined that a signal has been input is provided for selectively designating a plurality of burst lengths. Based on the burst length designation signal from the control means and the transfer period signal output from the state control means during the data transfer by the transfer execution means, determine the end of the burst length data transfer and output a burst end signal to the state control means. The state control unit further includes a data transfer instruction timing to the transfer execution unit, and an address holding / updating unit and a data number holding / updating unit, based on the burst end signal from the burst end determining unit. And the output timing of the update signal of the .

The DMA controller of the present invention is for executing a series of data transfer based on an instruction from a control means such as a CPU. Substantial data transfer is performed by a transfer execution unit such as a memory controller. Here, the transfer executing means collectively transfers the data of the burst length as described above in accordance with the instruction from the DMA controller. Therefore, the DMA controller realizes a series of data transfer instructed by the control unit by causing the transfer execution unit to repeatedly execute such data transfer with the burst length.

In this DMA controller, the state control means represented by the state machine repeatedly instructs the transfer execution means to perform data transfer. It is necessary to specify at least one address-related information. Further, the address-related information needs to be updated each time the transfer execution means is repeatedly instructed to perform data transfer.

Therefore, the address holding / updating means holds the address-related information, and updates the address-related information based on an update signal from the state control means. It should be noted that “at least one of the transfer source and the transfer destination” may be specified by only the transfer source address-related information depending on the transfer execution means, or conversely, by specifying only the transfer destination address-related information. This is because there is also a case where the address-related information is specified. For example, the memory controller described in the related art indicates only a transfer destination address. Also,
The “address related information” may be the address itself or a part such as the upper 5 bits of the address.

Further, since the present DMA controller performs a series of data transfers based on an instruction from a control means such as a CPU, it is necessary to determine the end of the series of data transfers. For this purpose, a data number holding / updating unit and a transfer end determining unit are provided.

[0013] The data number holding / updating means holds data number related information related to the number of transferred data pieces.
Like the address-related information, the data-number-related information also needs to be updated each time the transfer execution unit is repeatedly instructed to transfer data. Therefore, the data number holding / updating means
The data number related information is updated based on the update signal from the state control means.

[0014] Then, the transfer end judging means, based on the data number related information held in the data number holding / updating means,
It determines the end of a series of data transfer and outputs a transfer end signal to the state control means. For example, "data number related information"
It is conceivable to use the number of untransferred data. In that case,
When the number of untransferred data becomes “0”, the end of a series of data transfer is determined.

[0015] When the transfer end signal is input from the transfer end determining means, the state control means stops the data transfer instruction to the transfer executing means and ends a series of data transfer. The DMA controller of the present invention instructs a plurality of transfer execution units having different burst lengths to perform data transfer, and a control unit such as a CPU uses a burst length designation signal to specify each of the transfer execution units. A burst length in data transfer is selectively designated from a plurality of burst lengths.

Therefore, in the DMA controller of the present invention, in addition to the above-described functions, the burst end determining means includes:
The number of data transferred by the transfer execution unit is counted based on the transfer period signal output from the state control unit during the data transfer by the transfer execution unit, and the transfer execution unit responds to the burst designation signal from the control unit. The end of the data transfer of the burst length is determined. When the end of the data transfer of the burst length is determined, a burst end signal is output to the state control means.

The state control means, based on the burst end signal from the burst end determination means, outputs a data transfer instruction timing to the transfer execution means and outputs an update signal to the address holding / update means and the data number holding / update means. Change the timing and. Conventionally, a state machine as a state control unit in a DMA controller has a data transfer instruction to a transfer execution unit and an address counter as an address holding / updating unit and a data number holding / updating unit as a data number holding / updating unit at a timing corresponding to one burst length. The update signal was output to the transfer counter. That is, in a DMA controller capable of switching a plurality of burst lengths, individual state machines corresponding to the selected burst lengths are provided. As a result, the size of the DMA controller is increased, and the critical path for the clock signal becomes longer due to the signal transmission delay.
The speed of the DMA controller could not be increased.

On the other hand, in the DMA controller of the present invention, the burst end judging means judges the end of the burst length data transfer by the transfer executing means based on the burst length designation signal from the control means, and outputs the burst end signal. Output to the state control means. By judging the burst end signal, the state control means repeats the data transfer instruction to the transfer execution means and the output of the update signal to the address holding / updating means and the data number holding / updating means at timings corresponding to the respective burst lengths. Do.

Thus, even when a plurality of burst lengths are selectively designated by the burst length designation signal, the state control means does not need to be individually provided so as to correspond to each of the selected burst lengths. The size of the DMA controller can be reduced. As a result, the delay in signal transmission is reduced and the critical path for the clock signal is shortened, so that the speed of the DMA controller can be increased.

By the way, it is conceivable that the state control means adopts the configuration described in claim 2. That is, the state control means enables the request signal for preparing the transfer execution means for data transfer in accordance with an instruction from the control means in the first state which is the initial state, and executes the transfer execution in response to the request signal. Transitions to a second state in which the input of the acknowledge signal transmitted from the means is determined.
When the acknowledgment signal from the transfer execution means is input in the state of (1), a control signal instructing the start of data transfer is output to the transfer execution means, and a third state of outputting a transfer period signal and a burst end signal The input is determined, and the fourth state in which the transfer period signal is output is alternately repeated. When the burst end signal is input in the fourth state, the input of the transfer end signal is determined and the request signal is output. The state is invalidated, the state shifts to a fifth state in which an update signal is output, and if a transfer end signal is input in the fifth state, the state shifts to the first state. On the other hand, the transfer end signal is changed in the fifth state. If no is input, a transition to the second state is made.

In this case, the state control means transitions between the first to fifth states. The first state is an initial state. Here, when there is an instruction from the control means, the state shifts to the second state. In the second state, a request signal for making the transfer execution unit prepare for data transfer is made valid. Further, it is determined whether or not an acknowledgment signal output from the transfer execution unit in response to the request signal has been input. Here, when the acknowledgment signal from the transfer executing means becomes valid, the state shifts to the third state.

In the third state, a control signal instructing the start of data transfer is output to the transfer executing means. Thereby, the transfer execution means starts data transfer. The transition from the third state to the fourth state is unconditional. In the fourth state, the input of the burst end signal from the burst end determining means indicating the end of the data transfer of the burst length executed by the transfer executing means is determined. If the burst end signal is not input here, the state shifts to the third state. On the other hand, when the burst end signal is input, the state shifts to the fifth state.

When the transfer execution means is transferring data, the state control means alternately repeats the third and fourth states. The state control means, when in the third and fourth states, outputs a transfer period signal indicating that data transfer is being performed by the transfer execution means to the burst end determination means. Thus, the burst end determining means can determine the end of the data transfer of the burst length.

In the fifth state, the request signal to the transfer execution means is invalidated, and the data transfer of the burst length is temporarily terminated. Further, it outputs an update signal to the address holding / updating unit and the data number holding / updating unit. Further, it is determined whether or not a transfer end signal has been input from the transfer end determining means. If a transfer end signal is input here, the state shifts to the first state and a series of data transfer ends. On the other hand, when the transfer end signal is not input, the state shifts to the second state in order to instruct the transfer executing means to transfer the next data.

That is, the state control means instructs the transfer execution means to perform data transfer in the second and third states, and the third and fourth state signals are not input unless a burst end signal is input from the burst end determination means. The states are alternately repeated, and when the burst end signal is input in the fourth state, the state shifts to the fifth state, and an update signal is output to the address holding / updating means and the data number holding / updating means, and the second state is returned again. Move to. As described above, when performing a series of data transfer based on an instruction from the control unit, the state transition unit performs the second → third → fourth →
A series of state transitions of third → fourth →... → third → fourth → fifth → second is repeated. At this time, a third signal is output according to the burst end signal input timing of the burst end determination means.
And the number of repetitions of the fourth state changes, as described above, the data transfer instruction to the transfer executing means performed in the second and third states, and the address holding / updating means and data performed in the fifth state. The output timing of the update signal to the number holding and updating means can be changed.

By configuring the state control means in this way, it is possible to correspond to a burst length selectively designated from a plurality of burst lengths, and the size of the DMA controller can be reduced. As a result, the signal transmission becomes faster and the critical path for the clock signal becomes shorter, so that the DMA
Speed up of the controller can be realized.

By the way, in consideration of miniaturization of the DMA controller, it is desirable that the address holding / updating means is configured as described in claim 3. That is, in addition to the configuration described in claim 1 or 2, the address holding / updating means further corresponds to a burst length selectively designated from a plurality of burst lengths based on a burst length designation signal from the control means. It is preferable that the address-related information be updated using a common hardware configuration.

[0028] The data number holding / updating means may further comprise:
It is desirable to configure as shown in FIG. That is, in addition to the configuration described in claims 1 to 3, the data number holding / updating means further supports a burst length selectively designated from a plurality of burst lengths based on a burst length designation signal from the control means. The update of the data number related information to be performed may be performed using a common hardware configuration.

Conventionally, in a DMA controller capable of selectively switching a plurality of burst lengths, a so-called address counter as address holding / updating means and a so-called transfer counter as data number holding / updating means also correspond to each burst length. Therefore, the DMA controller is separately provided, which results in an increase in the size of the DMA controller, and further, the occurrence of a critical path, which makes it difficult to increase the speed of the DMA controller.

On the other hand, in the DMA controller according to the third aspect, the address holding / updating means updates the address related information corresponding to a plurality of burst lengths with a common hardware configuration. The data number holding and updating means updates the address related information corresponding to a plurality of burst lengths with a common hardware configuration. This makes it possible to further reduce the size of the DMA controller,
As a result, the critical path for the clock signal is shortened, so that higher speed can be realized.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the DMA controller 1 of the present embodiment.

The DMA controller 1 includes a memory controller 80 as “transfer executing means” and a “control means”.
And performs a series of data transfers based on an instruction from the CPU 90. The substantial data transfer is performed by the memory controller 80. The memory controller 80 collectively transfers data of a burst length in accordance with an instruction from the DMA controller 1 of the present embodiment. Therefore, the DMA controller 1 realizes a series of data transfer instructed by the CPU 90 by causing the memory controller 80 to repeatedly execute the data transfer of such a burst length.

The memory controller 8 of the present embodiment
0 indicates that data transfer with two burst lengths of 8 bytes and 16 bytes can be selectively executed. Therefore, the DMA controller 1 of this embodiment is selectively designated by the burst length designation signal s10 from the CPU 90.
It operates according to two burst lengths of byte and 16 bytes. When the burst length of 8 bytes is designated, the burst length designation signal s10 is at the low level, that is, “0”. When the burst length of 16 bytes is designated, the burst length designation signal s10 is at the high level, that is, “1”. Becomes

The DMA controller 1 includes a state machine 10 as "state control means", an address counter 20 as "address holding / updating means", a transfer counter 30 as "data number holding / updating means", and a series of data. Based on the transfer end decoder 40 as “transfer end judging means” for judging the end of transfer, and the memory controller 80 based on the transfer period signal s4 from the state machine 10.
A burst counter 51 that counts the number of transfer data in the data transfer of the burst length in the memory, and a burst end decoder 52 that determines the end of the data transfer of the burst length in the memory controller 80 based on the count value of the burst counter 51. ing. Note that the burst counter 51 and the burst end decoder 52 correspond to “burst end determining means”. Although each block shown in FIG. 1 operates based on a clock signal, wiring for the clock signal is not shown in order to avoid complication.

The address counter 20 has an address register 21 for holding address-related information, and an incrementer 22 for updating the address-related information held in the address register 21. The address register 21 holds transfer destination address information as address related information. The initial value of the address related information is set by the CPU 90 prior to a series of data transfer (signal s8 in FIG. 1). The address-related information held in the address register 21 is output to the memory controller 80 (see FIG. 1).
Middle signal s7).

As shown in FIG. 6, the address-related information, which is the address information of the transfer destination, is the lower three bits of the transfer destination address.
It is 8-bit data excluding bits. When the memory controller 80 performs 8-byte data transfer, the lower three bits of the transfer destination address are counted from "000" to "111" by a binary number by the memory controller.
When the memory controller performs 16-byte data transfer, the memory controller uses “00” in binary.
It is counted twice from "0" to "111".

That is, since the lower three bits of the transfer destination address are held by the memory controller 80, the address register 22 of the address counter 20 in the DMA controller 1 holds the address-related information excluding the lower three bits of the transfer destination address. . Therefore, when the memory controller performs data transfer with a burst length of 8 bytes, the incrementer 22 of the address counter 20 sets “1” in the address-related information every time the data is transferred with the burst length.
Is added to the address-related information, and when the memory controller 80 performs data transfer with a burst length of 16 bytes, the incrementer 22 of the address counter 20 adds ""2" is added to update the address related information.

The incrementer 22 has a circuit configuration shown in FIG. In this case, when the burst length designation signal s10 from the CPU 90 is “0”,
When the update signal s6 from the state machine 10 is input while indicating the burst length of bytes, “1” is added to the input 8-bit address-related information and output. On the other hand, the burst length designation signal s10 from the CPU 90
Is "1", that is, when indicating the burst length of 16 bytes, when the update signal s6 is input, "2" is added to the input 8-bit address-related information and output.

On the other hand, as shown in FIG. 1, the transfer counter 30 has a transfer register 31 for holding data number related information.
And a decrementer 32 for updating the data number related information held in the transfer register 31. The transfer register 31 holds untransferred data count information in a series of data transfers as data count related information. The initial value of the data number related information is set by the CPU 90 prior to a series of data transfer (signal s9 in FIG. 1).

The number-of-data-related information, which is information on the number of untransferred data, is 8-bit data excluding the lower three bits of the number of untransferred data in a series of data transfer, as in the above-described address-related information. . As described in the address related information, the memory controller 80 counts the lower three bits of the number of untransferred data.

Accordingly, the decrementer 32 is
In the case where the memory controller 80 performs data transfer with a burst length of 8 bytes based on the burst length designation signal s10 from the CPU, "1" is subtracted from the data number related information for each data transfer of the burst length to thereby reduce the data number. When the related information is updated and the memory controller 80 performs data transfer with a burst length of 16 bytes, the data number related information is updated by subtracting “2” from the data number related information for each data transfer of the burst length. I do.

The decrementer 32 has a circuit configuration shown in FIG. In this case, when the burst length designation signal from the CPU 90 indicates that s10 is "0",
When the update signal s6 from the state machine 10 is input when the burst length of the byte is specified, “1” is subtracted from the input data number related information, and the burst length specification signal s10 from the CPU 90 is “ When "1", that is, when the burst length of 16 bytes is specified, when the update signal s6 is input, "2" is subtracted from the input data number related information.

When the DMA signal s0 from the CPU 90 is enabled, the state machine 10 starts a series of data transfer processing. Then, the state machine 10 repeatedly instructs the memory controller 80 to transfer data of a burst length. When the state machine 10 instructs the memory controller 80 to transfer data of a burst length, first, the state machine 10 transmits the request signal s1.
Is enabled, and in a state where the acknowledge signal s2 from the memory controller 80 is enabled in response to the request signal s1, the state machine 10 outputs a control signal s3 for instructing the start of data transfer to the memory controller 80. .

The burst counter 51 counts the number of data transferred by the memory controller 80 based on a transfer period signal s4 from the state machine 10 indicating that data transfer is being performed by the memory controller 80. The burst end decoder 52
The count value of the burst counter 51 and the CPU 90
It determines the end of the data transfer of the burst length by the memory controller 80 on the basis of the burst length designation signal s10 from the controller and outputs a burst end signal s5. Then, based on the burst end signal s5 from the burst end decoder 52, the state machine 10 issues a data transfer instruction and an update signal to the memory controller 80 at timings corresponding to the two burst lengths of 8 bytes and 16 bytes, respectively. The output of s6 is repeated.

Further, when the transfer end decoder 40 determines the end of a series of data transfers based on the data number related information held in the transfer register 31 of the transfer counter 30, it outputs a transfer end signal s11. State machine 1
0 is a transfer end signal s from the transfer end decoder 40.
When 11 is input, a series of data transfer processing ends.

Next, the DMA controller 1 of this embodiment
The operation of the state machine 10 will be described in detail with reference to FIG. FIG. 2 is an explanatory diagram showing a state transition of the state machine 10. First, before starting a series of data transfer based on an instruction from the CPU 90, IDLE as a “first state”
It is in a state. Here, when the DMA signal s0 from the CPU 90 becomes valid, a transition is made to the WACK state, which is the “second state”.

In the WACK state, the request signal s1 is valid. When the acknowledgment signal s2 from the memory controller 80 is input in response to the request signal s1, the state shifts to the B3 state, which is the “third state”. B
In state 1, the control signal s3 is output. As a result, the data transfer of the burst length is started in the memory controller 80. Then, the memory controller 80
During the data transfer period of the burst length of B, the states B1 and B2 are alternately repeated. In the B1 and B2 states, a transfer period signal s4 is output.

In the state B2, when the burst end signal s5 from the burst end decoder 52 is input,
The state shifts to the LAST state as the “fourth state”. LA
In the ST state, it outputs an update signal s6. Here, when the transfer end signal s11 from the transfer end decoder 40 is not input, the state shifts to the WACK state and the state transition described above is repeated. On the other hand, when the transfer end signal s11 is input from the transfer end decoder 40, the state shifts to the IDLE state and a series of data transfer ends.

The state transition of the state machine 10 described above with reference to FIG. 2 will be described with reference to the timing chart of FIG. FIG. 3 is a timing chart in which input / output signals for the state machine 10 are associated with state transitions of the state machine.

First, when the DMA signal s0 from the CPU 90 is enabled, a transition is made to the WACK state (in FIG. 3) (in FIG. 3), and the request signal s1 is enabled (in FIG. 3). Then, when the acknowledge signal s2 from the memory controller 80 is input (in FIG. 3).
The states B1 and B2 are repeated (in FIG. 3). When the burst end signal s5 from the burst end decoder 52 is input in the state of B2 (in FIG. 3), the state shifts to the LAST state and the update signal s6 is output. (In FIG. 3). LAS
In the T state, the request signal s1 is invalidated (in FIG. 3), and the data transfer of the burst length by the memory controller 80 is temporarily terminated.

Next, the DMA controller 1 of this embodiment
The effect of will be described. In order to facilitate understanding of the description, first, a conventional problem will be briefly described. Conventionally, in a DMA controller capable of selectively switching a plurality of burst lengths, blocks in the DMA controller that operate according to the burst length, such as a state machine, an address counter, and a transfer counter, have a block length corresponding to the selected burst length. It was provided individually according to each. Therefore, a DMA controller capable of selectively switching a plurality of burst lengths has been increased in size and has a delay in signal transmission, so that a critical path for a clock signal has been lengthened, making it difficult to increase the speed.

On the other hand, the state machine 10 in the DMA controller 1 of the present embodiment repeats a series of state transitions from the WACK state to the WACK state as described above, and issues a data transfer instruction to the memory controller 80 and an update signal s6. Output. At this time, as shown in FIG. 3, when the burst end signal s5 is input from the burst end decoder 52, the state shifts to the LAST state (in FIG. 3).

That is, since the output timing of the burst end signal s5 from the burst end decoder 52 changes based on the burst length designation signal s10 from the CPU 90, the repetition period of the B1 and B2 states in a series of state transitions (in FIG. 3). Changes. That is, the period of a series of state transitions corresponding to the data transfer of the burst length changes. Therefore, the data transfer instruction to the memory controller 80 and the output of the update signal s6 can be performed at the timing corresponding to the burst length selectively designated by the burst length designation signal s10.

Thus, in the DMA controller 1 of the present embodiment, although a plurality of burst lengths can be selectively switched, only one state machine 10 is provided as shown in FIG. As a result, the size of the DMA controller 1 is reduced as compared with the related art.

As described above, the DM of the present embodiment is
The incrementer 22 of the address counter 20 in the A controller 1 has a configuration shown in FIG. This circuit is different from a conventional addition circuit in that a logic element O indicated by α in FIG.
R and NOT are newly added. With this circuit, even if two burst lengths of 8 bytes and 16 bytes are switched by the burst length designation signal, "1" or "2" is added to the address-related information corresponding to each burst length. can do.

Similarly, the decrementer 32 of the transfer counter 30 in the DMA controller 1 of the present embodiment has the configuration shown in FIG. This circuit is obtained by newly adding a logic element AND and NOT shown by β in the drawing to the conventional subtraction circuit. By this circuit, even when two burst lengths of 8 bytes and 16 bytes are switched by the burst length designation signal s10, "1" or "2" is obtained from the data number related information corresponding to each burst length. Can be subtracted.

That is, according to the hardware configuration shown in FIGS. 4 and 5, it is possible to update the address related information and the data number related information corresponding to the selected burst length.
As a result, it is not necessary to provide an address counter and a transfer counter respectively corresponding to a plurality of burst lengths as in the related art, and the size of the DMA controller 1 is further reduced. As a result, the occurrence of a critical path can be suppressed, so that the speed can be increased.

As described above, the present invention is not limited to such an embodiment, and can be implemented in various forms without departing from the gist of the present invention. For example, in the above embodiment, since the memory controller 80 specifies the address-related information of the transfer destination, the address counter 20 of the DMA controller 1 includes the address register 21 that holds the address-related information of the transfer destination. However, if the transfer execution means such as a memory controller specifies both the source and destination address-related information, the address counter may include an address register that holds both the source and destination address-related information. It is also conceivable to provide an incrementer for updating both address related information.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a DMA controller according to an embodiment.

FIG. 2 is an explanatory diagram illustrating a state transition of a state machine.

FIG. 3 is a timing chart showing a relationship between input / output signals to a state machine and state transitions.

FIG. 4 is a circuit diagram showing a configuration of an incrementer of an address counter.

FIG. 5 is a circuit diagram showing a configuration of a decrementer of a transfer counter.

FIG. 6 is an explanatory diagram illustrating address-related information held in an address register of an address counter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DMA controller 10 ... State machine 20 ... Address counter 21 ... Address register 22 ... Incrementer 30 ... Transfer counter 31 ... Transfer register 32 ... Decrementer 40 ... Transfer end decoder 51 ... Burst counter 52 ... Burst end decoder 80 ... Memory controller 90 ... CPU s0 ... DMA signal s1 ... request signal s2 ... acknowledge signal s3 ... control signal s4 ... transfer period signal s5 ... burst end signal s6 ... update signal s10 ... burst length designation signal s11 ... transfer end signal

Claims (4)

[Claims] 1. A state control means for instructing a transfer execution means for collectively transferring data of a burst length to transfer data of the burst length, and outputting an update signal, and an address relation of at least one of a transfer source and a transfer destination. When information is held and the update signal output by the state control means is input, an address holding / update means for updating the address-related information output to the transfer execution means is output by the state control means. When the update signal is input, a data number holding / updating means for updating the number of data whose transfer has been completed; and a series of data instructed by the control means based on the data number related information updated by the data number holding / updating means. Transfer end determining means for judging the end of data transfer and outputting a transfer end signal to the state control means. DMA that realizes the series of data transfer by repeatedly instructing the transfer executing means to transfer the burst length data until it is determined that the transfer end signal is input from the transfer end determining means. A controller configured to selectively designate a plurality of burst lengths based on a burst length designation signal from the control unit and a transfer period signal output from the state control unit during data transfer by the transfer execution unit; A burst end determination unit that determines the end of the long data transfer and outputs a burst end signal to the state control unit.The state control unit further includes a burst end signal from the burst end determination unit. An instruction timing of the data transfer to the transfer execution means, DMA controller characterized by being configured so as to change the output timing of the update signal to said data number storing updating means. 2. The DMA controller according to claim 1, wherein the state control unit requests the transfer execution unit to prepare for data transfer in accordance with an instruction from the control unit in a first state which is an initial state. Signal, and shifts to a second state in which an input of an acknowledgment signal transmitted from the transfer execution unit is determined in response to the request signal. When the acknowledgment signal is input, a control signal instructing the start of data transfer is output to the transfer execution unit, and a third state in which the transfer period signal is output and the input of the burst end signal are determined. ,
The fourth state in which the transfer period signal is output is alternately repeated, and when the burst end signal is input in the fourth state, the input of the transfer end signal is determined,
The request signal is invalidated, and the state shifts to a fifth state in which the update signal is output. If the transfer end signal is input in the fifth state, the state shifts to the first state. A DMA controller configured to shift to the second state when a transfer end signal is not input in the state of (5). 3. The DMA controller according to claim 1, wherein the address holding / updating unit further includes a burst selectively designated from a plurality of burst lengths based on a burst length designation signal from the control unit. A DMA controller configured to update address-related information corresponding to a length using a common hardware configuration. 4. The DM according to claim 1, wherein:
In the A controller, the data number holding / updating means may further update the data number related information corresponding to a burst length selectively designated from a plurality of burst lengths based on a burst length designation signal from the control means. A DMA controller configured to use the hardware configuration of the DMA controller.