JPS62232036A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate necessity of correcting a large quantity of software so far used when adopting a new instruction set by making each instruction set include an alteration instruction that converts to execution of an instruction based on bother instruction set. CONSTITUTION:Two instruction sets are prepared respectively in instruction executing sections 107, 108 of a CPU103 and a coprocessor 104, and mode change instructions Inst.F. Inst.F' that instruct change of execution (mode 0) of an instruction based on the instruction set to execution (mode 1) of an instruction based on other instruction set are included in each instruction set of the CPU103. Instructions executed respectively by the CPU103 and coprocessor 104 constitute instruction queues 109, 110. The coprocessor 104 has a pre-decoder 111 that judges whether instructions fetched to constitute the instruction queue 10 are mode change instructions Inst.F, Inst.F' or not, and outputs an identification information [1] in the case of mode change instructions and outputs [0] in other cases.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is an information processing device, specifically, an information processing device that maintains an instruction queue of the same size as an instruction queue assigned to a central processing unit f (hereinafter referred to as a CPU). , performs fetching in synchronization with the CPU according to the status output from the CPU, and
The present invention relates to an information processing device including a slave processor (hereinafter referred to as a coprocessor) that executes instructions included in an instruction set of a CPU.

[Conventional technology]

Traditionally, this type of coprocessor is used in conjunction with a master processor. An example of a system using a kcPU and a coprocessor is shown in FIG. 3. In the system shown in FIG. 3, 301 and 302 indicate an address bus and a data bus, respectively. CI'U303 bus f
The interface unit 305 and the bus interface unit 306 of the coprocessor 304 exchange instructions or data with a program memory S and a working memory (not shown) via an address bus 301 and a data bus 302. For example, an instruction is executed by the instruction execution unit 307 of the CPU 303 having a single instruction set and the instruction execution unit 308 of the coprocessor 304 having an instruction set corresponding to the CPU. Prior to execution, the commands are formed in instruction queues 309 and 310', respectively, and sequentially supplied to instruction execution units 307 and 308 via internal data buses 311 and 312Y, respectively. 313.31
4 is the state of the instruction queue 309 of the CPU 303 (see below).

This is a signal line that sends the queue status QSTt (referred to as QSTo) to the coprocessor 304, and is 3.15°316
．． Information 317 indicates the type of active bus cycle (hereinafter referred to as bus status BST2).

B5T1. This is a signal line for sending a signal (referred to as BAT□) from the CPU 303 to the coprocessor 304.

Next, the CPU 303 and the coprocessor 304 execute instructions A-B (hereinafter referred to as Inst, A to E).
The procedure for executing will be explained with reference to the instruction queue state diagram shown in FIG. 4 and the explanation in Appendix 1.

FIG. 4 shows the contents of the instruction queues of the CPO 303 and coprocessor 304 shown in FIG.
The information output to the coprocessor 304 through 06 and the information output through signal paths 307, 308, and 309 are shown over time. For simplicity, the queue is 4.
Byte, and it is assumed that there is no memory access associated with the execution of each instruction. In5t and AzE are 1-byte long instructions, and In5t and CE are instructions from the CPU 303.

In5t,B is an instruction of the coprocessor 304.

Now the instruction queue 309 of the CPU 303 and the coprocessor 3
The command key 3-310 of No. 04 contains In5t, A to D (step 1 in FIG. 4).

The CPU 303 receives instructions from -309 to In5t.

Take out A. CI'U303 simultaneously connects signal path 313.
．． 314 to the coprocessor 30
Send to 4. The coprocessor 304 is.

In response to this queue status, l is sent from the instruction queue 310.
:nst, take out A. The instruction queue has been removed.
, zInst, A are sent to the instruction execution unit 307 via the internal data bus 311 in the CPU 303 and decoded. In coprocessor 304, internal data bus 312
In5t, A is an instruction of the CPU 303, and as a result of each decoding, the CPU 303 executes In5t and Ag, and the coprocessor 304 does nothing as it is. Do not work(
Step 2 in Figure 4).

CPU3Q3 is In5t, A has finished executing.

The command nst, B is taken out from the instruction queue 309. At the same time, the CPU 3Q3 receives the queue status indicating the extraction of the IByte of the instruction code through the signal paths 313 and 314, and the coprocessor 304 extracts In5t, Btt from the instruction key -310. Jnst.

B is Lnst, CLJ U 3 Q as well as A
3 and the instruction execution unit 308 of the controller 304 are decoded. nst, B is an instruction of the coprocessor 304, and the decoding result C
The PU 303 does nothing, and the coprocessor 304
5t, execute B (step 3 in FIG. 4).

In5t,B is not an instruction of the CPU 303.

The CPU 303 extracts In5t and C from the instruction queue 309 even when the coprocessor 304 is executing the instruction.
t'o: Igo-ni +3t) 4 reads Jnst, (, ft Take it out.

Since In5t,C is an instruction of the CPU 303, CP
U303 executes In5t and C-It. Coprocessor 304 continues to execute Inst,B without being affected by the decoding of In5t,C (step 4 in FIG. 4).

Here, the CPU 303 performs a primary fetch operation because the bus is not in use and there are fewer instruction codes in the instruction key -309.

The CPU 303 outputs the next address of the instruction code in the instruction queue 309 (in this case, the address where In5t and E are stored) to the address bus 301.

Next, the instruction code corresponding to the output address is output from the memory onto the data bus 302. The CPU 303 takes in the instruction code output to the data bus 302 and stores it in an instruction queue 309. During this fetch operation,
The CPU 303 outputs a path status indicating a fetch operation to the coprocessor 304 through 1M signal paths 315, 316, and 317. Upon receiving this status, the coprocessor 304 stores the instruction code on the data bus 302 in the instruction queue 310 in the same manner as the instruction code VCPU 303 was stored in the instruction queue 309 (step 5 in FIG. 4). Attached Table 1 shows the above operations in steps 1 to 5.

[Problem that the invention seeks to solve]

In general, when developing a new CPU, an instruction set that can realize new functions is required, but there is also a need to inherit the conventional instruction set so that a large amount of previously developed software can be used as is. However, since the conventional CPU 303 described above had only one instruction set that included instructions common to the coprocessor 304,
Despite the advantage of being able to receive support from the coprocessor 304, there is a problem in that a large amount of software that has been developed for the previous C and PU requires modification.

Accordingly, one aspect of the present invention relates to an information processing apparatus that makes it unnecessary to modify previous software when adopting a new instruction set.

[Means for Solving the Problems 1 Effects and Effects] In the information processing device according to the present invention, the following applies to a plurality of instruction sets executed by the central processing unit.

Each instruction set includes a change instruction that causes a transition from execution of instructions based on the instruction set to execution of instructions based on another instruction set. Therefore, when the central processing unit and the coprocessor are fetching instructions synchronously and the central processing unit is sequentially executing the instruction queue based on a certain instruction set, the above modification instruction is executed and the central processing unit's instruction set is When the instruction set is switched to another instruction set, the central processing unit thereafter executes instructions in the instruction queue based on the other instruction set. Therefore, by including the instruction set that enables the realization of the fr function and the previous instruction set in the multiple instruction sets of the central processing unit, the software developed based on the previous instruction set has to be significantly modified. It can be used as is even without it, and new functions can be realized.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment, in which address buses 101. The data bus 102 is a bus interface unit 105 between the CPUI O3 and the coprocessor 104,
It is used for exchanging address information, commands, etc. between the 106 and peripheral devices such as program memory. Instructions supplied via the bus interface units 105° and 106'ft are executed by instruction execution units 107 and 108 based on the instruction set. Instruction execution unit 1 of CPU 103 and coprocessor 104
Two instruction sets are prepared for each of 07°108 and CM9. Each instruction set of the CPU 103 has mode change instructions In5t, F, and In5t for instructing a change from execution of instructions based on that instruction set (mode 0) to execution of instructions based on another instruction set (mode 1).

F' is included (see Figure 5). Instructions executed by the CPUI O3 and the coprocessor 104 respectively constitute instruction queues 109 and 110, and the instructions fetched by the coprocessor 104 to constitute the instruction queue 110 are mode change instructions In5t and F.

A predecoder 111 that determines whether or not it is "In5t,li" and outputs identification information "1" if it is a mode change command, and outputs "0" otherwise. have. The output of the predecoder 111 is stored in a bit group 112 corresponding to the instruction queue 110, and bits TO to T3 correspond to instructions QO to Q3.
corresponds to each.

114 and 115 are internal data buses for sending the instructions in the instruction queues 109 and 110 to the instruction execution units 107 and 108, respectively, and the information "1" or "0" stored in the bit group 112 is connected to the 1M line. 116 to the instruction execution unit 108 in synchronization with the instruction.
08 switches the instruction set based on the information output from the bit group 112.

Next, the operation when the CPU 103 cooperates with the coprocessor 104 to execute instructions (In5t, B, In5t, F, In5t, B') while switching modes will be described.

FIG. 2 shows the contents of the instruction keys of the CPU 103 and coprocessor 104 shown in FIG.
The information outputted to the coprocessor 104 through 18 and the same information outputted through signal paths 119, 120, and 121 are shown over time.For simplicity, it is assumed that there is no memory access associated with the execution of each instruction. Also, the command is 1
This is a byte-long instruction, and among the instructions of the CPU 103, “
Instructions with "I" are mode I instructions.

It is assumed that the commands not marked are mode O commands.

gInst,B is the coprocessor 104 instruction.

Now, the CPU 103 and coprocessor 104.

It is assumed that the mode is O, and the instruction key 109 and the instruction key of the coprocessor 104 are empty. C
The PUI O3 performs 7 etches and stores nst, B in the PO of the instruction key 109.

The coprocessor 104 synchronizes with the CPUI O3 according to the bus status output from the CPU 103, and
Bft7z and stores it in instruction key x-11(1) QO. At this time, the predecoder 111.

“0” is passed through the signal path 113 to bit group 1 corresponding to the location where the instruction queue 110 is stored.
Store it in To of 12.

Subsequently, cpυ103 is In5t, F, In5t
, B'.

In5t, C'q y z, command key, -109
0Pl.

p2. Store in P3. Similarly, coprocessor 104@,
In5t, F, In5t, B', In5t, c'
Y instruction key 1-110 Ql, Q2. Store in Q3.

Here, the pre-decoder 111 sends the word "1" indicating that the instruction execution mode is to be changed due to the fetching of In5t, F through the signal path 113, so that In5t, F of the instruction key 110 is stored. A pit group corresponding to the location is stored in 1120 bits (ie, Tl) (step l in FIG. 2).

The CPU 103 executes In5t from PO of instruction *, -109.
, take out B. In the coprocessor 104.

Based on the key status output by CPUI O3.

Instruction key, -110+7) QO to instruction nst, B are sent through the internal data bus 115ft, and bit group 112 TQ to O''' are sent to the instruction execution unit 10g through the signal path 116.The coprocessor 104 is in the mode 0 state. , and executes this command.Meanwhile, the CPU 103 then takes out 1nst and F from Pl of the command key 109 (step 2 in FIG. 2).

In5t,F is an instruction that transitions the instruction execution mode of the CPU 103, and when executing this instruction, the CPU 103 changes the instruction execution mode from mode O to mode 1.
Transition to. At the same time, in the coprocessor 104, the internal data bus 1 from Ql to Jnst and F of the instruction key 110 is
15, "1" from T1 of bit group 112 is sent to instruction execution unit 108 through signal path 116. The signal sent to the instruction execution unit 108 through the signal path 116 is “1”.
゛.

As a result, the instruction execution mode of the coprocessor 104 also transitions from mode 0 to mode 1 (step 3 in FIG. 2).

CPUI 03 is In5t, B'9 instruction -1
Extract from 090P2 and execute. Coprocessor 104
However, according to the key status outputted by the CPU 103, In5t, B' is extracted from the instruction key 110. In5t,B' is the same code as the instruction In5t,B in mode 0, but since the instruction execution mode of coprocessor 104 is mode 1, it is not executed (step in FIG. 2).

At this point, the CPU 103 performs the fetch again and returns In5t.
, F', In5t, C, In5t, D f Store in POlPi, P2 of the instruction queue 109. Similarly, the coprocessor 104 also performs In5t, F', In5t, C, In
5t, D Store in QO, Ql, and Q2 of the Y instruction queue 110.

The predecoder 111 detects the fetched In5tJ' and enters the instruction execution mode? A signal "1" indicating that the command is to transition is passed through the signal path 113.

It is stored in the bit group 1120 bits (Zunawa TO) corresponding to the location where Jnst and F are stored in the instruction queue 110 (step 5 in FIG. 2).

Hereinafter, the coprocessor 104 executes an instruction in synchronization with the CPU 103, and when In5t, F' is extracted from the instruction key-110, the bit group 11 that is simultaneously extracted is
The instruction execution mode is changed from mode 1 to mode O again by the TO signal of 2.

For each step 1 to 5 above? Attached Table 2 summarizes the functions of the CPU I O 13, coprocessor 104, etc., and Attached Tables 3 and 4 explain kiss-status and bus status.

[Explanation of effects]

As explained above, the present invention has a very excellent effect in that when adopting a new instruction set, it is not necessary to modify a large amount of software that has been used up until then.

Separate table 3

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment, FIG. 2 is a state diagram of an instruction queue in one embodiment, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a state diagram of an instruction queue in a conventional example. , FIG. 5 is a conceptual diagram showing a change in instruction execution mode. 103...Central processing unit, 104...
Coprose, f, In5t, F, In5t, F'
----Change instruction, 111... Instruction identification means (predecoder), 112... Identification information storage means (bit group). Agent: Patent Attorney Susumu Uchihara 1 ”””′〉・.

Claims (2)

[Claims] (1) In an information processing device that includes a central processing unit that can sequentially execute a set of instructions stored in an instruction queue, and a coprocessor that fetches and executes the same instruction in synchronization with the central processing unit, An information processing device characterized in that, for a plurality of instruction sets executed by the device, each instruction set includes a change instruction for transitioning from execution of an instruction based on the instruction set to execution of an instruction based on another instruction set. . (2) The coprocessor determines whether the instruction is a modification instruction when fetching a plurality of instruction sets corresponding to the instruction set of the central processing unit, and if the fetched instruction is a modification instruction. and an identification information storage means for storing instruction identification information for outputting identification information in correspondence with the fetched instruction, and the identification information storage means stores identification information corresponding to an instruction that has already been fetched when the instruction is executed. 2. The information processing apparatus according to claim 1, wherein the read instruction set is changed from the read command set.