JPS61180346A - Microcomputer - Google Patents

Abstract

PURPOSE:To increase easily external memories by attaining the reference to an added external memory and also using a general-purpose register for reference to the external memory to increase the number of reference registers. CONSTITUTION:External memories (a-c) are connected to a CPU. Then registers R1 and R0 are put together and an instruction stored in the register R0 is set by an indirect address designation processing. A decoder connected to the CPU detects a data memory reference signal S2 and a register number S3 and activates the memory (b) is extracted by the contents of the register R1 sent to the outside from an address buffer AB. This extracted data is fetched by a data buffer DB via data buses D0-D7. Then the contents of the buffer DB are transferred to a tentative register TR1, and the contents of a tentative register TR0 are added with those of the TR1 by an arithmetic logic unit ALU. The result of this addition is stored in the register R0.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a microcomputer that has been improved in reference to external data memory.

<Prior Art> In recent years, 8-pit microcomputers have been used as various information processing devices. Conventional general 8-bit microcomputers had a 16-bit address buffer, so when using RAM external to the CPU, the address buffer could be up to 64 bits.
I was only able to use up to a byte of memory. Therefore, if you need to expand the external memory further, you need to: ■ Create a special instruction word to refer to the external memory, or ■ Create a special register to specify an indirect address path or index address for the external memory. ■Special switching registers were provided to switch external memory connections. However, to realize these configurations, it is necessary to add many internal circuits, and ■,■
In this configuration, it was impossible to freely add special command words or special registers due to the internal circuitry of the CPU. Also, if a switching register is provided to switch the connection of external memory as shown in ■, another external memory will be set on the existing external memory space, so it is impossible to use the same address between different external memories. For example, when external memories a, b, and c are set in the same memory space as shown in Figure 4, data transfer between these external memories is no longer possible. Transfer is not possible without rewriting the switching register.

Purpose of the present invention The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a microcomputer with high flexibility when expanding an external memory.

<Example> Hereinafter, an example according to the present invention will be described in detail using the drawings.

FIG. 1 shows an internal block diagram of a CPU of an embodiment of a microcomputer according to the present invention. In the figure, DB is a data buffer, Do-D7 is eight data buses, and data is transferred to and from an external circuit via the data buffer DB'i-. B is an internal data bus. TRO,
TRI is a temporary register, A, LU is an arithmetic logic unit that performs arithmetic operations and logical operations, IR is an instruction register that holds instructions, ID is an instruction decoder that decodes instructions, TC
RO-R3 is a general-purpose register, SP is a stack pointer, PC is a program counter, AB is an address buffer, and Ao-A15 are 16 address paths.

As shown in Figure 2, the CPU with the above circuit configuration is an external memo!
Connected to JEL+beQ.

The processing procedure for performing indirect addressing and index addressing using the microcomputer configured as described above will be explained.

- Indirect addressing instruction...ADD @Ri, RO Adds the contents of the data memory indicated by general-purpose register R1 and the contents of general-purpose register RO, and writes the result to general-purpose register RO.
Store 0 in 0 The processing of this instruction is as follows.

■ The contents of general-purpose register RO are transferred to temporary register TR.
Transfer to O.

■ Sends the contents of general-purpose register R1 to address buffer AB, and sends the register number already sent to instruction register IR (in this case, 1 indicating general-purpose register R1) to register number output line S3. Furthermore, control timing section rrC As shown in FIG. 2, the decoder connected to the CPU (the internal circuit diagram of which is shown in FIG. 3) transmits the data memory reference signal S2 and The register number signal S3 is detected and the external memory IJb' is enabled.

(2) Data at the desired address of memory b is retrieved from memory b according to the contents of general-purpose register R1 sent externally from address buffer AB, and then transferred to data bus D. - The data is taken into the data barafuna DB via D7.

■ The contents of the data buffer DB are transferred to the temporary register T.
Transfer to RI.

(2) Arithmetic logic unit ALU adds the contents of temporary register TRO and the contents of temporary register TRI, and stores the result in general-purpose register RO.

0 Index address specification instruction... ADD 10 (R1), RO Adds the 10th content from the data memory contents indicated by general register R1 and the contents of general register RO, and writes the contents to general register RO.
Store in.

The processing of this command is as follows.

■ Address difference between next words stored in data buffer DB (10 in this case) t-Temporary register TR
Transfer to O.

■ General-purpose ° The contents of raster R1 are stored in temporary register T.
Transfer to RI.

(2) Arithmetic logic unit ALU- adds the contents of temporary register TRO and the contents of temporary register TRI, and stores the result in address buffer AB. Further, the register number already sent to the instruction register IR (in this case, 1 indicating general-purpose register R1) is sent to the register number output line S3. Furthermore, the control timing unit TC sends out a signal S2 indicating that the data memory is to be referenced.As shown in FIG. 2, the decoder connected to the CPU detects the data memory reference signal S2 and the register number signal S3. to enable memory bt.

(2) Data at the desired address of memory b is extracted from memory b according to the contents of general-purpose register R1 sent externally from address buffer AB, and then transferred to data bus D. ~ D7 to the data buffer yDB.

■ The contents of the data buffer DB are transferred to the temporary register T.
Transfer to RI.

■ The contents of general-purpose register RO are transferred to temporary register TR.
Transfer to O.

(2) Arithmetic logic unit ALU adds the contents of temporary register TRO and the contents of temporary register TRI, and stores the result in general-purpose register RO.

In the above microcomputer, the CPU is provided with a dedicated terminal for sending out the data memory reference signal S2 and a dedicated terminal for sending out the register number signal S3i. Also, the decoder detects that the register number signal S3 is 0 (00
), memory a is selected and register number signal S3 is 1.
(01), memory b'6 is selected, and when register number signal S3 is 2 (10), memory c is selected.

Effects> According to the present invention, an external memory can be added and referred to without any special addition to the circuit configuration, and
Since the external memory is referenced using general-purpose registers, the external memory can be easily expanded by increasing the number of reference registers.

[Brief explanation of the drawing]

FIG. 1 is an internal block diagram of a CPU of an embodiment of a microcomputer according to the present invention, FIG. 2 is a connection configuration diagram between the CPU and external memory, and FIG. 3 is an internal circuit diagram of a decoder.
FIG. 4 shows a memory configuration diagram. In the figure, DB: Data buffer 7Do-D7: Data bus B: Internal data bus TRO, TRI: Temporary register ALU: Arithmetic logic unit ■R: Instruction register
ID=Instruction decoder TC: Control timing section RO-R3: General-purpose register SP Ni stack pointer PC nib program counter AB near address buffer
Ao~A15 Near address agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1

Claims (1)

[Scope of Claims] 1. a) a general-purpose register capable of specifying an address of an external data memory, b) a transmission means for transmitting the contents of the general-purpose register to an address path, and c) for the external data memory. d) a first output terminal that outputs register number information of a general-purpose register set to d); and a second output terminal that outputs a signal indicating that the external data memory is to be referenced. Features a microcomputer.