JPH01243121A - Data processing unit - Google Patents

Abstract

PURPOSE:To improve an arbitrariness and a facility in the case of making a rewriting method into the branching means of a command executing sequence by, when a program counter is rewritten from an external part, causing a command prefetched in an instruction register to be invalid in response to it. CONSTITUTION:When a program counter 3 is rewritten from the external part, the command prefetched in an instruction register 5 is made invalid in response to it by being cleared, etc. A control to clear the unnecessary command to be prefetched can be executed by an external control signal such as a mode signal FC to instruct the rewrite of the program counter 3 or by executing the command supplied from the external part. Thus, the arbitrariness and facility in the case of making the method to rewrite the program counter 3 from the external part into the means to branch the command executing sequence can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a technology for externally rewriting a program counter in a data processing device that controls instruction prefetching such as pipeline processing, and furthermore, for rewriting a program counter that has already been prefetched at the time of rewriting. The present invention relates to a technique for preventing execution of an instruction that is currently being executed, and is effective when applied to, for example, a digital signal processor.

[Prior art]

Digital signal processing, which processes digital signals through operations such as digital calculations and conversion using lookup tables, includes filtering, equalization, noise and echo removal, modulation, Fourier transformation, extraction of signal characteristic parameters, prediction, image enhancement, etc. Digital signals are used to process such digital signals in real time or at high speed.
In order to obtain high processing power in the limited field of digital signal processing, signal processors, for example, separate data memory and program memory, as well as buses for them, and perform instruction fetch, data transfer, and operations in parallel. In addition to enabling pipelining processing, it is also possible to transfer multiple data in parallel by installing multi-port memory and having multiple data buses, and furthermore, by providing separate multipliers and adders, the frequency can be increased. It employs a unique architecture that enables high-product-sum operations to be executed in parallel.

Incidentally, in such a digital signal processor, switching of the instruction execution sequence such as branching to exception processing can be performed by vector interrupts, etc., but the present inventor believes that the digital signal processor On the other hand, focusing on the configuration of a slave module, we investigated a technique to rewrite the program counter externally under the control of the host processor and branch to an arbitrary sequence.

The technique for externally rewriting the program counter is described in, for example, the rHD61811 data sheet published by Hitachi, Ltd. in January 1986.

[Problem to be solved by the invention]

However, according to the inventor's study, in a digital signal processor that performs instruction prefetch control when rewriting the program counter from the outside, simply rewriting the contents of the program counter does not prevent the contents of the program counter from being prefetched. The existing instructions remain in the instruction register. Therefore, if the program counter is forcibly rewritten externally and used as a means of branching, unnecessary instructions that do not need to be executed must be executed, and this will prevent errors in data processing. In order to do so, it may be necessary to take other measures such as software to ensure that the internal state such as retained data is not affected by the execution of the instruction, or it may be necessary to take measures such as software or other means to prevent the internal state such as retained data from being affected by the execution of the instruction. It is clear that there is a problem in that the content must be carefully examined, the arbitrariness as a means of branching the instruction execution sequence cannot be improved much, and the continuity of data processing is hindered. was made into

It is an object of the present invention to improve the arbitrariness and ease of using a method of externally rewriting a program counter as a means of branching an instruction execution sequence, and to improve the ease of use of a method of externally rewriting a program counter as a means of branching an instruction execution sequence. The object of the present invention is to provide a data processing device in which the continuity of data is not disturbed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when the program counter is rewritten externally, the instructions prefetched in the instruction register are cleared and invalidated in response. Control to clear unnecessary prefetched instructions is
This can be done by an external control signal such as a mode signal that instructs rewriting of the program counter, or by executing a command supplied from the outside.
.

[For production]

According to the above-mentioned means, when the program counter is rewritten externally, unnecessary instructions prefetched into the instruction register are invalidated by being changed to an instruction code that means non-operation. By doing so, we can easily and reliably prevent unnecessary instructions prefetched into the instruction register from being executed without taking any other special measures, and branch the instruction execution sequence to rewrite the program counter from the outside. This method achieves arbitrariness and ease of use as a means, prevention of errors, and continuity of data processing in such a branching method.

〔Example〕

FIG. 1 is a block diagram of a digital signal processor that is an embodiment of the present invention.

The digital signal processor 1 shown in FIG. 1 is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique, although not particularly limited thereto.

Although not particularly limited, the digital signal processor 1 of this embodiment has an instruction control system and a data transfer operation system separated, so that instruction fetch, data transfer, and operation can be pipelined in parallel. There is.

The instruction control system includes a program counter 3 and an instruction memory 4 addressed by the output of the program counter 3.
, an instruction register 5 that fetches instructions output from the instruction memory 4, and an instruction decoder and controller 6 that decode the instructions supplied from the instruction register 5 and provide control signals to each section.

The data transfer calculation system basically consists of RAM (random access memory), which is used for general purposes during calculations, and ROM (read-only memory), which stores constant data used for filtering, Fourier transform, etc. ), a plurality of data buses are connected to each port so that multiple data can be transferred in parallel, and a multiplier 8 and By individually providing arithmetic and logic units 9, it is possible to perform frequently occurring product-sum operations in parallel. For example, the RA included in the data memory 7
M write ports are coupled to data bus DB1. R
Each read port in AM and ROM is connected to data bus DB2. is coupled to DB3 and the data bus DB2
The data read out to the data bus DB3 is supplied in parallel to the multiplier 8 and the arithmetic logic unit 9=7-, and the data read out to the data bus DB3 is supplied in parallel to the multiplier 8 and the arithmetic logic unit 9. It looks like this. The output of the multiplier 8 can be supplied to one input terminal of the arithmetic and logic unit 9 for the product-sum operation, and the other input terminal of the arithmetic and logic unit 9 is also coupled to the data bus DBI. has been done. The output of the arithmetic and logic unit 9 is returned to the data bus DBI via an accumulator 10.

The data memory 7 includes, but is not particularly limited to, an address pointer 11 that increments and redecrements data set via the data bus DBI and outputs the incremented data.
, or an address signal supplied from the address field of the instruction via the instruction register 6.

The digital signal processor 1 is positioned as a slave module or a ferrule module that operates under the control of a host processor (not shown) in a predetermined system. It is not interfaced with a host processor, etc.

The digital signal processor 1 of this embodiment includes means for externally rewriting the program counter 3 in addition to the method using an interrupt signal as a means for externally changing the instruction execution sequence. According to this embodiment, the program counter 3 is coupled to the data bus DBI via the gate 13, although this is not particularly limited.
B 17! The address of the instruction to be executed can be arbitrarily changed by the data supplied from +1. Data for rewriting the value of the program counter 3 is given from a host processor (not shown) via the input/output circuit 12. At this time, the host processor sends a mode signal FC that instructs rewriting of the program counter 3, although this is not particularly limited. Assert. As a result, the gate 13 is opened, and the value of the program counter 3 is rewritten by data supplied from the data bus DBI.

The digital signal processor of this embodiment performs, for example, instruction fetching, instruction decoding, instruction execution, etc. in parallel by pipeline processing in response to the demand for high-speed digital signal processing or real-time processing.

Therefore, even if the value of the program counter 3 is externally rewritten at the end, the next instruction to be executed in the normal sequence has already been prefetched into the instruction register 5. The instruction is invalidated in response to the rewriting operation of the program counter 3. That is, the mode signal FC is supplied to the instruction register 5, and when this is asserted, the instruction held in the instruction register 5 is cleared. Here, clearing means changing the instruction held by the instruction register 5 to a value that makes it substantially a non-operation instruction. For example, when mode signal FC is asserted, instruction register 5 includes logic that changes its hold instruction to a value equal to the non-operation code. Note that such logic can be provided as a circuit block separate from the instruction register 5.

According to the above embodiment, the following effects can be obtained.

(1) When branching the instruction execution sequence by externally rewriting the program counter 3 on which instruction prefetch control is performed, in response to rewriting the contents of the program counter 3, unnecessary Since the instruction is forcibly cleared and made equal to the non-operation code, there is no need to execute an unnecessary instruction that has already been prefetched when forcibly rewriting the program counter from the outside and using it as a means of branching. There isn't.

(2) From the above effects, in order to prevent errors in data processing due to the execution of unnecessary instructions that have already been prefetched as in the past, the internal state of retained data etc. is not affected by the execution of the instructions. We have taken measures to make this possible through software, and
There is no need to thoroughly examine the contents of the instructions to be executed in vain, and the arbitrariness and ease of the method of branching the instruction execution sequence by externally rewriting the program counter 3 can be significantly improved.

(3) From the above effect (1), program counter 3
It is possible to maintain the continuity of data processing when branching from a normal sequence in a method of branching an instruction execution sequence by rewriting externally.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, the mode signal FC explained in the above embodiment can be applied as data indicating an operation mode by a combination of a plurality of bits.

Further, in the above embodiment, a case has been described in which a mode signal is used to rewrite the program counter 3 and clear the instruction register 5, but the present invention is not limited thereto, and the present invention is not limited to this, and the present invention is not limited to this. It can be done by For example, in this case, the digital signal processor has a command execution function, and addresses are assigned to the program counter and instruction register. When issuing commands for rewriting the program counter and clearing the instruction register, the host processor sets the addresses of the program counter and instruction register in the control register in order to specify the block to be processed.

Then, by a data transfer command or the like, the value of the program counter is rewritten, and the contents of the instruction register are rewritten to a non-operation code.

The digital signal processor may also include other functional blocks such as expanded memory and timers.

Additionally, the method of branching the instruction execution sequence by externally rewriting the program counter is also used to switch the test sequence as desired in LSI testing. Although the present invention is applied to a digital signal processor, which is a field of application, the present invention is not limited thereto, and can be applied to a coprocessor,
It can also be widely applied to various peripheral controllers. The present invention can be applied at least to conditions in which an instruction to be executed is prefetched into an instruction register based on the output of a program counter, and is decoded and executed.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, when the program counter is rewritten externally, the instructions prefetched in the instruction register are invalidated in response to this, so that the method of externally rewriting the program counter is an optional method for branching the instruction execution sequence. The advantage of this method is that it is possible to achieve ease of use, ease of use, prevention of errors, and continuity of data processing in such a branching method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal processor that is an embodiment of the present invention. 1... Digital signal processor, 3...
Program counter, 4... Instruction memory, 5... Instruction register, 6... Instruction decoder and controller, 7... Data memory,
8... Multiplier, 9... Arithmetic logic operator, 11...
Address pointer, 12... Input/output circuit, 13...
Gate, FC...mode signal, DBI~DB3...
data bus.

Claims (1)

[Scope of Claims] 1. In a data processing device that prefetches an instruction to be executed into an instruction register based on the output of a program counter, decodes and executes the instruction, the program counter is made externally rewritable; 1. A data processing device characterized in that when a program counter is externally rewritten, an instruction prefetched into an instruction register is invalidated in response to the program counter being rewritten from outside. 2. The program counter is coupled to the internal data bus via gate means, and in response to an instruction to rewrite the program counter by an external control signal,
2. The data processing apparatus according to claim 1, wherein said gate means is opened and also controls clearing of instructions prefetched into an instruction register. 3. The rewriting control for the program counter and the corresponding clearing control of the instructions prefetched in the instruction register are performed by executing a command supplied from the outside. A data processing device according to claim 1.