JPS59136831A - Data transfer controller - Google Patents

Abstract

PURPOSE:To process at a high speed the transfer of blocks of variable length bit data by reforming the bit data when the word data is transferred. CONSTITUTION:A source bit address register 21 shows the bit address of a block to be transferred, and a destination bit address register 22 shows the bit address of a transfer destination block. A detecting circuit 30 detects the difference of contents between registers 21 and 22. A shift circuit 25 gives a shift of digit to the word data of a block to be transferred in response to the output of the circuit 30. The data received the digit correction from the circuit 25 is synthesized with the word data on the transfer destination block, and these synthesized data are transferred. In other words, the word data is shifted when the word data which is used as the unit transfer of a memory device is transferred. Then the word data is connected to a part of the word data to be transferred next as well as the word data of the transfer destination to be reformed as new word data. Then this new word data is transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access control device in a data processing system using a memory device whose access unit is a word consisting of fixed-length bits.

FIG. 1 shows the configuration of a data processing system employing a conventional general direct memory access device. Here, the processor 1 and the direct memory access control device 2 share the memory device 3, and according to the data transfer request signal DREQ from the peripheral device 4, the direct memory - The access control device 2 transfers data between the memory device 3 and the peripheral device 4 between the program transfers of the processor 1 or after forcibly prohibiting program transfers, thereby allowing data transfer requests to be performed. Since data transfer can be immediately responded to, a high data transfer rate can be obtained. .

In addition, the data transfer method using a direct memory access control device can not only be used for data transfer between peripheral devices and memory devices as described above, but also take advantage of its high data transfer rate to transfer data between memory devices. It can be applied to transfer. FIG. 2 shows a general configuration of a data processing system that employs a direct memory O access control device for data transfer between memory devices. In order to transfer a data structure that is consecutive at a ratio (hereinafter referred to as a data structure) to a different memory device 12, the processor 13 sends a data transfer request signal DREQ to the direct memory access control device 14. Due to this occurrence, the direct memory access control device 14 sequentially transfers the program data located in the memory device 11 to the memory device 12, thereby realizing extremely high-speed program data transfer. can.

By the way, the memory space that can be accessed by the processor is developed from the word address, which is the access unit of the memory device, into a so-called bit write address in which an address is assigned to each bit that constitutes word data, and this is
If expressed as a straight line as shown in the figure, the above-mentioned pro, ri,
``Transfer of data'' is nothing but copying a line segment t with a certain length as a line segment L' at a distance d on a straight line.1Ii1Movement of 1 minute t to line segment t' distance d
This is a process between blocks in data transfer.

However, in data transfer using a conventional direct memory access control device, one data transfer unit is the word specified by the word address, which is the access unit of the memory device. - Because the data is used, the size t of the block meeting data and the distance d between blocks are limited to integral multiples of the number of bits constituting the word data.
Furthermore, as seen in the applications in graphics and computer science,
In applications where the main focus is to treat memory space as a collection of bit data rather than as a collection of word data, word and
A data structure that spans two words even though the data widths are equal, or a so-called bit variable length data structure that contains multiple pieces of data or part of data in one word as shown in Figure 4b. In the case of a program p, 112. When attempting to transfer data, the destination
Bit data that is not originally a target of transfer is also transferred to the word data corresponding to the word address including the address, and the bit data originally included in this word is lost. Therefore, it is impossible to use a conventional direct memory access control device for the transfer of bit variable length data, and this has to be realized by slow program transfer.

An object of the present invention is to provide a data transfer control device that enables the transfer of variable length bits, and during shift data transfer, which is a unit transfer of a memory device, the word data is transferred by an arbitrary number of bits less than the word data width. The data is shifted and combined with a part of the word data to be transferred next and the word data of the transfer destination to be reconfigured as new word data and then transferred as word data. In a data processing system using a memory device consisting of a set of word data consisting of fixed-length bits, it is possible to transfer arbitrary bit-variable-length data to an arbitrary bit address in the memory space. This enabled high-speed block data transfer.

The present invention includes a source bit address register indicating a source bit address in a memory space of a bit data block to be transferred, and storing word data including bits indicated by the source bit address register. An input buffer to shift the word data of the input buffer γ by an arbitrary number of bits, and a transfer destination bit.
a destination bit address register indicating a bit address in the memory space of the data fist block; an output cover storing word data including the bit indicated by the destination bit address register; A synthesizer that selects and outputs the output of the output and the output cover, the input of the NOR, a counter that counts the number of transferred bits, and detects the difference between the contents of the source bit address Φ register and the destination bit address register. The present invention is characterized in that it includes a subtracter and a control circuit that performs timing control of the components.

The configuration and operation of an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 5 shows an embodiment of the present invention that handles so-called byte data having a word width of 8 bits. A source bit address register 21 for specifying the bit address of the transferred bit data. Distone and bit address register 22 for specifying the bit address of the destination bit data block. A human cover for storing the byte data containing the bit specified in the source Φ bit address address e register 21, Noah 2
3. input <'y The previous byte stored in 7723
Noah 24, an expansion cover that stores data. A shifter 25 for selecting arbitrary consecutive 8 bits from a series of 16 bits of data stored in the input cover, Noah 23, and the extended user cover, Noah 241C. Multiplexer 26 which selects the output of shifter 25 and the byte data containing the destination bit address-register 22. Output buffer 27 for storing the output of multiplexer 26. Bit counter 28 for counting the number of transferred bits. Decrementer 29 for updating the contents of bit counter 28. A subtractor 30 for detecting the difference between the contents of the source bit address register 21 and the destination bit address register 22.A control circuit 31 for controlling the operation and timing of all the aforementioned components. including.

Next, the operation will be explained using FIG. 6 which shows the flow of the operation.

The source bit address register 21 and the destination e-bit address register 22 each hold the bit address of the bit data currently being transferred. It has a byte specification section that specifies byte data that stores or should be stored, and a bit specification section that specifies the relative position of bit data in the specified byte data. Therefore bit address A
b is the content of the byte specification part, B is the content of the bit specification part.
(θ~7), it is expressed as Ab=Bx8+b.

Source bit address e register 210 byte designation section The byte data at the designated address 8B is stored in the input buffer 23 by strobe signals I B and F' 8. Furthermore, the byte data immediately before the user stored in the human cover Noah 23 is stored in the expansion human power buffer 24 by the strobe signal EIBF. At this time people Kabuffa 2
Whether the byte data stored in 3 contains enough bit data to be transferred to the DB address specified by the 220-byte specification field of the destination 6-bit address register. source bit
Contents sb of bit designation part of address register 2-1, destination command pin, l...Address reference register 2
The subtracter 30 compares the contents Db of the bit designation section No. 2 with the contents Db of the bit designation section No. 2 to check. If the result of Db-8b is negative, the subtracter 30 outputs a data request signal MO indicating that the byte data stored in the NOR 23 is insufficient.
The byte data of the current human cover 7A23 is transferred to the extended human cover Noah 24 using the strobe signal FIB8, and the byte data of address 8B and +1 is transferred to the 9 person cover using the strobe 1 word IBPS. , stored in Noah 23. In this way, the input buffer 23 and expansion manual buffer 24 obtain continuous 16-bit data, but this is done by starting from the Oth bit of the byte Φ data at the SB address and moving it from O to 7 bits to the right (decreasing the bit address). This occurs because 2 bytes of data are required to obtain the byte data shifted in the smaller direction).

Shifter 25 is source bit φ address register 21
In order to correct the misalignment between the transferred byte contention data indicated by the 0-byte designation field and the destination bit (transfer destination pie indicated by the byte designation field of the address register 22)-data bit, this shift is Subtractor 3 shown
Output of 0, that is, source bit, 1...Shift selects the difference (8b-Db) between the content sb of the bit specification part of the address register 21 and the content Db of the bit specification part of the destination bit address register 22. Signal 8HTn
As, the human power buffer 23 and the extended human power buffer 24
The 16-bit data is shifted 8b-Db bits to the right (in the direction of decreasing the bit address) to obtain the lower 8 bits. At this time, if 5b-8d<0, a left shift (in the direction of increasing bit address) is required.

The byte data obtained by the shifter 25 is as described below.
Otherwise, the strobe signal OBF 8 is stored in the output buffer OBF without any modification in the multiplexer 27.

First, when there is no destination bit address (
Consider 1 to 7). The aforementioned Toshidistonesi, N.
The bit specification part of the bit address register 22 indicates the bit position of the transfer bit in the transfer destination byte data, but since the bit data is transferred as a byte gater, the first byte transfer of the bit data processor It is reset to 0 at all other times. In other words, Db≠0 means that this transfer is the first byte of the bit data transfer, and the bit data less than Db (0 to Db-
1) indicates that it must not be destroyed during data transfer. At this time, the output of the shifter 25 is the upper Db~
The bits up to 7 are selected, and the lower bits from 0 to Db-1 are selected by the lower multiplex selection signal MPXL of the multiplexer 26, and the DB specified by the byte specification section of the destination bit address register 220 is selected.
The lower 0-Db-1 byte data of the address is selected, and the selected byte data is stored in the output buffer 27 by the strobe signal 0BFS.

Second, the contents of the bit counter, that is, the number of remaining transfer bits BO is less than 8, which is the number of bits composing the byte data (BO(8
). This state indicates that the next transfer is
This indicates that bit data (BO to 7) of BC bits or more at the time of the last byte transfer of a data block must not be destroyed by byte data transfer. At this time, the lower 0-BC-1 is selected as the output of the controller 25,
The upper bits from BO to 7 are selected by the upper multiplex selection signal MPXH of the multiplexer 26 from the upper BC to the byte data of the DB address specified by the byte specification section of the destination bit address register 22.
Bit data up to 7 is selected, and the selected byte data is stored in output buffer 27 by strobe signal 0BFS.

The above two conditions occur simultaneously when bit data of less than 8 bits is transferred from bits other than the 0th bit of the transfer destination byte data, but the above operation causes bits φp and p of the transfer destination byte data to be transferred.

Bits and data other than data are compensated.

The byte data stored in the output buffer 27 is transferred to the DB address specified by the byte specification field of the distonne bit address register 22, and one bit transfer data is transferred. ends.

Each time the source bit address register 21 transfers byte data to the input buffer 23, the contents of the byte designation field are incremented by 1 by the increment signal lNO3, and the bit designation field is incremented by the previous content sb and the destination bit address register 21. Difference S from the contents Db of the bit and g designation parts of the address register 22
b - D b obtained by the subtracter 30 is set by the setting signal 5ET8. This behavior causes the source
The contents of the bit address register 21 always indicate the beginning of the next bit or bit data program to be transferred.

On the other hand, the distone bit address register 22 increments the contents of the byte designation field each time the byte data stored in the output buffer 27 is transferred to the outside.
Add 1 to 0D and reset the bit designation section with signal 5BT
1) Set to '0' by D.

This behavior does not always result in a byte transfer, except for the first byte transfer.
This indicates that bit data can be transferred starting from the 0th bit of data.

Further, the bit counter 28 is set to 8 byte by the decrementer 29 every time byte data is transferred from the output buffer 27.
-Reduce Db. This operation indicates that, except for the first byte transfer, 8-bit bit block data is transferred according to the byte transfer (Db is set to 0 for the second and subsequent byte transfers as described above). ). In addition, since the bit counter 28 indicates the number of remaining 9 bits to be transferred, the content exceeding the lower 3 bits indicates the number of remaining bytes to be transferred, and BOO indicates that the content of the lower 3 bits or more is 0. , indicating that this is the last transfer.

It is clear that the above object can be achieved by repeating the above operation until it is detected by the BOO signal that the content BO of the bit counter 27 becomes 8 or less.

Next is the bit pro when this embodiment is used.

An example of data transfer will be explained using FIG. In this example, a source bit data block having a length of 24 bits starting from the bit address 10 shown in FIG. 7(a) and starting from the bit address 110 shown in FIG. Distones starting from the address, nφ bit,
The purpose is to transfer data blocks. Therefore, the content 8B of the byte designation part in the source bit address register 21, the content sb of the bit designation part, and the content Db, B, and the content Db of the bit designation part of the byte designation part in the destination bit o address register 22. has the following values:

8B=1, 5b=2. DB=13. Db=6 Figure 7 (C
) shows a state in which the source bit data shown in FIG. 7(a) is shifted to the left by 4 bits. Figure 7(d) shows the destination B.

Indicates the first transferred byte data to the data block (address 133 0 at this time Db-8b=6-2=420
It can be seen that the byte data stored in the sb cover 23 contains enough data for the byte transfer to the destination bit data processor. However, since Db=6≠0 and bits 0 to Db-1 (Q to 5) of the byte data at address 133 must not be changed, the lower 6 bits of the byte data at address 133 must be changed.
The bits and pieces must be preserved. After the byte data transfer at address 133, SB, 8b, DB, and Db have the following values.

8B=2.8b=4. DB=14. Db=0 FIG. 7(e) shows the distortion, bit data pro,
Indicates the second transfer byte data to RI (address 144. In this poet's cover, the byte data of address 2 is stored in F23, and the byte data of address 1 is stored in F24 of the extended user cover. .

In the output buffer 27, the 2 bytes (16 bits) stored at address 1 - data are shifted to the right (in the direction of decreasing bit address) 5b - Db = 4 - 〇 = 4 bits, the lower 8 bits are bit shifted, The first byte data is stored and transferred to address 144. After transferring the byte data at address 144, SB,
Sb, DB and Db have the following values.

8B=3, 5b=4. DB=15. Db=0 Figure 7 (
f) indicates the third transferred byte data to RI after destination bit data transfer (address 155).

After transferring the byte data at address 155, SB, Sb, D
B and Db have the following values.

8B=4, 5b=4. DB=16. Db=0 Figure 7 (2
)) indicates the fourth (last) transferred byte data to the destination bit data block (16
Address 6 0 At this time, Kapaffa 23 has a part-time job at address 4.
data, expansion user cover, and the byte at address 3 in F24.
If the data is stored in the block, the destination bit is sufficient for the byte transfer to the data block, etc.
The source bit data block has 5 bits left (BO=6).
Just bit BO of address 166 byte data
7 (6-7) must not be changed, the top two bits and pieces of address 166 are saved.

As a result, the above objective can be achieved reliably. In addition, in this embodiment, the source bit Φ address register 21 and the destination bit address register 22
It is clear that by initializing both bit designation parts to 0, the function of the conventional direct memory access control electronic manufacturing, that is, the function of byte processing, data transfer, is achieved. Although the transfer direction is limited to sequential transfer in the direction of increasing addresses, four cages can be achieved by updating the bit address register.

Since the data can be transferred in the direction of decreasing the number of addresses, it is clear that transfer between data processors having overlapping addresses can be realized without any problem.

As explained above, the present invention realizes high-speed block transfer of variable-length bit data by reconfiguring bit data during word data transfer, and is a versatile direct memory processor. An access control device can be obtained.

[Brief explanation of the drawing]

Figure 1 is a general diagram of a direct memory access control device applied to data transfer between a peripheral device and a memory device, and Figure 2 is a diagram of a direct memory access control device applied to a memory device. FIG. 3 is a diagram showing data movement in data transfer using a conventional direct memory access control device, and FIGS. 4a and 4b are bit diagrams. FIG. 5 is a diagram showing an example of variable length data, FIG. 5 is a diagram illustrating an embodiment of the present invention, FIG. 6 is a flow chart showing the operation of the embodiment, and FIG. 7 is a diagram showing the operation of the embodiment. It is a figure showing an example. 1...Processor, 2...Direct memory access control device, 3...Memory device, 4...Peripheral equipment fi,'s... ...System bus, 11.12 ...Memory device, 1
3...Process...14...Old...Direct...
Memory access control device, 15...System bus, 21...Source e-bit address.
Register, 22... Destination bit address register, 423 Old... Input cover. 7a, 24... Human power buffer for expansion, 25...
Group shifter, 26...Multiplexer, 27.
Old: output buffer 7, 28: bit counter, 29: old: decrementer, 30: subtracter, 31: control circuit. REQ DRεQ He-N+1--←-N+ ---Word, Ar°LS-N+4 N-←
--Ward Ams (b) Ward 4

Claims (1)

[Scope of Claims] A source-bit address register indicating a bit address of a transferred program, and a distonity indicating a bit address of a destination program. the contents of the source bit address register, the source bit address register, and the destination bit address register;
a detection circuit that detects a difference in the contents of the habit address register; and a shift circuit that shifts the word data of the transferred block according to the output of the detection circuit;
A direct memory access control device characterized in that the data digit corrected by the shift circuit and the word data at the transfer destination are combined and transferred.