JPS63228360A - Dma controller - Google Patents

Abstract

PURPOSE:To attain a high speed operation and the access to the address space of a wide range with simple constituting by dividing increment/decrement operation into individual operation unit and adopting system to be exchanged. CONSTITUTION:A selector circuit 3 which segments a holding register for DMA address and a holding register for the number of transfer bytes, selects one content among them and inputs it to an operation circuit, and the operation circuit 4 which executes increment and decrement with respect to the operation unit are provided. With using an incrementer/decrementer circuit having the bit width for one divided operation unit, count operation with respect to the register having the optional bit width is enabled. Since the incrementer/ decrementer circuit turns into the circuit of a small-scale, an operation delay value becomes small, and the counter action speed of one time can speedily designed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to 1) an HA control device, particularly a DMA control device that generates 7 addresses for controlling DMA transfer and counts the number of transferred bytes.

[Conventional technique f]

Conventional DMA control system fk+, JP-A-58-21703
As described in Publication No. 3, by performing seven operations on the contents of the DMA address register or transfer byte count register using an incrementer and decrementer circuit, and then writing to the corresponding register again, the DMA address and transfer byte count register can be calculated. [Problems to be Solved by the Invention] In the above-mentioned conventional technology, when configuring an MA control device that can access a wide address space, the DMA address register and transfer byte number register are No consideration is given to the fact that if the width becomes too large, incrementer and decrementer circuits with corresponding bit widths will be required.
CARRY
The purpose of the present invention is to solve problems when the calculation delay value becomes large (such as transmission time) and the counter operation becomes slow.
M
A: To provide a control device.

[Means for solving problems]

The above purpose is to create a selector circuit that divides the DMA address register and transfer byte number register into arithmetic units of fixed bit @, and selects the contents of one of these arithmetic units and inputs it to the intermenter and decrementer. This is achieved by adopting a method in which the increment and decrement operations are divided into individual operation units and executed.

[Effect]

The function of the selector circuit and the counting operation sequence are shown in the flowchart of FIG.

(The selector circuit selects the lowest operation unit of the DMA address register, and the increment operation circuit selects the lowest operation unit of the DMA address register.
Count and amplify the contents.

When CARRkJ is 1f, the count in the DMA address register is finished, and then the transfer byte number register counts in line 7 rx.If CARRY occurs, it is selected by the next higher arithmetic unit selector circuit, and then Content Z
The count is up. Judging CARRY again, below:
It continues counting up the higher-order operation units in order until no CARRY occurs (
The counting operation ends at this point, or when the highest level calculation unit is counted.

The counting of the Hyde number register can also be performed in the same manner as above, by simply replacing the counter with the countdown.

Regarding the counting operation of the DMA address register, FIG. 4 shows how register contents are updated.

By performing the operations explained above, the divided tv7
By using incrementer and decrementer circuits having a bit width of one h operation unit, it is possible to perform a count operation on a register having an arbitrary bit width.

Also, since the incrementer and decrementer circuits are small-scale circuits, the calculation delay value is also small, or
The counting operation speed can be designed to be fast. Therefore, although the present invention requires an extra count operation for nine times when a CARRY occurs, it is more advantageous than the prior art in terms of average operation speed.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
is a DMA address register, 2 is a transfer byte number register, 5 is a selector circuit that divides the contents of the above register into 1-byte wide calculation units and inputs it to the calculation circuit 4, 4 is a 1-byte wide incrementer/decrementer operation - circuit,
5 is a 1-byte wide slave register that holds the output of the above-mentioned operator circuit.

6 is a DMA sequence control unit that controls switching of the selector circuit 6, write timing control of the register group, and increment/decrement switching of the arithmetic circuit 4, and 7 is a DMA address register (c) capacity?
Next, the operation of this embodiment, which is a buffer circuit for outputting to the address bus, will be explained.

data r, DMA address register 1. The transfer byte number register 2 is initialized by the CPU via the υ data bus. When the DMA control device is activated, a DMA address is output to the address bus and a DMA cycle is executed. Next, after the DMA cycle is completed, the selector circuit 6 selects the lowest order of the DhlA address register 1. Select the arithmetic unit and enter the arithmetic circuit 4.Arithmetic circuit 4
acts as an incrementer and the slave register 5
The lowest calculation unit of the DMA address register is counted up. Here, the CARRY of the calculation circuit 4 is
The DMA sequence control unit 6 determines that CARR
When Y occurs 1f, the counting operation ends, and then the counting operation of the transfer byte number register starts. C.A.R.R.
If Y occurs, is selector circuit 3 the next higher calculation unit? The selection is made, and the counting circuit 4 performs a count-up. CARRY is determined again. If CARRY does not occur, the counting operation ends. If CARRY occurs, the higher-level performance unit is counted up. When the count up of the unit of operation is performed, the 10 count operation of the DMA address register is completed, and then the number of transferred bytes is counted and the counting operation of the dinuta 2 is started. , the operation is exactly the same as the DMA address register 10 count except that the increment function is switched to the decrement function.

When the series of counting operations is completed as described above, the DMA completion address is output to the address bus again, and the DMA completion address is outputted to the address bus again.
Cycles are executed, from then on, the DMA address registers 1 . While updating the contents of transfer byte number register 2, DMA cycles are performed, and when counting the highest operation unit of transfer byte number register 1, CARRY
If this occurs, the DMA control device t outputs an end count signal and ends the DM and 4M operation.

FIG. 2 is an example of a DMA control device according to the prior art. In the figure, the MA address register is shown.

2 is a transfer byte number register, 8 is an address increment circuit, 9 is a transfer byte number decrement circuit, 10 is a slave register that holds the address operation result, 11 is a slave register that holds the transfer byte number operation result, 6 is each A DMA sequence control section 7 controls the programming timing of the register group, and 7 is a buffer circuit that outputs to the DMA address Y address bus.

As can be seen by comparing FIG. 2 of the conventional example and FIG. 1 of the present embodiment, according to the present embodiment, the address increment circuit 8. Transfer byte count decrement circuit9. and slave registers 10, 11y, selector circuit 6. 1-byte width arithmetic circuit that serves as both an incrementer and decrementer 4. Since the slave register 5 can be replaced with a 1-byte width slave register 5, the number of elements can be reduced by about 15 compared to the conventional example, which is effective in simplifying the device.

In addition, by downsizing the arithmetic circuit from 6 bytes to 1 byte, it is possible to design the one-time counting operation speed to about double, which increases the average operation speed to about 1.8 times. It is possible to do this, and it is also effective in increasing the speed of the device.

〔Effect of the invention〕

As explained above, the present invention provides an incrementer circuit that is effective in the following points, regardless of the bit width of the DMA address register and transfer byte number register.

Since the decrementer circuit can be made into a small-scale circuit, it is effective in simplifying the device and reducing costs.Also, since the calculation delay value can be reduced, it is effective in increasing the speed of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a star counting method. 1...L) MA address register, 2... Transfer byte number register, 5... Selector circuit, 5... Slave register 2, 6... DMA sequence control unit, 7... Address buffer Circuit: 8: Address increment circuit; 9: Transfer byte number detarriment circuit. Figure 1 Figure 2 z

Claims (1)

[Claims] 1. DMA control consisting of a DMA address holding register, a transfer byte number holding register, an arithmetic circuit that increments or decrements the contents of the register, and a buffer circuit that outputs the output of the DMA address holding register to the address bus. In the device, DMA
Address holding register, transfer byte number holding register,
A DMA characterized in that it has a selector circuit that divides the data into arithmetic units of a certain bit width, selects one of the contents and inputs it to the arithmetic circuit, and an arithmetic circuit that increments or decrements the arithmetic unit. Control device.