JP2985201B2 - Microcomputer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to an instruction processing method for stack operation on an internal register.

[Conventional technology]

In recent years, the application fields of microcomputers are expanding more and more, including various OA equipment such as printers and disk drives, and automotive electrical equipment such as engine controls.
As these devices become more sophisticated, the amount of information to be processed by the microcomputer is increasing, and further enhancement of the performance of the microcomputer is desired.
On the other hand, in applications in which devices are incorporated in such fields, the size of devices themselves is continually being reduced, and the cost of such devices is continually reduced.

Such a microcomputer usually has internal registers called general-purpose registers, and executes various instructions such as data transfer between these internal registers or an external device such as a memory, and arithmetic and logic operations.

Among these instructions, a PUSH / POP post instruction is known as an instruction used particularly when the contents of a plurality of general-purpose registers are temporarily stored in an external memory. PUSH post
One instruction executes a process of stacking and storing the contents of a plurality of general-purpose registers specified by the post parameter in a stack area of an external memory specified by a stack pointer (hereinafter, referred to as SP) inside the microcomputer. The POP post instruction performs a process of returning a plurality of data stored in the stack area to the general-purpose register specified by the post parameter with one instruction.

FIG. 6 is a diagram showing an example of the instruction code configuration of the PUSH post instruction, and FIG. 7 is a diagram showing an example of the configuration of the general-purpose register GR. In the second byte of the instruction code, each bit has one-to-one correspondence with each of the eight general-purpose registers GR0 to GR7 in FIG. For example, if bits 0, 2, and 4 are 1, the general registers GR0, GR2, and GR4 are saved on the stack,
When only bit 7 is 1, the general-purpose register to be processed is
GR7 only.

FIG. 8 shows a flowchart of microprogram processing of a PUSH post instruction in a conventional microcomputer controlled by a microprogram, and its operation will be described. Here, in addition to the general-purpose registers and SP described above, the microcomputer includes internal temporary registers TA and TB and a shifter that are controlled by a microprogram in order to realize various data processing such as arithmetic and logic operations using ordinary instructions. I have.

First, in the first step 201, the second byte of the instruction code is stored in the internal temporary register TA, and in step 202, 7 is set as the register selection variable in the internal temporary register TB.
To be stored. Then, in step 203, the TA value is shifted to the left,
If the carry (hereinafter referred to as CY) shifted in step 204 is 1, the SP is decremented (step 205), GR7 is selected based on the TB value, and GR7 is added to the address indicated by SP.
Is transferred (step 206), the TB is decremented (step 207), and the process branches to step 203. Also,
If the carry CY in step 204 is 0, the stack operation is not performed, the TB is decremented (step 209), and then step 203 is executed again. As above, in step 208
By repeating until TB becomes 0, the saving processing of the general-purpose registers from GR7 to GR0 specified by the post data is realized.

The PUSH / POP post instruction temporarily saves the contents of general-purpose registers so that the contents of general-purpose registers are not affected when the flow of a program such as a subroutine call or interrupt processing changes temporarily. Used for purpose.

[Problems to be solved by the invention]

In the above-described conventional instruction processing, a predetermined general-purpose register is selected and saved on the stack by searching for 1 in each bit of the post data by microprogram processing. Therefore, the execution time of the instruction is long because the processing is complicated despite the short word length of the instruction. Further, in the case of a PUSH post instruction, for example, even if only bit 0 is 1, it is necessary to shift post data from bit 7 to bit 1 and decrement a register selection variable. And it was very inefficient. In particular, in interrupt processing that requires high-speed processing, this PUSH / POP post
There is a case where an instruction execution time of an instruction causes an overhead, which may cause a problem, and a faster instruction processing method has been desired.

In order to speed up the processing, dedicated hardware for detecting one bit of post data and selecting the corresponding general-purpose register is provided, and the contents of the specified general-purpose register are saved on the stack by microprogram processing. After that, a method is known in which the bit is automatically reset to 0 so that the processing is performed with the minimum necessary number of execution clocks. However, such a method using dedicated hardware is complicated and large in scale, although the hardware cannot be used for purposes other than post data discrimination, and it is suitable as a method adopted by inexpensive microcomputers. Not.

An object of the present invention is to improve such conventional problems,
An object of the present invention is to provide a microcomputer capable of realizing high-speed PUSH / POP post instruction processing with minimum hardware.

[Means for solving the problem]

The configuration of the microcomputer of the present invention includes a data memory for storing processing data, a program memory for storing a program to be executed, a program counter for sequentially generating addresses of the program memory, and an instruction read from the program memory. An instruction register for storing codes, a micro-ROM for storing micro-programs for various instruction processing, and a micro-address generation unit for inputting each output of the micro-ROM and the instruction register and generating an address of the micro-ROM, An instruction execution control unit that controls the sequence of the microprogram and outputs an operation instruction signal from the microROM; a plurality of internal registers; a stack pointer that specifies an address of a stack area of the data memory; According to the traffic light, A data processing unit including a logical operation unit that performs an instruction process for executing data transfer between one or more of the internal registers and a memory specified by the stack pointer with a single instruction. RO
In M, a field for specifying the internal register using the operation specifying signal as address information for controlling the data processing unit, a field for specifying an address of a step next to a step during execution of the microprogram, And a field for specifying a branch condition.

According to the present invention, a gate circuit is provided between the instruction register and the micro address generation unit to determine that all the upper bits or lower bits of the instruction code of the instruction register are “0”, The output can reduce the number of inputs to the microaddress generation unit. Further, the field for specifying the branch condition of the microprogram in the micro ROM may include a bit field for specifying each of a plurality of internal registers to be transferred as the branch condition.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an internal configuration of a microcomputer according to one embodiment of the present invention. This embodiment includes an instruction execution control unit 1, a data processing unit 2, a program memory 5, a data memory 6, and a data bus 3 connecting these.

The instruction execution control unit 1 performs sequence control for sequentially executing a predetermined microprogram based on the instruction code read from the data bus 3, and outputs an operation designation signal 4 to the data processing unit 2. The data processing unit 2 performs data transfer,
Each instruction processing such as arithmetic logic operation is performed. The data bus 3 is connected to a program memory 5 for storing a program executed by the microcomputer and a data memory 6 for storing processing data.

The instruction execution control unit 1 includes a program counter PC10 for sequentially generating addresses of the program memory 5 as the instruction is executed.
And an 8-bit instruction register IR11 for storing an instruction code read from the program memory 5, a micro ROM 12 for storing a micro program for each instruction, and an output of the IR 11 and the micro ROM 12 to generate an address of the micro ROM 12. And a micro address generation unit 13.

FIG. 2 is a format diagram of the output of the micro ROM 12 of FIG. This output includes an operation designating field for designating the state of the operation designating signal 4, a next address designating field for designating the address of the micro ROM 12 next to the currently executing step in the microprogram in one instruction, And a branch designation field for designating the branch condition.

In addition, the micro address generation unit 13 in FIG. 1 selects the output of IR11 at the instruction execution start timing, and
Generates the start address of the microprogram of the corresponding instruction based on the value of. At the timing after the first step, the next address designation field is used for the address of the micro ROM 12 in the micro address generation unit 13, and the address of the next step is generated. The branch specification field is used for specifying an address modification condition in the micro address generation unit 13. As described above, the contents of the micro ROM 12 in each step are sequentially read, and the data processing unit 2 performs a series of predetermined instruction operations according to the state of the operation designation field.

The data processing unit 2 includes a general-purpose register 20 including eight registers GR0 to GR7, an arithmetic and logic operation unit ALU21,
SP22 for designating the start address of the stack area of the data memory 6.

Next, among general-purpose registers 20 from GR0 to GR7, post
The instruction operation of the PUSH post instruction for saving a plurality of registers specified by data to the stack area of the data memory 6 will be described with reference to the microprogram processing flowchart of FIG. Here, the configuration of the post data is the same as the configuration of FIG.

First, in step 101, the second byte of the instruction code is
, And the content of IR11 is designated as the address modification condition by the branch designation field, and the process branches (step 102). I
If the R11 value is 00000001B (B is a binary number), SP22 is decremented (step 103), and GR0 is added to the address indicated by SP22.
Is transferred (step 104), and the instruction is terminated. If the IR11 value is 00000011B in step 102, the SP
22 is decremented (step 105) and the contents of GR1 are transferred (step 106), and then SP22 is decremented (step 103) and the contents of GR0 are transferred (step 104). Further, if the IR11 value is 11111111B, all contents of GR7 to GR0 are transferred while decrementing SP22. Similarly,
If the IR11 value is 00000000B, the instruction is immediately terminated without performing the transfer. The other values of IR11 are similarly transferred.

In this way, according to the contents of IR11, microprogram processing for saving only the designated combination of general-purpose registers in the stack area is prepared, and the processing is executed by branching to each.

Here, there are 256 combinations of IR11, and microprogram steps for all combinations of general-purpose registers are necessary.However, since microROM12 is usually composed of a mask ROM, the degree of device integration is lower than that of general random logic. Since it is extremely expensive and does not require any dedicated hardware, a minimum hardware configuration is possible. Also,
The POP post instruction can be implemented in a similar manner.

FIG. 4 is a block diagram showing the internal configuration of a microcomputer according to a second embodiment of the present invention. In this embodiment, the branch of the microprogram is divided into upper and lower 4 bits of post data. It is something to do. This embodiment is different from the first embodiment in that gate circuits 14 and 15 are inserted between the IR 11 and the microaddress generation unit 13.

The instruction execution control unit 1 decodes the same program counters PC10, IR11, micro ROM 12, and micro address generation unit 13 as in the first embodiment, and decodes the upper 4 bits and lower 4 bits of IR11, and sets all 4 bits to 0. Is detected,
And gate circuits 14 and 15 for outputting detection signals 16 and 17 to the microaddress generation unit 13 as address modification conditions. If the above 4 bits are 0000B, the upper zero detection signal 16
Becomes the logical value “1”. When the lower 4 bits are 0000B, the lower zero detection signal 17 has a logical value "1". Here, the basic operation of the hardware related to the sequence control of the instruction execution control unit 1 is the same as that of the first embodiment, and the description is omitted. Also, the data processing unit 2,
The data bus 3, the operation designation signal 4, the program memory 5, and the data memory 6 are the same as in the first embodiment.

Next, the instruction operation of the PUSH post instruction of the second embodiment will be described with reference to the microprogram processing flowchart of FIG. Here, the structure of post data is the sixth
The configuration is the same as that shown in FIG.

First, in step 101, the second byte of the instruction code is IR11
The state of the upper zero detection signal 16 and the lower zero detection signal 17 is designated by the branch designation field as an address modification condition, and branching is performed (step 102). If the high-order zero signal 16 has the logical value "1", the branch specifying field is used to specify the contents of the high-order 4 bits of IR11 as the address modification condition and branch (step 111). If the IR11 value is 0001B, SP22 is decremented (step 103), and the contents of GR4 are transferred to the address indicated by SP22 (step 104).
If the IR11 value is 0011B in step 103, SP22 decrements (step 105), and transfers the contents of GR5 (step 105).
106) After that, decrement SP22 (step 103), GR4
Is transferred (step 104). Similarly, if the RI11 value is 1
If it is 111B, transfer all the contents of GR7 to GR4 while decrementing SP22.

Next, if the lower zero signal 17 is a logical value "1",
The contents of the lower 4 bits of IR11 are designated as address modification conditions, and branching is performed (step 113). If IR11 value is 0001B, SP
22 is decremented (step 114), and the contents of GR0 are transferred to the address indicated by SP22 (step 115). Also,
If the IR11 value is 0011B in step 113, SP22 is decremented (step 116) and the contents of GR1 are transferred (step 117), and then SP22 is decremented (step 114) and the contents of GR0 are transferred (step 115). Similarly, if the IR11 value is 1111B, all contents of GR3 to GR0 are transferred while decrementing SP22.

In step 101, if the upper zero signal 16 is a logical value "0" and the lower zero signal 17 is a logical value "1", the flow directly branches to step 113, and the processing for GR7 to GR4 is not performed. If the high-order zero signal 16 is a logical value “1” and the low-order zero signal 17 is a logical value “0”, only the processing from GR7 to GR7 is executed, and the instruction is terminated (step 112). Similarly, if both the high-order zero signal 16 and the low-order zero signal 17 have the logical value "0" in step 102, the instruction is immediately terminated. IR11
The same applies to other values of.

Thus, IR11 is divided into upper and lower 4 bits,
According to the contents, microprogram processing for saving only the combination of the designated four types of general-purpose registers in the stack area is prepared, and the processing is executed by branching to each of them. Here, there are 32 combinations of IR11 including the upper 4 bits and lower 4 bits, and the gate circuit 1
4 and 15 can also be normal NOR gates and can be realized with minimum hardware.

In addition, the POP post instruction can be similarly implemented using this hardware as it is.

〔The invention's effect〕

As described above, according to the method of the present invention, PUSH / P
The OP post instruction can be processed by saving the designated general-purpose register to the stack area by branching the microprogram based on the post data. Because it does not require complicated dedicated hardware for searching the bits of
There is an effect that a high-speed and inexpensive microcomputer can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the microcomputer of the present invention, FIG. 2 is a diagram showing an output format of the micro ROM 12 of FIG. 1, and FIG. 3 is a flowchart of the micro program processing of FIG. FIG. 4 is a block diagram of a microcomputer according to a second embodiment of the present invention, FIG. 5 is a flowchart of the microprogram processing of FIG. 4, and FIG. 6 is a configuration diagram of instruction codes of a general PUSH post instruction. FIG. 7 is a block diagram of a general-purpose register used in FIG. 6, and FIG.
FIG. 1 is a flowchart of an example of a microprogram process in a conventional microcomputer. 1 ... instruction execution control unit, 2 ... data processing unit, 3 ... data bus, 4 ... operation designation signal, 5 ... program memory, 6 ... data memory, 10 ... program counter (PC), 11 …… Instruction register (IR), 12 …… Micro RO
M, 13: Micro address generation unit, 14, 15: Gate circuit, 16: Upper zero detection signal, 17: Lower zero detection signal, 20: General purpose register, 21: Arithmetic logic operation unit, (AL
U), 22 ... Stack pointer (SP), 101-115, 201-2
08 …… Processing steps.

Claims (3)

(57) [Claims] 1. A data memory for storing processing data, a program memory for storing a program to be executed, a program counter for sequentially generating addresses of the program memory, and an instruction code read from the program memory. An instruction register, a micro-ROM for storing micro-programs for processing various instructions, and a micro-address generation unit for inputting outputs of the micro-ROM and the instruction register and generating an address of the micro-ROM; An instruction execution control unit that performs sequence control and outputs an operation instruction signal from the micro ROM, a plurality of internal registers, a stack pointer that specifies an address of a stack area of the data memory, and a small number according to the operation instruction signal. And at least one of the internal cash registers And a data processing unit including a logic operation unit which performs instruction processing to execute data transfer in a single instruction with the memory specified data and by the stack pointer, the micro RO
M has a field for specifying the internal register using the operation specifying signal as address information for controlling the data processing unit, a field for specifying an address of a step next to a step during execution of the microprogram, A field for designating a branch condition. 2. A gate circuit between an instruction register and a micro-address generation unit, the gate circuit determining whether the upper bit or the lower bit of the instruction code of the instruction register is all "0". 2. The microcomputer according to claim 1, wherein the number of inputs to said micro address generation unit is reduced by a judgment output. 3. The microcomputer according to claim 1, wherein the field for specifying the microprogram branch condition in the microROM includes a bit field for specifying each of a plurality of internal registers to be transferred as the branch condition.