JPS6113345A - Processor of tagged data - Google Patents

Abstract

PURPOSE:To improve the processing speed of tagged data, by connecting a mechanism which changes tags in data in accordance with tag value designating inputs with an operator. CONSTITUTION:An arithmetic control section designates one or two sets of data from a register file 1 composed of plural data holding registers and supplies the designated data to the input terminal 20 or 21 of an operator 2 through buses 24 and 25 and causes the operator 2 to execute prescribed operation on the data. After the operation, the control section stores the operated data in one register of the register file 1 from the output terminal 22 of the operator 2 through a bus 26. The input terminals 20 and 21 and output terminal 22 of the operator 2 are respectively connected with tag changing mechanisms 30-32. The tag changing mechanisms 30-32 can change tags constituted by means of specific bit position in each data on passing data. Necessity of tag change, tag value to be changed and set, etc., are controlled by signals inputted from control lines 34-36.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a data processing device that processes tagged data.

As a data processing device that processes data with a complex structure, a tag is attached to the data to indicate its type.For example, when executing an operation, specific information is specified by the value of the tag attached to the operand data. There is a method in which control is performed, such as determining the calculation method.

In such a data processing device, it is necessary to change tags in data during the calculation process. The present invention relates to improvements in such tag change control.

[Problems to be solved by the prior art and the invention] For example, if the data consists of an 8-bit tag and 24-bit actual data, and the tag representing the integer type is °1, then the integer "5" and The data of the integer "7" has the following structure in hexadecimal representation.

Integer '5' 01000005 Integer '7' 01000007 Therefore, if you simply add the integer 5 and the integer 7 using the data in the above configuration, you will get 0200000C, which is non-integer data with tag 2. I end up.

Conventionally, for this purpose, an integer arithmetic microprogram or the like would set the operand data tag to °0' before the operation.
In the above example, '00000005' and 'ooooooo.

7". When we perform addition with this data, we get '
oooooooc'', so this tag is changed to ``1'' and the addition process ends.

Therefore, a total of three tag change processes are required before and after the target calculation, which poses a problem of slowing down the actual execution speed of the calculation.

[Means for solving problems]

An object of the present invention is to provide an improved data processing device that can eliminate the above problems.

This object is achieved by the present invention, in which, when processing data in a format in which a tag indicating the data type is retained in the data, a mechanism for changing the tag in the data by inputting a tag value is connected to an arithmetic unit. This is accomplished by a tagged data processing device.

[Effect]

That is, as in the past, the tag value to be changed is determined based on the instruction to be executed and the type of operand data.

A mechanism is provided to change the tag in the data using the tag value designation generated based on this determination as input, and this is connected to the arithmetic unit, so there is no need to spend any special steps in the microprogram etc. to change the tag. Tag changes are performed without any changes.

〔Example〕

FIG. 1 is a block diagram of an arithmetic control section of a processing device according to an embodiment of the present invention.

As is well known, the arithmetic control section specifies one or two sets of data from a register file 1 consisting of registers that hold a plurality of data, and supplies them to the input terminal 20 or 21 of the arithmetic unit 2 via a bus 24,25. , has a function of executing a predetermined operation on the data by the arithmetic unit 2 and storing it in a register in the register file 1 from the output terminal 22 via the bus 26.

According to the invention, a tag change mechanism 30.31.32 is connected to the input terminal 20.21 and the output terminal 22 of the arithmetic unit 2.

In this configuration, the above-mentioned operand data is made to pass through the tag change mechanism 30, 31 or 32 before and after passing through the arithmetic unit 2.

The tag modification mechanisms 30.31 and 32 are capable of modifying the tag for the data passing through, which is constituted by a particular bit position within each data.

Control line 34 indicates whether changes are necessary, tag values that should be changed and set, etc.
．． It is controlled by signals input from 35 and 36.

It is assumed that these signals are separately determined by conventional methods based on the instruction to be executed and the type of data to be operated on, and are supplied from the control unit 37.

FIG. 2 shows an example of the configuration of the tag change mechanisms 30, 31, and 32. For example, data consisting of 32 bits is input from the signal line 40, from which the 24-bit actual data part 41 excluding the 8-bit tag part is passed through as is, and the tag part 42 is changed if necessary. and output to the signal line 43.

For example, if the mechanism in FIG. 2 is the tag changing mechanism 32, the input signal line 40 is connected to the output terminal 22 in FIG.
Connect to 6.

In this example, control lines 44 and 45 are connected to the control lines 44 and 45 of FIG. I
l&! 36 details are shown.

A 1-bit signal that specifies whether or not to change the tag is input to the control line 44, and this signal controls the gate circuit 46 to either pass the input tag value on the signal line 42 as is or to change the tag value on the signal line 47. Change the tag value to .

The signal line 45 is a 4-bit input, for example, which specifies a new tag value when changing the tag value.

The signal on the signal line 45 becomes, for example, an address input to a tag memory 48 stored in a read-only storage device, and is used to read a specified tag value from the tag memory 48.

For example, the tag memory 48 stores 16 tag values of 8 bits each.
The type of tag value stored and specified on the signal line 45 can be read out to the signal line 47 and outputted via the gate circuit 46 as described above.

〔Effect of the invention〕

As is clear from the above description, the present invention has a remarkable industrial effect in that the tags of the data to be processed can be operated at high speed before and after processing the tagged data, thereby improving the performance of the processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a tag changing mechanism. In the figure, 2 is a register file, 2 is an arithmetic unit, 30, 31, 32 is a tag change mechanism, 37 is a control unit, 46 is a gate circuit, and 48 is a tag memory. Agent Patent Attorney Calibration Koshibu Part 1 Figure

Claims (1)

[Claims] A tag characterized in that, when processing data in a format in which a tag indicating the type of data is held in the data, a mechanism for changing the tag in the data by inputting a tag value specification is connected to an arithmetic unit. attached data processing equipment.