JPS63223833A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To improve the processing efficiency at a low cost for an arithmetic unit by excluding the partial bits (tag part) of the parallel input data out of the arithmetic subject and then replacing the tag part excluded previously with a part of the output data. CONSTITUTION:The parallel input stored in the input registers 1a and 1b undergo the arithmetic processing through an arithmetic part 2 according to a command signal 6a stored in an arithmetic control register 6. In this case, all bits of the input data are defined as the arithmetic processing subjects for execution of arithmetic as long as the contents of a command signal 8a of an invalid control register 8 are equal to '0'. The arithmetic result is outputted as it is to an output register 4. While the partial bits (tag part) of the input data are excluded for execution of arithmetic by a designation signal 7a of a tag width designating register 7 when the signal 8a is equal to '1'. Then a hybrid processing circuit 3 replaces the tag part excluded previously with a part of the data on the arithmetic result of the part 2 and outputs it.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an arithmetic device installed in a computer or the like.

"Prior Art" Conventionally, in arithmetic units installed in computers and the like, the central processing unit (CPU) usually operates to process parallel data of a specific width. for example,
8 bits, 16 bits, 32 bits, etc., depending on the calculation speed and data transfer capacity of the central processing unit (CPLI).
The number of bits also varies.

By the way, in recent computer language processing systems, tags are used to determine the type of data, for example, whether the data is numerical data or data indicating other special types of content such as pointers. It is well known that data is captured and processed.

When implementing such a language processing system, the parallel data is divided into a tag section and a data section before arithmetic processing by a central processing unit (CPU). In this case, the parallel data is divided immediately before arithmetic processing, and after only the data is subjected to arithmetic processing, the tag part and the data part after the arithmetic processing are combined again.

``Problems to be solved by the invention'' Now, in order to divide and combine data like this,
Requires special software for its processing. For example, a special microprogram or the like is created for this purpose to proceed with this process.

However, such processing reduces the efficiency of calculations, reduces the processing power of the computer, and becomes an obstacle to increasing the calculation speed.

In addition, there are dedicated systems that completely separate the data part and tag part to increase speed, but such systems can also be used for general processing that does not use tags.
When this method is implemented, the tag section becomes unnecessary, the bus structure becomes specialized, and the system cost increases.

The present invention has been made with attention to the above points, and it is an object of the present invention to provide an arithmetic device that enables efficient processing of a language processing system at low cost, and that also aims to reduce cost. It is.

"Means for Solving the Problem" The arithmetic device of the present invention includes an arithmetic unit that performs certain arithmetic processing on parallel input data, and a command for excluding some bits of the parallel input data from the object of the arithmetic operation. an arithmetic processing specifying section that outputs a signal to the arithmetic section; and an arithmetic processing specifying section that receives the command signal and selects some bits of the parallel output data output from the arithmetic section as a result of the arithmetic processing in accordance with the contents of the instruction. , and a mixing processing circuit that replaces some bits of the parallel input data excluded from the calculation target.

"Operation" When the above-described arithmetic device receives a command signal in the arithmetic section, it excludes some bits (tag section) of the received parallel input data from the object of the arithmetic operation. However, the arithmetic unit outputs parallel data having the same number of bits as the input data together with the arithmetic result.

The mixing processing circuit then operates to replace the previously excluded tag portion with a portion of its output data.

As a result, high-speed processing can be achieved using the parallel cheater and hardware used in the language processing system.

In addition, even in processing that does not use tags, by not inputting command signals, all input data is subject to calculations, so there is no need to separate the tag part and data part with special memory, increasing versatility. It is possible to realize a low-cost system that can be maintained.

Embodiment FIG. 1 is a block diagram showing an embodiment of an arithmetic device of the present invention.

This device includes an arithmetic unit 2 that processes two parallel input data stored in two input registers 1a and 1b, and a mixing processing circuit 3 that processes output data of this arithmetic unit 2.
and an output register 4 for storing the processing results. Furthermore, in order to control the operation of each of these parts,
An arithmetic processing designation section 5 is provided. A predetermined command signal is sent from the arithmetic processing specifying section 5 to the arithmetic control register 6,
It is output and stored in the tag width designation register 7 and the invalidation control register 8.

The calculation control register 6 contains the calculation contents of the calculation unit 2, for example,
A command signal indicating the distinction between addition, subtraction, multiplication, and division is stored. The tag width designation register 7 stores a command signal indicating the tag width and its position in the parallel input data stored in the input register la.

The invalidation control register 8 stores a command signal indicating whether or not the arithmetic processing in the arithmetic unit 2 and the signal processing in the mixing processing circuit 3 should be executed while ignoring the tag width.

The calculation unit 2 is connected to receive command signals stored in the calculation control register 6, the tag width designation register 7, and the invalidation control register 8. On the other hand, in the mixing processing circuit 3,
It is connected so that the command signals stored in the tag width designation register 7 and the invalidation control register 8 are input.

Note that for convenience of illustration, the number of signal lines is shown as 4-bit parallel processing, but in this embodiment, all input data is 16-bit parallel data, and the arithmetic unit 2 and The output data of the mixing processing circuit 3 is also 16
Bit parallel data. The parallel input data stored in the input register 1a is wired so as to be input to both the arithmetic unit 2 and the mixing processing circuit 3.

FIG. 2 shows a more detailed block diagram of the mixing processing circuit 3 shown in FIG. 1.

First, this mixing processing circuit 3 is provided with 16 replacement circuits 10, matching the number of input parallel data. Each permutation circuit 10 consists of three AND gates 11.1
2.13, an inverter 14, and an OR gate 15.

Each replacement circuit 10 has 1 output from the calculation section 2 (FIG. 1).
In addition to bit data 10a, data 10b is directly input from input register la (FIG. 1). Data 10a output from the arithmetic unit 2 is input to one terminal of the AND gate 13. Also, input register 1
The data 10b directly input from a is input to the AND gate 12.
input to one terminal of Furthermore, the command signal 7a input from the tag width designation register 7 is input to one terminal of the AND gate 11, and the command signal 8a input from the invalidation control register 8 is connected to the other terminal of the AND gate 11. has been done. Note that the command signal 8a output from the invalidation control register 8 is common to each replacement circuit 10. On the other hand, the tag width control register 7 outputs a parallel 16-bit command signal 7a, each bit of which outputs a corresponding replacement circuit 1.
It is wired to input 0.

In the permutation circuit 10, the output signal of the AND gate 11 is input to the inverter 14 and the other terminal of the AND gate 12. The output signal of the inverter 14 is
It is input to the other terminal of AND gate 13. The output signal of the AND gate 13 and the output signal of the AND gate 12 are both connected to be input to an OR gate 15.

A total of 16 bits of parallel data is output from the OR gates 15 of the 16 replacement circuits 10 and stored in the output register 4.

The arithmetic device of the present invention having the above configuration operates as follows.

Note that specific examples of parallel data processed by this calculation unit 2 are illustrated in FIGS. 3 and 4.

First, in FIG. 1, the calculation section 2 has an input register 1a.
The parallel input data stored in 1b and 1b is subjected to arithmetic processing according to the command signal 6a stored in the arithmetic control register 6.

At this time, if the content of the command signal 8a of the invalidation control register 8 is off ("0"), the computation is performed using all bits of the input data as objects of the computation process. That is, the third
As shown in the figure, the data in input register 1a and 16. The calculation result 20 is obtained by adding the data. The calculation result 20 is output to the mixing processing circuit 3. On the other hand, the carry bit 20a is determined by carrying the most significant bit of the operation result 20. This carry pin 20a is not directly used in the illustrated circuit of the device of the present invention, but is used in another circuit not illustrated. Next, the mixing processing circuit 3 in FIG.
Regardless of the contents of the command signal 7a of the tag width designation register 7, the calculation result of
Output to.

On the other hand, the command signal 8a of the invalid control register 8 is turned on (“1”
”), in FIG. 1, the calculation unit 2 refers to the command signal 7a of the tag width designation register 7, and according to its contents, performs calculations on the tag of the predetermined number of bits, excluding this. Execute.

For example, as shown in FIG. 4, it is assumed that the upper two bits of each data are the tag part 21.

In this case, the content of the parallel 16-bit command signal 7a of the tag width designation register 7 is such that its upper two bits are on and the other 14 bits are off. When three ON signals among the command signals 7a of the tag width designation register 7 are input to the AND gates 11 of the upper two replacement circuits 10 of the mixing processing circuit 3, the command signal 8a of the invalidation control register 8 is also turned ON. Therefore, the output signal of the AND gate 11 is turned on. This output signal closes the AND gate 13, which has been open to pass the output data 10a of the calculation section 2, and opens the AND gate 12. As a result, the data 10b input from the input register 1a passes through the analog gate 12 and the OR gate 15 to the output register 4.
is output to.

That is, the 2-bit tag is input to the mixing processing circuit 3 without passing through the arithmetic unit 2, passes therethrough as it is, and is output to the output register 4. In the other replacement circuit 10 to which the remaining 14 bits of the command signal 7a of the tag width designation register 7 that are turned off are input, the AND gate 11 remains closed, and the output signal thereof opens the AND gate 13, and the AND gate 13 is opened. 12 closes. As a result, the data 10a output from the arithmetic unit 2 is output to the output register 4 through the AND gate 13 and the OR gate 15.

In this way, the parallel data output to the output register 4 has its upper two bits replaced with the output signal of the arithmetic unit 2 and the tag. Note that, as shown in FIG.
When the most significant bit of the lower 14 bits excluding the tag part 21 is carried over, the result is held as a carry bit 20a'.

"Modification" The arithmetic device of the present invention is not limited to the above embodiment. The position of the tag part may be anywhere in the parallel input data, and it does not matter how many bits it has.

Furthermore, in processing that does not use the tag section, it is also possible to input no command signal and use all input data as the object of calculation in the arithmetic section.

"Effects of the Invention" According to the arithmetic device of the present invention described above, some bits (tag part) of the received parallel input data are excluded from the calculation target, and then the tag part that was excluded in advance is added to the output data. Processing such as replacing a part of
Since it is realized by hardware, it is possible to speed up the processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the arithmetic device of the present invention;
FIG. 2 is a block diagram illustrating the details of the mixing processing circuit of the arithmetic unit, and FIGS. 3 and 4 are explanatory diagrams illustrating the operation of the arithmetic unit. 1a, 1b...Input register, 2...Arithmetic unit, 3...Mixing processing circuit, 4...Output register, 5...Arithmetic processing Specified part. Applicant: Fuji Xerox Co., Ltd. Agent

Claims (1)

[Claims] an arithmetic unit that performs certain arithmetic processing on parallel input data; an arithmetic processing designation unit that outputs a command signal to the arithmetic unit to exclude some bits of the parallel input data from calculation targets; A command signal is received, and in accordance with the contents of the command, some bits of the parallel output data output from the arithmetic unit as a result of arithmetic processing are replaced with some bits of the parallel input data excluded from the arithmetic target. An arithmetic device comprising: a replacing mixing processing circuit.