JPH07182266A - Interface device - Google Patents

Abstract

PURPOSE:To execute receiving processing in data transfer for receiving data by triggering a strobe signal without applying load on a receiving side controller. CONSTITUTION:At the time of receiving data and a strobe signal from a master device, a busy signal generator 108 generates a busy signal making succeeding reception inpossible to be performed by triggering the reception by the strobe and the busy signal is returned to the master device. A timer counter 101 receiving the strobe signal counts clocks and outputs its count value to comparators 105 to 107. Respective comparators 105 to 107 compare the output value from the counter 101 with respective values set up in registers 102 to 104, and when both the values coincide with each other, respectively output corresponding signals. At this time data latched in a data latch 120 are inputted to an internal CPU or the like, and when a flag reset signal is supplied to a reception disabling flag generator 121, the states of the busy signal and an ACK signal are changed in accordance with the output timing of respective comparators 105 to 107 to prepare succeeding data reception.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an interface device,
Specifically, it relates to an interface device for receiving data from a host device such as a host computer.

[0002]

2. Description of the Related Art Conventionally, between a host device such as a host computer and a printing device below it, the host device monitors the status signal of the printing device. Then, when the print reception is possible, the data is output and a pulse signal called a strobe signal is output.

In the interface section on the printing apparatus side, the reception of data is detected by this strobe signal,
A signal to that effect (in most cases, an interrupt signal) is output to the control processor of the device to notify the reception of data. The control processor receives this signal and outputs a status signal from the interface to the host computer by handshaking.

[0004]

However, in the above-mentioned conventional example, the processing of the processor must be interrupted every time data is received, and the handshake processing must be performed.
This is a factor that reduces the data processing speed of recent peripheral devices that require high-speed data processing. In addition, when the processor performs handshake, there is a limit in response speed and operation speed, and there is a drawback that the data transfer speed cannot be increased accordingly.

[0005]

The present invention has been made in view of the above problems, and does not burden the control device on the receiving side with the receiving process in the data transfer for receiving data by using the strobe signal as a trigger. It is intended to provide an interface device that makes it possible to do.

In order to solve this problem, the interface device of the present invention has the following structure. That is,
An interface device for receiving blackboard data transferred from a host device by using a strobe signal as a trigger, and timer means for starting timekeeping based on the strobe signal, and one or more returned to the host device. Storage means for storing the timing of the change of the status signal,
And a changing means for changing the level of the corresponding status signal when the time stored in the storage means is reached based on the time value measured by the timer means.

An interface device of another invention has the following configuration. That is, an interface device for receiving data transferred from a host device by using a strobe signal as a trigger, and a plurality of latch means for latching a unit of data sent in one data transfer; Counting the number of times the signal is received, selecting one of the latch means based on the count value and latching the received data, timer means for starting time counting based on the strobe signal, and the host device Storage means for storing the change timing of one or more status signals to be returned to, and based on the time value measured by the timer means, when the time stored in the storage means comes, the corresponding status signal The counting means counts strobe signals corresponding to the number of changing means and the latch means for changing the level, and If the processing unit is not carried uptake data latched in said latch means, and a stop means for stopping the counting of the timer means.

[0008]

In the structure of the present invention, for example, in the first invention, when the strobe signal is received, the clocking is started at that time and the status signal returned to the host device is changed based on the clocked value.

[0009]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

In the embodiment, an example will be described in which the printer is adapted and the data exchange with the host computer is adapted to an interface (hereinafter referred to as "Centro interface") specified by Centronics Co., USA.

FIG. 1 is a block diagram of the Centro interface unit in the embodiment. In the figure, 10
A timer counter 1 is activated by a strobe signal (a low-level pulse signal output when the host computer sends data), counts by a clock signal, and outputs a count value. 102 is a register for storing the timing of resetting the BUSY signal which is one of the handshake signals, 103 is a register for storing the timing of setting an ACK signal (negative logic signal, the same applies below), 104 is a timing of resetting the ACK signal Is a register for storing.

Reference numeral 105 denotes a comparator, which is a timer counter 1
The count value output from 01 is compared with the value set in the register 102, and when both values match, a match signal is output. Similarly, 106 and 107 are also comparators, which compare the values set in the registers 103 and 104 with the output values of the timer 101, and output a coincidence signal when they coincide.

Numeral 108 indicates BU upon receiving the strobe signal.
BU is set when the SY signal is set and the reset signal is input.
A BUSY signal generator (composed of flip-flops) for resetting the SY signal, 109 sets an ACK signal when a set signal is input, and resets an ACK signal when a reset signal is input (Composed of flip-flops), 110 is a comparator 105
Are flip-flops set by the coincidence signal generated by the same, 111, 112 are flip-flops similarly set by the coincidence signals output by the comparators 106, 107, 113, 114, 115 are AND gates, 116 is an OR gate, 117 Is an AND gate, 118 is an inverter, 119 is an AND gate, 120 is a data latch that latches input data by a strobe signal, 121 is a reception not possible flag generator, which is set by the strobe, and a CPU (not shown) in the printing apparatus Data latch 1
It is reset by the flag reset signal output after reading the data latched in 20. Although not shown, when the host computer outputs data and outputs a strobe signal, a signal to that effect is output to the CPU or the like of the printing apparatus.

Next, the operation of the interface section will be described with reference to the timing chart shown in FIG.

In the figure, period A corresponds to the BUSY reset count value set in the register 102, period B is the ACK set count value set in the register 103, and period C is the ACK reset set in the register 104. Corresponds to the count value of. Further, T1 is the timing when the strobe is input and the timer counter 101 starts counting, T2 is the timing when the timer counter 101 continues counting and the count value coincides with the count value of the ACK set in the period B, and T3 is the same in the period A. BUSY
Similarly, T4 is a timing that coincides with the reset count value and T4 is a timing that coincides with the ACK reset count value of the period C.

Needless to say, the description will be as follows in comparison with the configuration of FIG.

When data is output from a higher-level device such as a host computer and a strobe signal is output to instruct the lower-level device (printing device) to transfer data, the strobe triggers to output a BUSY signal. Disable data transmission for the time being. At this time, the timer counter 101 starts counting the clock CLK used inside the device and continues to output it to the comparators 105 to 107.

Here, the processing when the CPU or the like inside the printing apparatus reads the data latched in the data latch 120 and outputs the flag reset signal to the unreceivable flag generator 121 is as follows.

Since the timing of the signal bypassed by the Centro interface is substantially as shown in FIG. 2, the coincidence signal is first output from the comparator 106 when the period B elapses. At this time, the unreceivable flag generator 121 has been reset by the CPU or the like, and the output signal thereof is low, that is, the output of the inverter 118 is high, so that the AND gate 113 to.
All 115 are open. Therefore, when the coincidence signal is output from the comparator 106, the flip-flop 111 is set and the signal is supplied to the ACK signal generator 109 via the AND gate 114. As a result, the signal ACK (negative logic) indicating that the strobe signal has been successfully received is output. Next, in the same manner, the comparator 105 outputs a coincidence signal when the period A has elapsed and resets the BUSY signal (R
EADY state). Then, when the period C has elapsed, the comparator 107 outputs the coincidence signal, so that A
The CK signal will be reset (logic high).

In the above example, the CPU or the like inside the apparatus fetches the received data and outputs the flag reset signal within a predetermined period. FIG. 3 is a timing chart when the fetching or the output of the flag reset signal is delayed.

Note that A to C in FIG. 3 are the same periods as A to C in FIG. However, the broken line portion in FIG. 3 indicates a period during which the timer counter 101 stops counting the CLK, as described below, and the period of that portion is not taken into consideration.

In the figure, U1 is the timing when the strobe is input and the timer counter 101 starts counting, and U2 is the timing when the timer counter 101 continues counting and the count value coincides with the count value of the ACK set in the period B. is there. If the CPU does not output the reset signal for the nude, the timing U3
At the time point when the period C has passed, the output signal of the unreceivable flag is output to the timer counter 101, and the timer counter 101 stops counting the CLK.

During this period, the unreceivable flag generator 121
Since the signal of logic high is output, as a result, B
The USY signal continues to be output and the ACK signal is not output.

Thus, this state continues until the CPU inside the apparatus fetches the latched data and outputs the flag reset signal, and the timer counter 101 outputs the flag reset signal until the timer counter 101 outputs the clock CLK.
Restart the clock. As a result, the timings T2, T3, T4 in FIG. 2 are U3, U4, as a whole as shown in FIG.
It will be delayed like U5.

In the above description, the set period (register 1
The value set to 02 to 104) is B <A, but B
In the interface which is bypassed at the timing of> A, the value set in the corresponding register can be changed, so the present invention is not limited to this.

Further, the registers 102 to 104 are connected to a data bus as shown in the figure and have a structure in which the contents can be updated. Therefore, for example, a program ROM (not shown) storing the processing procedure in the printing apparatus. Since these values can be changed simply by replacing the above, it becomes possible to flexibly deal with the case where the timings A, B, and C are accelerated, for example, when the CPU mounted in the printing apparatus is made faster.

<Explanation of Second Embodiment> FIG. 4 shows the structure of the interface section in the second embodiment.

In FIG. 4, 401 to 404 are each 8
A data latch having a bit configuration, 405 selects any one of the data latches 401 to 404 based on 2 bits (count value is 0 to 3) input from a counter 406 that counts a strobe signal. , A demultiplexer that outputs a latch signal to the selected data latch. Others are the same as the embodiment (first embodiment) described with reference to FIG. 1, and therefore description thereof will be omitted.

The feature of the second embodiment is that a 4-byte data latch is newly added to the first embodiment to act as a reception buffer. When the data strobe is input, first, the demultiplexer 405 supplies a latch signal to any one of the data latches 401 to 404 to latch the received data.
Initially, the counter value of the counter 406 is 0, so
The received data is latched in the data latch 401. The counter 406 counts up a little later, and outputs the value as "1".

Similar to the first embodiment, the timer counter 10
1 starts counting up, and similarly, the ACK signal (negative logic) and the BUSY signal are changed at the timings of B, A, and C. As a result, when the next strobe is input,
This time, the data is latched in the data latch 402, and then the counter 406 is counted up to “2”.
Further, similarly, the timer counter 101 starts, and B,
The ACK and BUSY signals change at the timings A and C, and the timer counter is reset. When the next strobe signal is input, the data is latched in the data latch 403 and the counter 406 counts up to "3". Similarly, the ACK and BUSY signals are B, A, and C.
, And the next data can be received.

Now, when the next strobe is input (4
When the second data is received), the data is latched in the data latch 404, and the received data is latched in all the data latches. That is, it means that no more data can be received. At this time, the count value of the counter 406 becomes "4", and a carry signal (a signal indicating carry) is output. Counter 406
When the carry signal (signal indicating the counter value “4”) is output to AND gate 119 and inverter 118. This has the same function as the unreceivable flag of the first embodiment. That is, at this time, the data latches 401 to 4
This means that the data held in 04 is read through the data bus and the reception is disabled until the counter is cleared by the counter clear signal.

Therefore, as in the first embodiment, if the count value of the timer counter 101 becomes B and the counter 406 is reset before the ACK signal output timing T2 or U2, the timer counter 101 counts. Re-start, 'ACK, BU at timing T2, T3, T4
The SY signal changes and the sequence ends normally. However, if the counter 406 is not cleared, that is, if the data is not read from the registers of the data latches 401 to 404, the timer counter 101 outputs the timer B at the timing U2 as in the first embodiment. A stop signal is input to the counter 101, and the counter 101 continues to stop. After that, the sequence is restarted when the counter is cleared, and ACK and B are sent at timings U3, U4, and U5.
The USY signal changes and the timer counter 101 is reset. At this time, since the counter 406 has been cleared to 0, it has returned to the initial state. Then, the preparation for receiving the next 4-byte data is completed.

FIGS. 5 and 6 show timing charts when the above processing is performed. It is needless to say that FIG. 5 corresponds to FIG. 2 and FIG. 6 corresponds to FIG.

As described above, according to the second embodiment, even a plurality of bytes of data can be automatically received at a predetermined timing without software control, and automatically when the buffer is full. It is possible to stop, wait for recovery, and restart.

Note that, for example, the CPU inside the printing apparatus has four CPUs.
Since it is possible to spend time in the internal processing until one data is received, the CP can be compared with the first embodiment.
It is possible to reduce the burden on U and the like.

It should be noted that, although the description will be mixed up, when data of 4 bytes is input to the CPU or the like, a signal to that effect is supplied. In addition, the data latches 401 to 404
If the internal data bus has, for example, 32 bits, all the data can be taken in by one reading process, which is convenient.

<Description of Third Embodiment> FIG. 7 shows the configuration of the interface section of the third embodiment. In FIG.
Reference numeral 701 is an OR gate for ORing the reception disable flag generator 121 and the timer stop signal. The other structure is the same as that of the first embodiment, and the description thereof is omitted.

The feature of the third embodiment is that the interface sequence can be stopped and restarted by a timer stop signal output from the control unit for controlling the interface circuit. The timer stop signal is generated by software executed by the CPU or the like inside the printing apparatus, and the open / close of the AND gates 113 to 115 is controlled through the AND gate 119 through the OR gate 701 and the inverter 118.

The above configuration brings about the same effect as when the reception disable flag described in the first embodiment is set. That is, the timer counter 101 changes the count value B
When the first coincidence signal is output, the stop signal is input to the timer counter 101 to stop, and the AND gate 114 masks the output of the ACK signal. In this state, wait for the timer stop signal to be reset. If reset, the timer counter 101 restarts counting, outputs an ACK signal, and executes the subsequent sequence.

FIG. 8 is a timing chart showing this operation. At the timing V1, the data strobe signal
This indicates that the timer has started and the timer stop signal has been output at timing V2. Then, at the timing V3, the timer counter outputs B, and the coincidence signal is output from the comparator 106.
However, since the timer stop signal is output, the timer counter stops here, and the sequence is stopped in this state until the timer stop signal is reset. When the timer stop signal is reset at timing V4, the ACK signal is output and at the same time the timer is restarted and the subsequent sequence is restarted. Therefore, timing V5
BUSY is reset by and the ACK signal is reset by V6. By adding such a configuration, the interface device operated by hardware can be controlled by software. Especially when data transfer is performed by hardware such as DMA transfer,
In a system in which the flag reset signal is generated by hardware, controllable by software is an effective means.

The technique disclosed in the third embodiment may be applied to the second embodiment, which is easily applicable from the above description.

<Description of Fourth Embodiment> FIG. 9 shows the configuration of the interface section in the fourth embodiment. In the figure, reference numerals 901 to 903 denote counters that output a signal when counting a predetermined count value.
The counter 901 outputs a signal at the timing of resetting the BUSY signal, the counter 902 outputs a signal at the timing of setting the ACK signal, and the counter 903
The signal is set to be output at the timing of resetting the ACK signal.

These counters start counting with a strobe signal and output the signals to the flip-flops 110 to 112 at their respective determined timings. This is the same as when the coincidence signal in the first embodiment is input to the flip-flop. Also, counters 901 to 90
3 stops when a stop signal is input from the AND gate 119. When a reset signal is input from the AND gate 117, the AND gate 117 is reset to prepare for the next strobe.

As can be seen from the above, in the fourth embodiment,
The operation is exactly the same as in the first embodiment except that the constituent elements are changed.

As described above, according to the first to fourth embodiments, the following operational effects can be obtained.

By changing the handshake output signal by the timer, the software load is lightened.

By providing a means for setting the timing of signal change, a flexible interface can be made and the connectivity with various host computers is improved.

By the means for stopping the counter after waiting until the timing of signal change when reception is not possible, there is no loss time when restarting.

By providing the stopping means from software, the hardware sequence can be controlled. When the stop signal from the software is included in the time until the first signal change, the loss time is 0.

In the embodiment, the Centro interface is adopted as the interface, and the printing device is taken as an example of the device. However, any method can be used as long as it is an interface with a host device that outputs a strobe signal in units of data to be transferred. Those skilled in the art can easily infer that the present invention is not limited to the Centro interface, and is not limited to the printing device, since it may be any one.

[0051]

As described above, according to the present invention, it is possible to perform the receiving process in the data transfer of receiving data by using the strobe signal as a trigger, without burdening the control device on the receiving side.

[0052]

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an interface unit according to a first embodiment.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the first embodiment.

FIG. 4 is a circuit configuration diagram of an interface unit according to a second embodiment.

FIG. 5 is a timing chart for explaining the operation of the second embodiment.

FIG. 6 is a timing chart for explaining the operation of the second embodiment.

FIG. 7 is a circuit configuration diagram of an interface unit in a third embodiment.

FIG. 8 is a timing chart for explaining the operation of the third embodiment.

FIG. 9 is a circuit configuration diagram of an interface unit in a fourth embodiment.

[Explanation of symbols]

Reference Signs List 101 timer counter 102 register holding BUSY reset count value 103 register holding ACK set count value 104 register holding ACK reset count value 105 to 107 comparator 108 BUSY signal generator 109 ACK signal generator 110 to 112 flip-flop 113 ~ 119 gate 120 data latch 121 unreceivable flag generator

Claims (7)

[Claims] 1. The black data transferred from a host device,
An interface device for receiving a strobe signal as a trigger, the timer device for starting timing based on the strobe signal, and a memory for storing the timing of change of one or more status signals returned to the host device. An interface device comprising: means for changing the level of the corresponding status signal when the time stored in the storage means is reached based on the time value measured by the timer means. 2. The timing data stored in the storage means is composed of a rewritable register, and can be changed to a desired value under a processing means for performing a predetermined process based on the received data. The interface device according to claim 1, wherein the interface device is provided. 3. The interface device according to claim 1, further comprising stop means for stopping the time counting of the timer means when the next data after the received data cannot be received. 4. The interface device according to claim 3, further comprising means for urging the stop means based on a signal from software by a processing means inside the apparatus. 5. The data transferred from the host device,
An interface device for receiving a strobe signal as a trigger, and a plurality of latch means for latching a unit of data sent in one data transfer; counting the number of times the strobe signal is received, and calculating the count value. Based on the strobe signal, a counting means for selecting one of the latch means for latching the received data, a timer means for starting timing based on the strobe signal, and one or more status signals to be returned to the host device. Number of storage means for storing the timing of change, and change means and latch means for changing the level of the corresponding status signal when the time stored in the storage means is reached based on the measured value by the timer means. The counting means counts a strobe signal corresponding to
An interface device comprising: stop means for stopping the timing of the timer means when the processing means in the main body of the apparatus is not fetching the data latched by the latch means. 6. The timing data stored in the storage means is composed of a rewritable register, and can be changed to a desired value by the processing means based on the received data. The interface device according to claim 5. 7. The interface device according to claim 6, further comprising means for urging the stop means based on a signal from software by the processing means.