JPH0374752A - Direct memory access restart system - Google Patents

Abstract

PURPOSE:To quickly restart the direct memory access DMA transfer at the end of an interruption process without preparing any special program by providing an instruction code comparator to perform the comparison between the instruction code transmitted on a bus line and the instruction code stored in an instruction code register. CONSTITUTION:When the DMA transfer which is interrupted by an interruption processper formed by a host device is started with reproduction control, an instruction code comparator 32 consisting of a register, etc., compares the instruction code transmitted on a bus line 10 with the instruction code stored in an instruction code register 31. Then the comparator 32 samples the instruction code of the line 10 with an instruction fetch signal and at the same time reads the contents out of the register 31 to compare the sampled instruction with the contents of the register 31. When the coincidence is obtained from the comparison, a DMA restart signal showing the validity is outputted. As a result, the DMA transfer is quickly restarted without preparing any special program.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a direct memory access restart method for controlling the restart of direct memory access transfers interrupted by interrupt processing by a host device.

(Prior Art) Direct memory access transfer is widely used when transferring large amounts of data between memory circuits. This direct memory access transfer is performed under the control of a direct memory access (DMA) restart method that performs data transfer exclusively, leaving the control of the processor that performs normal processing. In general, a printing device can be mentioned as a device that involves transferring a large amount of data. The printing device performs processing such as developing font data into image data in units of dots. During this expansion, data is transferred from the storage circuit that stores the font data to the storage circuit that stores the image data. Direct memory access transfer is used for this data transfer.

Here, a description will be given using a printing apparatus equipped with a DMA restart method as an example.

FIG. 2 is a block diagram of a conventional printing device.

In the figure, a communication control circuit 4 of a printing device 3 is connected to a host device 1 via a communication line 2.

A memory circuit (A) 5, a memory circuit (B) 6, a continuation circuit 7, and a print control circuit 8 are connected to the communication control circuit 4 via a bus line 10. An interrupt control circuit 9 is connected to the print control circuit 8 .

This interrupt control circuit 9 is also connected to the communication control circuit 4. A printer mechanical section 12 is connected to the reading circuit 7 via a mechanical section control circuit 11 .

The host device 1 is composed of a host processor and the like that controls the operation of the printing device 3. The communication line 2 is used for transmitting data, instruction codes, etc. between the host device 1 and the printing device 3. The communication control circuit 4 has a function of controlling communication between the host device 1 and the printing device 3, and converting a physical interface such as a Centronics-compliant interface or an R3232C interface into a signal that can be processed within the printing device 3. The storage circuit (A) 5 is composed of a ROM or the like that stores graphic information (font data, etc.) that can be printed by the printing device 3.

The storage circuit (B) is composed of a RAM and the like that stores graphic information (image data, etc.) to be actually printed. The sequel circuit 7 reads the graphic information stored in the storage circuit (B) at a predetermined timing and transfers it to the mechanism control circuit 11. The print control circuit 8 controls the operation of the printing device 3.

The interrupt control circuit 9 mediates a plurality of interrupt requests to the microcomputer 15. The mechanical unit control circuit 11 controls various mechanical units, such as the print head and the medium transport system, based on the image data transferred from the reading circuit 7. The printing device mechanism section 12 includes a print head, a medium transport system, and a motor, gears, etc. that drive these.

By the way, the print control circuit 8 includes a microcomputer 15, an instruction ROM 16, and a direct memory access (D
MA) circuit 17 is provided.

The microcomputer 15 includes a processor and the like that recognizes instruction codes from a host device and controls each part of the printing device 3. The instruction ROM 16 stores programs, data, etc. necessary for the operation of the microcomputer 15.

The DMA circuit 17 is provided with a DMA control circuit 18, a DMA address generation circuit 19, and a bit shift calculation circuit 20.

The DMA control circuit 18 starts and stops (interrupts) the DMA.
It controls the Furthermore, this DMA control circuit 18
A DMA stop circuit 18a is provided. This D
The MA stop circuit 18a controls the stop of DMA transfer and its subsequent restart. Bit shift calculation circuit 2
0 performs operations such as moving bit strings of data for DMA transfer.

Now, the interrupt control circuit 9 mediates a plurality of interrupt requests to the microcomputer 15. This interrupt control circuit 9 also includes a DMA stop signal generation circuit 9.
A is provided.

This DMA stop signal generation circuit 9a outputs a DMA stop signal to transfer the stop of DMA transfer to the DMA circuit 17 when an interrupt request with a higher priority than this DMA transfer occurs during execution of the DMA transfer. It is.

Note that the instruction code of the microcomputer 15 is also transmitted to the bus line 10.

FIG. 3 shows a circuit diagram of the interrupt control circuit 9.

In the figure, the interrupt control circuit 9 includes an inverter 21a,
2lb, 21c, and off gate 22a.

22b, 22c, and a Noah gate 23a.

Note that the DMA stop signal generation circuit 9a has a NOR gate 23.
It is composed of a.

Now, the interrupt request 1 output from the communication control circuit 4 is input to the input terminal IN+. Similarly, the input terminals IN2 to IN4 are connected to other circuits other than the communication control circuit 4, such as the continuous circuit 7.
Interrupt requests 2 to 4 from the mechanism control circuit 11 and the like are input. Regarding the priority of each interrupt request, interrupt request 1 has the highest priority, and priority decreases in order of interrupt request 2, interrupt request 3, and interrupt request 4. Then, each request signal is sent to the output terminal OUT+ only when a request with a higher priority is not issued.
~OUT, is output. The request signal output to this output terminal is input to an interrupt terminal of the microcomputer 15.

Now, the DMA stop signal generation circuit 9a outputs a DMA stop signal when interrupt request 1 or interrupt request 2 is issued. This DMA stop signal is input to the DMA control circuit 18.

FIG. 4 shows a part of the circuit diagram of the DMA control circuit 18.

In the figure, the DMA control circuit 18 includes a flip-flop (JK flip-flop) 24 and OR gates 25a to 25A.
25g and inverters 26a to 26c.

Note that the DMA stop circuit 18a is connected to the OR gates 25a to 2.
5d and a flip-flop 24.

Now, DMA requests 1 to 4 are input to the DMA control circuit 18 via the bus line 10. Further, a DMA stop signal output from the DMA stop signal generation circuit 9a is input to the J terminal of the flip-flop 24. Further, a DMA restart signal generated by a command from the microcomputer 15 is input to the K terminal. A clock that controls the timing of its operation is input to this flip-flop 24.

The DMA request 1 to 4 signals are signals outputted by the program instructions of the microcomputer 15.

These signals are output when a program instruction is executed, and after a DMA request signal can be generated by executing a program instruction, a change in an external event (
There are some that are triggered by paper feed detection, etc.).

Furthermore, when restarting a DMA transfer that has been stopped by a DMA stop signal, the microcomputer 15 outputs a DMA restart signal according to a program instruction.

The priority of each DMA request is as follows: DMA request 1 has the highest priority, D
The priority decreases in order of MA request 2, DMA request 3, and DMA request 4. Then, each request signal is sent to the output terminal O only when a request with a higher priority is not issued.
It is output as DMA permissions 1 to 4 to UT+ to OUT. This permission signal is input to the DMA control circuit 18, and the DMA
In the control circuit 18, the microcomputer 1
At the same time, the DMA address generation circuit 19 and the bit shift calculation circuit 20 are activated based on the data necessary for processing related to DMA transfer set by the program instruction No. 5, such as information such as read destination and write destination.
from the microcomputer 15. D
The MA control circuit 18 includes a DMA address generation circuit 19,
The bit shift calculation circuit 20 is driven to start a predetermined DMA transfer.

Note that when the output of the flip-flop 24 (the level of the Q terminal) of the DMA stop circuit 18a is low level, any D
In response to the MA request, the output of one of the OR gates 25a to 25d becomes low level, and the DMA permission becomes valid (
low level). Also, flip-flop 2
When the output of 4 is high level, OR gates 25a to 25d
The output is kept at high level. Therefore, DMA permission is set to an invalid state (high level).

When the output of the flip-flop 24 is at a low level, the J terminal is set at a low level and the K terminal is set at a high level. Further, when the output of the flip-flop 24 is at a high level, the J terminal is set at a high level and the K terminal is set at a low level.

That is, when the DMA stop signal is at low level, DMA transfer is possible. This means that, as explained in FIG. 3, when interrupt request 1 occurs, DMA transfer is interrupted. This means that when interrupt request 1 occurs, the DMA
This is because the output level of the stop signal generation circuit 9a becomes high level.

By the way, the DMA restart signal takes a level that is opposite to the level of the DMA stop signal. That is, it is kept at a high level while a DMA transfer is being executed, and is kept at a low level while a DMA transfer is stopped.

(Problems to be Solved by the Invention) Now, a process of stopping the DMA transfer while it is being executed and restarting the DMA transfer will be described.

For example, in response to a request from the microcomputer 15, the font data in the memory circuit (A) is referenced and
) is expanded by image data or MA. In this case, the output of the flip-flop 24 of the DMA stop circuit 18a is set to low level. Here, data is transferred from the host device 1, and the communication control circuit 4 outputs an interrupt request 1 to the interrupt control circuit 9. As a result, the DMA stop signal generation circuit 9a outputs a high level DMA stop signal. At the same time, an interrupt signal corresponding to interrupt request 1 is input to microcomputer 15. Since the DMA restart signal is normally at a low level, the output of the flip-flop 24 of the DMA stop circuit 18a is at a high level. Along with this, the DMA control circuit 18
All DMA grants output from are set to an invalid state. Furthermore, the DMA control circuit 18 temporarily saves (stores) data related to the DMA transfer to be stopped, for example, parameters indicating the progress status of the DMA transfer, in an internal storage circuit provided within the DMA control circuit 18, and then stops the DMA transfer. Stop. Thereafter, the microcomputer 15 starts occupying the bus line 10 in order to process the information received by the communication control circuit 4, and predetermined data transfer and the like are executed.

Now, when the communication control circuit 4 releases the occupation of the bus line 10, that is, when the predetermined interrupt processing is completed, it sets the interrupt request 1 to an invalid state. As a result, the DMA stop signal output from the DMA stop signal generation circuit 9a is set to low level.

When the microcomputer 15 recognizes that the interrupt request 1 is set to an invalid state, the microcomputer 15 downloads the DMA from the instruction ROM 16.
Execute the restart program one after another. As a result, the microcomputer 15 outputs a high-level DMA restart signal to the flip-flop 24 of the DMA stop circuit 18a.

The output of flip-flop 24 is again set to a low level, granting DMA permission corresponding to any of DMA requests 1-4. The DMA control circuit 18 restarts the DMA transfer in accordance with the contents when DMA permission is granted for the previous parameter.

Now, as explained above, conventionally, when restarting a DMA transfer after it has been stopped, the microcomputer 15 had to execute a program to output a DMA restart signal. Therefore, even if the bus line 10 is no longer occupied by the communication control circuit 4, the DM
A transfer could not be restarted, causing a delay in program execution. This has been an obstacle to quickly completing the DMA transfer. Also, when restarting DMA transfer, D
A program for outputting the MA restart signal must be specially prepared in response to the interrupt request output by the interrupt control circuit 9, which creates a problem that the structure of the software stored in the instruction ROM 16 becomes complicated. was. Also, instruction ROM1
When creating a program to be stored in 6, consideration regarding DMA restart results in an increase in constraints when creating the program.

The present invention has been made with attention to the above points, and there is no need to prepare a special program, and furthermore, when the interrupt processing that caused the DMA transfer to stop is completed, the DMA transfer can be promptly resumed. The purpose of this invention is to provide a direct memory access restart method that can realize the following.

(Means for Solving the Problems) The direct memory access restart method of the present invention provides, in an information processing device having a microcomputer and a direct memory access circuit in its control circuit, when the microcomputer and the direct memory access circuit are in operation. an interrupt control circuit that issues an interrupt request to the microcomputer when processing by the computer is required and it is necessary to stop the direct memory access operation;
a command monitoring circuit that recognizes the end of occupation of the bus line by the host device and instructs the direct memory access control circuit to restart the direct memory access transfer that received the stop instruction; The circuit includes an instruction code register that stores in advance an instruction code indicating the end of interrupt processing, and an instruction code that compares the instruction code transmitted on the bus line with the instruction code stored in the instruction code register. A comparison circuit is provided, and if the comparison result is a match, the instruction code comparison circuit issues the restart instruction to the direct memory access control circuit, and the direct memory access control circuit receives the restart instruction. In this case, the direct memory access transfer that received the stop instruction is restarted.

(Operation) In the above method, the instruction code register of the instruction monitoring circuit is
An instruction code indicating the end of interrupt processing is stored in advance. The instruction code comparison circuit compares the contents of the instruction code with the instruction code stored in the instruction code register every time the instruction code is transmitted to the bus line. If the result of this comparison is a match, an instruction to resume direct memory access transfer is issued to the direct memory access control circuit. As a result, the direct memory access control circuit resumes the previously stopped direct memory access transfer.

(Embodiment) Here, a direct memory access (DMA) restart method of the present invention will be explained using a printing apparatus as an example.

FIG. 1 shows a block diagram of a printing apparatus according to the DMA restart method of the present invention.

In the figure, a communication control 4 of a printing device 3 is connected to a host device 1 via a communication line 2. A memory circuit (A) 5, a memory circuit (B) 6, a printout circuit 7, a print control circuit 8, and an instruction monitoring circuit 30 are connected to the communication control circuit 4 via a bus line 10. An interrupt control circuit 9 is connected to the print control circuit 8 . This interrupt control circuit 9 is also connected to the communication control circuit 3. A printer mechanical section 12 is connected to the continuous output circuit 7 via a mechanical section control circuit 11 .

The higher-level device 1 is composed of a higher-level processor and the like that controls the operation of the printing device 3. The communication line 2 is used for transmitting data, instruction codes, etc. between the host device 1 and the printing device 3. The communication control circuit 4 has a function of controlling communication between the host device 1 and the printing device 3, and converting a physical interface such as a Centronics-compliant interface or an R3232C interface into a signal that can be processed within the printing device 3. The storage circuit (A) 5 is composed of a ROM or the like that stores graphic information (font data, etc.) that can be printed by the printing device 3.

The storage circuit (B) is composed of a RAM and the like that stores graphic information (image data, etc.) to be actually printed. The continuation circuit 7 performs continuation of the graphic information stored in the memory circuit CB) at a predetermined timing and transfers it to the mechanism control circuit 11. The print control circuit 8 controls the operation of the printing device 3.

The interrupt control circuit 9 mediates a plurality of interrupt requests to the microcomputer 15. The mechanical unit control circuit 11 controls various mechanical units, such as the print head and the medium transport system, based on the data transferred from the reading circuit 7. The printing device mechanism section 12 includes a print head, a medium transport system, and a motor, gears, etc. that drive these.

By the way, the print control circuit 8 includes a microcomputer 15, an instruction ROM 16, and a direct memory access (D
MA) circuit 17 is provided.

The microcomputer 15 includes a processor and the like that recognizes instruction codes from a host device and controls each part of the printing device 3. The instruction ROM 16 stores programs, data, etc. necessary for the operation of the microcomputer 15.

The DMA circuit 17 is provided with a DMA control circuit 18, a DMA address generation circuit 19, and a bit shift calculation circuit 2o.

The DMA control circuit 18 starts and stops (interrupts) the DMA.
It controls the Note that this DMA control circuit 1
8 is provided with a DMA stop circuit 18a. This DMA stop circuit 18a controls the stop of DMA transfer and its subsequent restart. The bit shift arithmetic circuit 20 performs arithmetic operations such as moving a bit string of data for DMA transfer.・DMA control circuit 18
The configuration is the same as the conventional one explained earlier in FIG.

Now, the interrupt control circuit 9 mediates a plurality of interrupt requests to the microcomputer 15. This interrupt control circuit 9 also includes a DMA stop signal generation circuit 9.
A is provided.

This DMA stop signal generation circuit 9a outputs a DMA stop signal to transfer the stop of DMA transfer to the DMA circuit 17 when an interrupt request with a higher priority than this DMA transfer occurs during execution of the DMA transfer. It is. The configuration of this interrupt control circuit 9 is also the same as that described above with reference to FIG.

The instruction monitoring circuit 30 monitors instruction codes transmitted on the bus line lo.

FIG. 5 shows a block diagram of the instruction monitoring circuit 30 according to the present invention.

The instruction monitoring circuit 30 includes an instruction code register 31 and an instruction code comparison circuit 32. The instruction code register 31 and the instruction code comparison circuit 32 are each connected to the bus line 10. Further, the instruction code register 31 and the instruction code comparison circuit 32 are connected by an internal bus line 33.

The instruction code comparison circuit 26 includes a microcomputer 1
An instruction fetch signal is input from 5, and a DMA restart signal is further output to the DMA stop circuit 18a.

The instruction code register 31 stores, for example, RT I (R
It is made up of several-bit registers that store instruction codes such as (eturn from interrupt) instructions. The instruction code comparison circuit 32 is composed of a register and the like that compares the instruction code transmitted on the hash line 10 and the instruction code stored in the instruction code register 31. This instruction code comparison circuit 26 is connected to the bus line 10 by the instruction fetch signal.
At the same time as the upper instruction code is sampled, its contents are successively output from the instruction code l/raster 31 and the two are compared. If the result of this comparison is a match, a DMA restart signal indicating validity is output.

Now, let's go back to FIG. 1 and explain.

Now, from the microcomputer 15 to the instruction monitoring circuit 30
The instruction fetch signal transmitted to the microcomputer 15 is a signal output as a response signal when the microcomputer 15 receives some instruction code. That is, when this fetch signal is output, it means that some instruction code is being transmitted on the bus line 10. For example, when the microcomputer 15 declares the end of a previously accepted interrupt process, it sends an RTI command onto the bus line lo and simultaneously outputs a fetch signal. The instruction monitoring circuit 30 compares the instruction code transmitted on the bus line 10 and the instruction code stored in the instruction code register 31. If the results do not match, a DMA restart signal indicating invalidity is output.

If it is valid, it outputs a DMA restart signal indicating validity. The DMA stop circuit 18a performs predetermined control by accepting this DMA restart signal.

Here, DMA transfer according to the present invention will be explained with reference to FIG.

FIG. 6 is a time chart showing the operation of the present invention.

Here, a case is shown in which the DMA transfer that was being executed upon receiving the DMA permission 1 signal is stopped (interrupted) and then restarted.

FIG. 6(a) is a waveform diagram showing the output timing of the instruction fetch signal. FIG. 2B is a waveform diagram of data transmitted on the bus line 10. FIG. FIG. 3(c) is a waveform diagram of the DMA restart signal output from the instruction monitoring circuit 30. FIG. 4D is a waveform diagram of the clock input to the flip-flop 24 (FIG. 4) of the DMA stop circuit 18a. FIG. 4(e) is a waveform diagram of DMA permission 1 output from the DMA control circuit 18.

Now, in the figure, when the instruction fetch signal F is output (FIG. 6(a)), an instruction code is transmitted on the bus line 10 (FIG. 6(b)). In this case “MOV
Assume that an instruction code such as "A, B" is transmitted. This instruction code is sampled by the instruction code comparison circuit 32 of the instruction monitoring circuit 30 and compared with the contents of the instruction code register. In this case, a mismatch is detected. As a result, the DMA restart signal is set to low level (invalid state).Therefore, even if a clock is input to the flip-flop 24 (FIG. 6(d)), the level of DMA permission 1 is not converted (the 6(e)).This is because the output of the flip-flop 24 is kept at a high level.

Next, when the interrupt processing is completed, the microcomputer 15 outputs the fetch signal F (see FIG. 6(a)).
), the code of the RTI command is transmitted on the bus line 10 (FIG. 6(b)). The instruction code comparison circuit 32 of the instruction monitoring circuit 30 samples the instruction code of this RTI instruction. As a result, the instruction code comparison circuit 32 outputs a high-level (valid state) DMA restart signal (FIG. 6(C)). On the other hand, the circuit that had issued the interrupt request withdraws the request. Interrupt control circuit 9
The DMA stop signal from is set to low level (invalid state).

Now, the flip-flop 24 of the DMA stop circuit 18a outputs its output (Q
terminal) changes to low level. Then, DMA permission 1, which was stopped first, is set to low level (enabled state) (
Figure 6(e)).

As a result, the DMA control circuit 18 recognizes the previously saved parameters and restarts the DMA transfer.

FIG. 7 shows a flowchart according to the present invention.

First, the microcomputer 15 issues an instruction to the DMA control circuit 18 to execute DMA (step S
2). The microcomputer 15 determines whether there is an interrupt request 1 (step S2). This result is NO
In this case, the process moves to step S3. In step S3,
The DMA control circuit 18 determines whether the DMA transfer is completed. If the result is YES, the process ends; if the result is NO, the process returns to step S2.

Now, if the result of step S2 is YES, the DMA
The transfer is stopped, and the communication control circuit 4 executes information processing, ie, data transfer that occupies the bus line 10 (step S4). Then, the instruction monitoring circuit 30 causes the RT
It is determined whether or not the I command has been output (step S5). If the result is YES, the command monitoring circuit 3
0 outputs a DMA restart signal, restarts the previously stopped DMA transfer, and moves to step S2. If the result of step S5 is NO, the output of the RTI command is continued to be monitored.

The DMA restart method of the present invention is not limited to the above embodiments.

In the embodiment, the case where the present invention is installed in a printing device is explained as an example, but if the DMA transfer is stopped due to interrupt processing and then restarted, the present invention is not limited to the printing device, but can also be applied to, for example, a general computer system. I can do it.

Also, the instruction code for recognizing the end of interrupt processing is RTI.
It is not limited to commands, and may be anything that indicates that the interrupt processing has ended.

(Effects of the Invention) As described above, according to the present invention, there is no need to run a specially prepared program for restarting DMA transfer, and the DMA transfer is restarted by recognizing the end of interrupt processing. The delay time from the end of interrupt processing to the restart of DMA transfer can be significantly reduced. Further, since there is no need to prepare a special program for restarting DMA transfer, it is possible to simplify the program stored in the instruction ROM. Furthermore, it also reduces restrictions when creating programs.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a printing device according to the present invention, Fig. 2 is a block diagram of a conventional printing device, Fig. 3 is a circuit diagram of an interrupt control circuit, and Fig. 4 is a circuit diagram of a DMA control circuit. Part, 5th
6 is a block diagram of an instruction monitoring circuit according to the present invention, FIG. 6 is a flow chart showing the operation of the present invention, and FIG. 7 is a flow chart according to the present invention. DESCRIPTION OF SYMBOLS 1... Host device, 4... Communication control circuit, 5... Memory circuit (A), 6... Memory circuit (B), 7... Successive circuit, 8... Print control circuit, 9...Interrupt control circuit, 9a...DMA stop signal generation circuit, 15...Microcomputer, 6...Instruction ROM, 18.DMA control circuit, 8a...
- DMA stop circuit, 9... DMA address generation circuit, O... bit shift calculation circuit, O... instruction monitoring circuit, 1... instruction code register, 2... instruction code comparison circuit. Fig. 3 18aoM#KyotoguchitaiDMAM$ITh[WKFig.

Claims (1)

[Scope of Claims] In an information processing device having a microcomputer and a direct memory access circuit in its control circuit, while the direct memory access circuit is operating, processing by the microcomputer is required and the direct memory access operation is stopped. an interrupt control circuit that issues an interrupt request to the microcomputer when it is necessary to perform an interrupt; an instruction monitoring circuit that issues a restart instruction to the direct memory access control circuit; the instruction monitoring circuit includes: an instruction code register that stores in advance an instruction code indicating the end of interrupt processing; and an instruction code register that is transmitted over the bus line. an instruction code comparison circuit that compares an instruction code stored in the instruction code register with an instruction code stored in the instruction code register, and if the comparison result is a match, the instruction code comparison circuit The direct memory access restart method is characterized in that the direct memory access control circuit issues the restart instruction to a circuit, and when the direct memory access control circuit receives the restart instruction, restarts the direct memory access transfer that received the stop instruction. .